DESCRIPTION (COMPLETE)
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We Claim:
1. In a computer apparatus having a processor (102), a system memory (106), a flash memory (108), a memory controller (104), wherein said apparatus comprises:
a memory means/window detector (110) coupled to said processor (102), said memory controller (104), a first input of a first logic gate (122) and a first input of a second logic gate (124), said first logic gate having an output coupled to said memory controller and said second logic gate having a second input for receiving a system memory access enable signal;
a memory window control (114) coupled to said system memory, said memory controller, said flash memory, said memory means/window detector, an output of a third logic gate and a first input of a fourth logic gate, said fourth logic gate having a second input for receiving a flash memory programming enable signal;
a system memory access enable register (112) coupled to an output of said second logic gate (124), a second input of said first logic gate, and an input of said third logic gate (126) ; and
a flash memory programming enable register (118) coupled to an output of said fourth logic gate;
a flash memory programming circuit coupled to said flash memory programming enable register and said flash memory.
2 The apparatus as claimed in claim 1, wherein said first logic gate is an OR gate.
3. The apparatus as claimed in claim 1, wherein said second logic gate is an AND gate.
4 The apparatus as claimed in claim 1, wherein said third logic gate is a
NOT gate.
5 The apparatus as claimed in claim 1, wherein said fourth logic gate is
an AND gate.

6. The apparatus as claimed in claim 1, wherein said system memory
includes a cache memory.
7. The apparatus as claimed in claim 1, wherein said memory window
control includes a set of registers.
8. The apparatus as claimed in claim 1 wherein said set of registers
includes a base register and a limit register.
9. A method for preventing unauthorized modification of flash memory
with computer apparatus as claimed in claim 1 comprising the steps
of:
loading a flash memory upgrade program containing a new flash memory image and a digital signature into a portion of said system memory;
configuring said memory controller to limit said processor to
accessing only said flash memory and said portion of said system
memory;
verifying said flash memory update program using said digital
signature; and
updating said flash memory only if said flash memory upgrade
program is authentic.
10. The method as claimed in claim 9, wherein said loading step
comprises:
loading said flash memory update program into a set of addresses
contained in said system memory, said set of addresses having a
starting address and a length;
loading a base register with said starting address; and
loading a limit register with said length.
11. The method as claimed in claim 10, wherein said configuring step
comprises: providing a memory access disable signal to said memory
controller; setting a memory address window detector to generate a
memory access enable signal to said memory Controller.
12. The method as claimed in claim 11, wherein said configuring step
comprises, providing a cache access disable signal to said memory
controller and said processor.
13. The method as claimed in claim 9, wherein said verifying step
comprises the steps of:
decrypting said digital signature to obtain an original hash value; calculating an independent hash value for said flash memory update program; and
comparing said original hash value and said independent hash value to determine a match.
14. The method as claimed in claim 9, wherein said updating step
comprises:
setting a flash memory programming enable register to enable programming of said flash memory; and executing said flash memory upgrade program.
15. A method substantially as herein described with reference to and as
illustrated in the foregoing description and accompanying drawings.