APPARATUS FOR SYNCHRONIZING UNINTERRUPTIBLE POWER SUPPLIES CROSS REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application Serial No. 60/647,661, filed January 27, 2005, which is incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION The present disclosure relates generally to uninterruptible power supplies (UPSs), and particularly to synchronization control systems for control thereof. UPSs are employed in a variety of applications where a constant source of power is desired at a load. A typical UPS system involves an inverter feed path, also generally referred to as the inverter, that is operably connectable in parallel with a bypass feed path, also generally referred to as the mains. The mains may be connected to a utility-, but may also receive power from some other supply not connected to a utility electrical grid. The inverter may receive power from the same source as the mains, but may also receive power from some other supply. There are several types of UPSs depending on their operation mode. Double conversion UPSs offer the maximal protection level as the load is always fed by the inverter. On the other hand, with line-interactive UPSs, the load is fed by the mains and the inverter is used to correct the shape of the load voltage. There are also several possible UPS configurations to supply a critical load, such as Redundant Parallel Architecture (RPA), Dual Independent Configuration, Load Bus Synchronization, and Power Tie, for example. With the RPA concept, (N+M) UPSs are paralleled to supply a load that can be fed by N UPSs only. This way, a redundancy of M units is achieved. More and more, and for high availability, Dual Independent Configurations are requested by customers. This requires the synchronization of two independent UPS groups and the use of an Intelligent Static Switch (ISS) that automatically switches the critical load from one source to the other. Another concept is Load Bus Synchronization where two independent UPS groups can be temporarily synchronized in order to move the critical load from one side to the other for maintenance purposes. An extension of the Load Bus Synchronization concept is the Power Tie concept, where the two independent UPS groups are permanently synchronized and their load shared as if they were a unique UPS group in a RPA configuration. Finally, and with consideration to the bypass configuration, it is desirable to be able to choose between two different options, a centralized bypass or decentralized bypass. Accordingly, there is a need in the art for a control system and apparatus that allows multiple configurations of UPSs in critical power management systems. BRIEF DESCRIPTION OF THE INVENTION An embodiment of the invention includes an Intelligent Synchronization Module (ISM) for an Uninterruptible Power Supply (UPS) system for servicing a load, wherein the UPS system has at least one of a first UPS group and a second separate and independent UPS group, each of the first and second UPS groups having a master UPS. The ISM has a processing circuit and a storage medium, readable by the processing circuit, storing instructions for execution by the processing circuit for: assigning the first UPS group the role of master group and the second UPS group the role of slave group; and, passing phase information relating to the master group to the slave group, thereby enabling the master UPS of the slave group to effect synchronization with the master group. Another embodiment of the invention includes an Uninterruptible Power Supply (UPS) system for servicing a load. The UPS system includes a first UPS group and a second UPS group separate from and independent to the first UPS group, each of the first and second UPS groups being configured to service the load, and an Intelligent Synchronization Module (ISM) in signal communication between the two ITS groups. The ISM is configured to assign the first UPS group the role of master group and the second UPS group the role of slave group, and to pass phase information relating to the master group to the slave group, thereby enabling the slave group to effect synchronization with the master group. BRIEF DESCRIPTION OF THE DRAWINGS Referring to the exemplary drawings wherein like elements are numbered alike in the accompanying Figures: Figure 1 depicts an exemplary block diagram of a double conversion UPS system for use in accordance with an embodiment of the invention; Figure 2 depicts the exemplary UPS system of Figure 1 in expanded Wetail; Figure 3 depicts an exemplary intelligent synchronization module (ISM) in combination with two groups of UPSs in accordance with an embodiment of the invention; ' Figure 4 depicts an exemplary intelligent synchronization module (ISM) in accordance with embodiments of the invention; Figures 5-10 depict alternative exemplary configurations for employing the ISM of Figure 4 in accordance with an embodiment of the invention; and Figures 11-13 depict exemplary control algorithms for use in accordance with embodiments of the invention. DETAILED DESCRIPTION OF THE INVENTION An embodiment of the invention provides an Intelligent Synchronization Module (ISM) for allowing multiple configurations of an Uninterruptible Power Supply (UPS) system that services at least one load. In an embodiment, the UPS system has a first UPS group and a second separate and independent UPS group, with each of the first and second UPS groups having a master UPS. A function of the ISM is to assign the first UPS group the role of master group and the second UPS group the role of slave group, and to pass phase information relating to the master group to the slave group, thereby enabling the master UPS of the slave group to effect synchronization with the master group. In a more general sense, the ISM is a control system that exchanges information, performs synchronizations, and executes control algorithms and commands. Figure I shows an exemplary block diagram of a typical double conversion UPS system 100. The UPS system 100 consists of two converter blocks, a rectifier 130 and an inverter 140, and energy storage device 135 such as a battery for example. During normal operation, the rectifier 130 converts the mains input supply 112 to regulated DC to charge the energy storage- battery bank 135 as well as supply power to the inverter 140. The inverter 140 converts the DC to a voltage and frequency regulated AC output at all times. During a stored energy mode, that is, during a condition where the mains input supply 112 is not available, the inverter 140 draws power from the energy storage device 135, thereby enabling continued supply the output or load 105. Bypass operation is possible through a Static Switch Module (SSM) 120. Figure 2 expands on the schematic of Figure 1 to show further detail of the exemplary UPS system 100 that services the load 105. Here, the UPS 100 includes a bypass feed path 110 and an inverter feed path 115 that are operable in parallel with each other during the transfer of power from one path to the other. The power source 112 for the bypass feed path 110 may be a utility or other main power source, as discussed previously. The power source 117 for the inverter feed path 115 may be the same as that of the bypass feed path 110 (as illustrated in Figure 1 for example), or it may be a different power source (as illustrated in Figure 2 for example). The bypass feed path 110 is engagable with the load 105 via the SSM 120, also herein referred to as a first switch 120, to deliver a bypass current to the load 105, and the inverter feed path 115 is engagable with the load 105 via a second switch 125 to deliver an inverter current to the load 105. In an embodiment, the first switch 120 is a remote controllable SSM of a type known to one skilled in the art, and the second switch 125 is a remote controllable contactor of a type known to one skilled in the art. The inverter feed path 115 includes the rectifier 130, the battery 135, and the inverter 140, and may also include an output isolation transformer 145, and filtering capacitors 150. Disconnect switches (K4) 155, (K6) 160, (Ql) 165 and (Q2) 170 may be employed for additional protection and/or control and/or maintenance. In an embodiment, switches (K4) 155 and (K6) 160 are circuit breakers, and switches (Ql) 165 and (Q2) 170 are manual disconnects. The leakage inductance of isolation transformer 145 and the output capacitors 150 are used together to filter the inverter output voltage (Uo) 200. While Figure 1 depicts a UPS 100 in one-line diagram form, it will be appreciated that UPS 100 may have multiple phases, such as three phases for example, and that any reference herein to a current or a voltage in one phase is intended to be a reference to the current and voltage of each phase. In an embodiment, a control system 175, illustrated generally in Figure 1 and more specifically in Figure 2, includes a processing circuit 180 and a storage medium 185, readable by the processing circuit 180, storing instructions for execution by the processing circuit for controlling the UPS 100 in a manner to be described in more detail below. In an embodiment, input signals to control system 175 include inverter bridge currents (Ib) 190, inverter Joad currents (IL) 195, inverter output voltages (Uo) 200, load voltages (UL) 205, bypass load currents (Ibyp) 210, and bypass input voltages (Ubyp) 215, that are generated by any sensor suitable for the intended purpose. Another input signal to control system 175 may be (aux) 220 that is provided by an auxiliary contact (not specifically shown but represented also by reference numeral 220) at second switch (K7) 125 and identifies the on/off state of the main contacts of second switch 125. Further input signals to control system 175 include a Ssync signal and a o of the oscillator 434, which refer to the master UPS of the slave UPS group. The fast synchronization algorithm 450 is illustrated in Figure 13 with its control variables illustrated. As depicted, algorithm 450 primarily consists of three modules: a phase & frequency error computation module 451; a fast phase control 452 with its own control parameters; and, an oscillator (O) 453. This fast synchronization algorithm 450 serves to keep the two UPS groups A and B synchronized. Similar to the slow synchronization algorithm 430, the input to the fast synchronization algorithm 450 is cpisM_othen which again is the actual phase of the master UPS group, and the outputs are the phase and frequency parameters ao and o>o of the oscillator 434, which again refer to the master UPS of the slave UPS group. In an embodiment, the slow 430 and fast 450 synchronization algorithms are implemented in firmware, having algorithms driven by control equations, which will now be discussed with reference to Figures 12 and 13. The FFO 43J1 depicted in Figure 12 includes an internal oscillator having a phase angle (pOsc and an angular frequency (DOSC- This internal oscillator is controlled to track the phase angle (pisM_other- Once the oscillator is synchronized to q>ISM other the oscillator angular frequency o>osc *s a measure for the unknown angular frequency o>isM_other- This is why this block is called fast frequency observer. The equations describing the above algorithm are: Atposc = 9isM_other - osc + Acoosccom* TE Equa.-5 0 = o>0 + Aco * T|: Equa.-15 cx0 = ot0 + con * TI; Equa.- 1 6 In a classical digital PLL (phase lock loop) scheme, the synchronization precision of 10 bits of digital phase information would be too a low resolution for proper synchronization control. However, with the slow and fast synchronization algorithms disclosed herein, a synchronization precision of less than Ijis maybe achieved. Since only the digital phase information is sent on the communication bus between the ISM and the UPS groups, it is possible to optimize the bandwidth of the transmission. Also, since the slow synchronization algorithm needs the frequency information (see Figure 12 for example), this information may be extracted from the phase information through an FFO (fast frequency observer) 43 1 .In an embodiment, the slow and fast synchronizations depicted in Figures 12 and 13 are implemented using the same algorithm, with the only difference being the feedback gains obtained by assigning different poles to the phase control. Accordingly, different feedback gains lead to different synchronization speed and stiffness. To determine an appropriate feedback gain, the static stiffness may be defined with respect to the phase and frequency errors. Exemplary relationships are as follows. For slow synchronization, the static stiffness with respect to a frequency error is 16 Hz/sec correction for an error of 1 Hz, and the static stiffness with respect to the phase error is 18/(27i) = 3 Hz/s correction for an error of Irad, for example. For fast synchronization, the static stiffness with respect to the frequency error is 20 Hz/s correction for an error of IHz, and the static stiffness with respect to the phase error is 100/(2n) « 16 Hz's correction for an error of Irad, for example. By assigning different poles to the phase control, it is possible to design a fast and a slow phase control, thereby obtaining two sets of feedback gains. As used herein, the following variable definitions apply: 9iSM_other = phase angle to synchronize to (phase angle of the "supermaster") Mother = angular frequency of the "supermaster" (cp and co are linked by co=dcp/dt) coa = angular frequency of the oscillator (of the master of the "superslave" group) a0 = phase angle of the oscillator (of the master of the "superslave" group) = phase angle error (between the "supermaster" and "superslave" groups) = angular frequency error (between the "supermaster" and "superslave groups) AOJ = singular frequency correction to be applied to the oscillator = feedback gain for the phase angle error - slow synchronization = feedback gain for the angular frequency error - slow synchronization K