WE CLAIM:
1. A processor compri sing:
a decoder to decode an instruction to zero a cache line;
an execution unit, coupled to the decoder and responsive to the decode of the
instruction, to issue a write command to initiate a cache line sized write of zeros at a memory address;
a coherent cache, coupled to the execution unit, to receive the write command, to
determine whether there is a hit in the coherent cache responsive to the write command, to determine whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros when the cache coherency protocol state is the modified state or the exclusive state, and to issue the write command toward an interconnect when there is a miss responsive receiving to the write command;
the interconnect, responsive to receipt of the write command, to issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit, wherein the interconnect, or the execution unit responsive to a message from the interconnect, to cause a cache line in one of the coherent caches to be configured to indicate all zeros when the write command and the snoop did not cause the cache line sized write of zeros to be performed.
2. The processor of claim 1, wherein the coherent cache is also to make that cache line's cache coherency protocol state be an invalid state and issue the write command toward the interconnect when the cache coherency protocol state of the hit cache line is not the modified state or the exclusive state.
3. The processor of claim 1, wherein the decoder and the execution unit are part of a first core, and wherein the plurality of coherent caches includes a coherent cache of a second core.
4. A processor comprising:
a decoder to decode an instruction to zero a cache line;
an execution unit, coupled to the decoder, to issue a command responsive to the decode of the instruction;

a interconnect, responsive to receipt of the command, to issue a snoop to each of a plurality of coherent caches for which it must be determined if there is a hit, wherein the execution unit on its own, the interconnect, or the execution unit responsive to a message from the interconnect, to cause a cache line in one of the plurality of coherent caches coupled to the execution unit to be configured to indicate all zeros when the snoop did not cause the cache line write of zeros to be performed.