Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described. In one embodiment, a processor includes a matrix operations accelerator circuit that includes a two-dimensional grid of fused multiply accumulate circuits that is switchable to a scheduling mode for execution of a decoded single instruction where the matrix operations accelerator circuit loads a first buffer of the two-dimensional grid of fused multiply accumulate circuits from a first plurality of registers that represents a first input two-dimensional matrix, checks if a second buffer of the two-dimensional grid of fused multiply accumulate circuits stores an immediately prior input two-dimension matrix that is the same as a second input two-dimensional matrix from a second plurality of registers that represents the first input two-dimensional matrix, and when the second buffer of the two-dimensional grid of fused multiply accumulate circuits stores the immediately prior input two-dimension matrix, from execution of a previous instruction, that is the same as the second input two-dimensional matrix: prevents reclamation of the second buffer between execution of the previous instruction and the decoded single instruction, performs an operation on the first input two-dimensional matrix from the first buffer and the immediately prior input two-dimension matrix from the second buffer to produce a resultant, and stores the resultant in resultant storage, and when the second buffer of the two-dimensional grid of fused multiply accumulate circuits does not store the immediately prior input two-dimension matrix, from execution of the previous instruction, that is the same as the second input two-dimensional matrix: loads the second input two-dimensional matrix into the second buffer of the two-dimensional grid of fused multiply accumulate circuits, performs the operation on the first input two-dimensional matrix from the first buffer and the second input two-dimension matrix from the second buffer to produce a resultant, and stores the resultant in the resultant storage.
| # | Name | Date |
|---|---|---|
| 1 | 202044039434-FORM 1 [11-09-2020(online)].pdf | 2020-09-11 |
| 2 | 202044039434-DRAWINGS [11-09-2020(online)].pdf | 2020-09-11 |
| 3 | 202044039434-DECLARATION OF INVENTORSHIP (FORM 5) [11-09-2020(online)].pdf | 2020-09-11 |
| 4 | 202044039434-COMPLETE SPECIFICATION [11-09-2020(online)].pdf | 2020-09-11 |
| 5 | 202044039434-FORM-26 [04-11-2020(online)].pdf | 2020-11-04 |
| 6 | 202044039434-FORM 3 [11-03-2021(online)].pdf | 2021-03-11 |
| 7 | 202044039434-FORM 18 [21-07-2021(online)].pdf | 2021-07-21 |
| 8 | 202044039434-FORM 3 [14-09-2021(online)].pdf | 2021-09-14 |
| 9 | 202044039434-FER.pdf | 2024-02-14 |
| 10 | 202044039434-FORM 3 [15-04-2024(online)].pdf | 2024-04-15 |
| 11 | 202044039434-Information under section 8(2) [29-04-2024(online)].pdf | 2024-04-29 |
| 12 | 202044039434-Proof of Right [09-08-2024(online)].pdf | 2024-08-09 |
| 13 | 202044039434-PETITION UNDER RULE 137 [13-08-2024(online)].pdf | 2024-08-13 |
| 14 | 202044039434-OTHERS [14-08-2024(online)].pdf | 2024-08-14 |
| 15 | 202044039434-FER_SER_REPLY [14-08-2024(online)].pdf | 2024-08-14 |
| 16 | 202044039434-COMPLETE SPECIFICATION [14-08-2024(online)].pdf | 2024-08-14 |
| 17 | 202044039434-CLAIMS [14-08-2024(online)].pdf | 2024-08-14 |
| 18 | 202044039434-ABSTRACT [14-08-2024(online)].pdf | 2024-08-14 |
| 1 | Search039434E_06-02-2024.pdf |