Claims:1. A computer-implemented method comprising:
receiving a plurality of circuit block design digital files, each circuit block design digital file comprising a design for testability (DFT) placeholder circuit design;
receiving a DFT design digital file comprising a respective DFT circuit design for each circuit block design digital file;
replacing each DFT placeholder circuit design with its respective DFT circuit design to generate a plurality of circuit block design digital files having a completed DFT design; and
generating a system on a chip design digital file from the plurality of circuit block design digital files having the completed DFT design.
, Description:TECHNICAL FIELD
[0001] The disclosure relates generally to electronics, and, more specifically, an embodiment of the disclosure relates to a scalable design for testability (DFT) architecture for a system on a chip (SoC).

BACKGROUND
[0002] A processor, or set of processors, executes instructions from an instruction set, e.g., the instruction set architecture (ISA). The instruction set is the part of the computer architecture related to programming, and generally includes the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term instruction herein may refer to a macro-instruction, e.g., an instruction that is provided to the processor for execution, or to a micro-instruction, e.g., an instruction that results from a processor’s decoder decoding macro-instructions.

BRIEF DESCRIPTION OF THE DRAWINGS
[0003] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
[0004] Figure 1 illustrates a system on a chip (SoC) according to embodiments of the disclosure.
[0005] Figure 2 illustrates a plurality of partitions and circuit blocks according to embodiments of the disclosure.
[0006] Figure 3A illustrates a subsystem comprising a plurality of circuit blocks and partitions according to embodiments of the disclosure.
[0007] Figure 3B illustrates the subsystem of Figure 3A including multiple design for testability (DFT) circuits and their couplings according to embodiments of the disclosure.
[0008] Figure 4A illustrates a DFT placeholder circuit design according to embodiments of the disclosure.
[0009] Figure 4B illustrates a DFT circuit design according to embodiments of the disclosure.
[0010] Figure 5 is a flow diagram illustrating operations for generating an SoC design digital file according to embodiments of the disclosure.
[0011] Figure 6A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the disclosure.
[0012] Figure 6B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the disclosure.
[0013] Figure 7A is a block diagram of a single processor core, along with its connection to the on-die interconnect network and with its local subset of the Level 2 (L2) cache, according to embodiments of the disclosure.
[0014] Figure 7B is an expanded view of part of the processor core in Figure 7A according to embodiments of the disclosure.
[0015] Figure 8 is a block diagram of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the disclosure.
[0016] Figure 9 is a block diagram of a system in accordance with one embodiment of the present disclosure.
[0017] Figure 10 is a block diagram of a more specific exemplary system in accordance with an embodiment of the present disclosure.
[0018] Figure 11, shown is a block diagram of a second more specific exemplary system in accordance with an embodiment of the present disclosure.
[0019] Figure 12, shown is a block diagram of a system on a chip (SoC) in accordance with an embodiment of the present disclosure.
[0020] Figure 13 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the disclosure.

DETAILED DESCRIPTION
[0021] In the following description, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail in order not to obscure the understanding of this description.
[0022] References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.