Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.
| # | Name | Date |
|---|---|---|
| 1 | 202147036834-PRIORITY DOCUMENTS [13-08-2021(online)].pdf | 2021-08-13 |
| 2 | 202147036834-FORM 1 [13-08-2021(online)].pdf | 2021-08-13 |
| 3 | 202147036834-DRAWINGS [13-08-2021(online)].pdf | 2021-08-13 |
| 4 | 202147036834-DECLARATION OF INVENTORSHIP (FORM 5) [13-08-2021(online)].pdf | 2021-08-13 |
| 5 | 202147036834-COMPLETE SPECIFICATION [13-08-2021(online)].pdf | 2021-08-13 |
| 6 | 202147036834.pdf | 2021-10-19 |
| 7 | 202147036834-FORM-26 [03-11-2021(online)].pdf | 2021-11-03 |
| 8 | 202147036834-FORM 3 [14-02-2022(online)].pdf | 2022-02-14 |
| 9 | 202147036834-FORM 3 [16-08-2022(online)].pdf | 2022-08-16 |
| 10 | 202147036834-FORM 18 [28-12-2022(online)].pdf | 2022-12-28 |
| 11 | 202147036834-FER.pdf | 2023-01-23 |
| 12 | 202147036834-FORM 3 [22-05-2023(online)].pdf | 2023-05-22 |
| 13 | 202147036834-Information under section 8(2) [23-05-2023(online)].pdf | 2023-05-23 |
| 14 | 202147036834-Proof of Right [06-07-2023(online)].pdf | 2023-07-06 |
| 15 | 202147036834-PETITION UNDER RULE 137 [12-07-2023(online)].pdf | 2023-07-12 |
| 16 | 202147036834-OTHERS [12-07-2023(online)].pdf | 2023-07-12 |
| 17 | 202147036834-FORM 13 [12-07-2023(online)].pdf | 2023-07-12 |
| 18 | 202147036834-FER_SER_REPLY [12-07-2023(online)].pdf | 2023-07-12 |
| 19 | 202147036834-CLAIMS [12-07-2023(online)].pdf | 2023-07-12 |
| 20 | 202147036834-FORM 3 [28-11-2023(online)].pdf | 2023-11-28 |
| 1 | SearchHistoryE_23-01-2023.pdf |