Field of the Invention:
The instant invention in general relates to an area efficient distributed device structure for integrated voltage regulators and in particular relates to an area efficient distribution of a large size device for integrated voltage regulators.
Background of the Invention:
In a VLSI chip both the core and the I/O blocks play an important role. The I/O blocks are arranged in the periphery in a ring-like fashion. To handle various signals like the power signals (high voltage and low voltage supplies and grounds), ESD signals, slew control signals, there are various rails passing above all the I/O blocks. However, these I/O blocks are placed apart by a certain distance, the minimum of which is known as the pitch of the technology used. To ensure the continuity of these rails, some filler cells known as the IO-FILLERS are generally used. These filler cells contain nothing more than metal rails and ensure the continuity of rails in a non-stop ring-like fashion. The rails are generally in the top metal layers. However, the area occupied by these filler cells is not used for the fabrication of any transistor. Thus, the area, in the metal rails is underutilized.
Concept of a voltage regulator is such that it contains a driver MOS (also called a pass transistor), whose size depends upon the load current capability of the voltage regulator and generally huge to provide current to the entire chip. This MOS needs an input supply VIN and gives out an output supply VOUT, controlled by a voltage VCONT generated by a feedback circuit and an error amplifier as illustrated in Figure 1. The output supply generated needs to be distributed in the entire chip. It is not feasible to route the output supply to each and every corner of the chip, thus it is preferable to make use of the I/O ring in the periphery of the chip. This I/O ring will automatically route the supply VOUT around the periphery of chip. This is implemented by placing this driver MOS on the periphery of the chip so that it takes the input supply from one rail of the I/O ring and
puts the output supply on another rail of the I/O ring with the controlling voltage VCONT on a third rail.
The rails for VIN, the higher input supply and VOUT, the lower output supply are always present in an I/O ring with their corresponding grounds. In addition to these rails, there are certain dedicated rails in an I/O ring to take an external reference signal round the chip. One of these rails can be used to take the VCONT signal round the periphery of the chip to connect the gates of all the pass transistors together. In this way all the three nodes connected to the pass transistor are taken round the I/O ring with great ease.
Conventional voltage regulators have a bypass mode, where VIN is to be bypassed to the output node VOUT by pulling down the VCONT node to ground, and VIN applied is at the level of the VOUT itself. For example in the bypass mode of a 5V to 1.2V voltage regulator, the voltage VIN which is otherwise of 5V level itself becomes 1.2V, and this voltage is then transferred to the VOUT node after the resistance drop of a switched on PMOS. So the MOS sizes need to be huge to have a low on resistance.
A conventional technique employed for a VLSI Chip containing a voltage regulator is illustrated in Figure 2. Also shown in the figure is the lumped pass transistor, the output transistor of the Voltage Regulator, along with a number of pads to satisfy electromigration rules. This arrangement suffers from severe drawbacks such as electromigration problems due to poor power distribution, high IR drops, and difficulty in routing to the core.
Another conventional structure shows distributing the pads and fractions of the pass transistor over the periphery of the chip. If the Pass Transistor has four such pads then the transistor can be split into four parts with each part occupying a side of the chip along with a pad. The scheme is shown in Figure 3. This provides better power distribution and low IR drops, but the problem in this structure is that each such I/O can consume more area than a standard I/O in order to accommodate the huge-sized pass transistor. The problem gets worse in the bypass mode of the voltage regulators, where we need much
higher sizes of the pass transistor as there is no regulation in the bypass mode and we need to drastically reduce the on-resistance of the pass transistor. Thus, this structure has drawbacks in pad-limited designs.
US Patent 6594809 is another prior art patent pertaining to area utilization within the core of chip It relates to low leakage diode insertion for integrated circuits, particularly to inserting diodes in filler cells in the core of the integrated circuits. The drawback of this patent is that it does not provide a solution for utilization of area on the periphery of chip.
Thus, a need is felt for an area efficient structure that utilizes the area on the periphery of the integrated circuit by ensuring that each I/O occupies the same area as a standard I/O and does not pose area problem to a pad -limited design.
Object and Summary of the Invention
The object of the present invention is to provide an area efficient distributed device structure for integrated voltage regulators.
It is another object of the present invention to replicate the pass transistor between a plurality of IOs around the periphery of the chip.
It is further an object of the present invention to minimize electro migration problems in the chip and minimize IR drops in the overall Chip supplied by integrated voltage regulators.
It is yet another object of the present invention to distribute the pass transistor so that each I/O occupies the same area as a standard I/O and does not pose problem to a pad-limited design.
To achieve said objectives the present invention provides an area efficient distributed device structure for integrated voltage regulators comprising:
at least one filler cell connected between a pair of PADS on I/O rail of a chip,
at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip.
Further, the present invention provides a method for creating a distributed device structure for integrated voltage regulators comprising steps of:
- coupling at least one filler cell between a pair of PADS on I/O rail of a chip,
- incorporating replicas of said device in additional filler cells, and
- connecting said additional filler cell to said I/O rails.
Brief description of the drawings
The invention will now be described with reference to the accompanying drawings
Figure 1 illustrates a conventional voltage regulator.
Figure 2 illustrates the conventional technique of placing a pass element in a VLSI
Chip.
Figure 3 shows another conventional technique for placing a pass element in a
VLSI chip.
Figure 4 illustrates an area efficient distributed device structure for integrated
voltage regulators in accordance with the instant invention.
Figure 5 illustrates the structure within a filler cell in accordance with the instant
invention.
Detailed Description
The instant invention provides a distributed structure for a pass transistor in such a way such that each I/O occupies the same area as a standard I/O and does not pose any area problem to a pad-limited design. The remaining pass transistors can be accommodated in the area earlier occupied by the IOFILLERS (Figure 4) by breaking it into small parts These FILLER cells can be of multiple sizes (8x, 16x, 32x, 64x) and spread throughout the I/O ring on the periphery of the chip.
Thus, it is possible to use the area occupied by the IOFILLERS to fabricate the pass transistor of a regulator. More specifically, the conventional IOFILLERS can be replaced by new TRANFILLER cells, each containing a small portion of the pass transistor below the I/O rails, besides the various metal layers. The lowest metal layers can be used for the routing purposes in the transistor. The invented structure for the distributed device is illustrated by Figure 4. Just as there are many IOFILLERS present in a chip, similarly a plurality of TRANFILLERS can replace some or all of these IOFILLERS, depending upon the size of the pass transistor remaining to be placed after placing some of it along with its associated pads; wherein the TRANFILLERS are filler cells comprising the replicas of the device to be distributed. Just as IOFILLERS, the TRANFILLERS can also be made to be available in various sizes of 8x, 16x, 32x, 64x.
As discussed above, the invention is aimed at making a VLSI Chip more area-efficient, and has got the following advantages over the conventional structures of integrated voltage regulators.
-Makes the Chip less susceptible to Electromigration. Particularly in circuits where the current-carrying capacity of the pass transistor under consideration is expected to be very high, Electromigration becomes a key factor. By distributing the transistor in the explained fashion, the required current finds several parallel paths instead of a single path as in the case of a lumped transistor. In this way, the fabricated product becomes less susceptible to failures resulting due to surge of currents.
-Reduces the possibility of IR drops in the Chip, which might be there due to the huge size of the chip. In other words, this scheme would ensure uniformity in the supplies distribution.
-In a pad-limited design ensures area efficient device distribution on the periphery of the chip. The pitch of the pads can be the minimum supported by the technology, even for the special I/Os containing the pass transistor, as the remaining transistor goes into the FILLERS
Along with the pass transistor, other devices such as capacitances and resistances that might be required to compensate the regulator can also be placed in the TRANFILLERS, thereby making the structure more symmetrical and area-efficient.

We Claim:
1. An area efficient distributed device structure for integrated voltage regulators
comprising:
at least one filler cell connected between a pair of PADS on I/O rail of a
chip,
at least one additional filler cell having small size replica of said device is
coupled to said I/O rails for distributing replicas of said device on the
periphery of said chip.
2. An area efficient distributed device structure for integrated voltage regulators as claimed in claim 1, wherein said device is small size replication of a transistor.
3. An area efficient distributed device structure for integrated voltage regulators as claimed in claim 2, wherein said transistor is connected at the output node of said voltage regulator for driving output current.
4. An area efficient distributed device structure as claimed in claim 1, wherein said device is small size replication of a resistor.
5. An area efficient distributed device structure as claimed in claim 1, wherein said device is small size replication of a capacitor.

6. An area efficient distributed device structure as claimed in claim 1, wherein said second filler cell comprising multiple sized filler cells corresponding to the device layout rules.
7. An area efficient distributed device structure for integrated voltage regulators as claimed in claim 1, wherein said additional filler cell is placed on said I/O rail.
8. An area efficient distributed device structure for integrated voltage regulators as claimed in claim 7, wherein said additional filler cell is coupled around a PAD for distributing said replicas corresponding to size of said device.
9. A method for creating a distributed device structure for integrated voltage regulators comprising steps of:
coupling at least one filler cell between a pair of PADS on I/O rail of a
chip,
incorporating replicas of said device in additional filler cells, and
connecting said additional filler cell to said I/O rails.
10 A method for creating a distributed device structure for integrated voltage regulators as claimed in claim 9, wherein said connecting is coupling said additional filler cells on said I/O rails and around PADS.
11. A method for creating a distributed device structure for integrated voltage regulators as claimed in claim 10, wherein said coupling is replicating said device on the periphery of said chip for maximal area utilization.
12. A method for creating a distributed device structure for integrated voltage regulators substantially as herein described with reference to the accompanying drawings.
13. An area efficient distributed device structure for integrated voltage regulators substantially as herein described with reference to the accompanying drawings.