FIELD OF THE INVENTION:

The present invention relates to protective relay for tripping or isolating a circuit or power system from its peripheral or connected means upon detecting a fault in the peripheral or connected means which could damage the circuit or the power system. More specifically the present invention is directed to develop an adaptive over-current relay which advantageously involves Artificial Neural Network (ANN) based soft computing tool to realize the smart decision making logics as well as adaptively reconfigurable user defined relay characteristics on a hardware platform and efficiently executes the relaying operation upon detecting over current fault avoiding any transient current variation.

BACKGROUND OF THE INVENTION:
A protective relay is a device used for tripping or isolating a circuit from its peripheral or connected means when a fault such as over-current, over-voltage, reverse power flow, over-frequency, under-frequency is detected in the peripheral or connected means which could damage the circuit. An over-current relay is a special class of the protective relays which is specifically configured to dispose in conjunction with electrical power systems and operate when the supply/driving current of such electrical power systems exceeds a predetermined value (setting value). The over-current relay protects the electrical power systems against excessive currents which are caused by short circuits, ground faults, etc.
Evolution of the protective relays including the over-current relays begins with sluggish and expensive electromechanical relays, then relatively cheaper and efficient solid state relays and finally to modern and advanced digital/ numeric relays which are economical, fast and reliable, robust and has communication capability [1-5]. However, in the conventional relays including the over-current relays (ORC) which operate with fixed setting, it is difficult to ensure proper protection operation when operating conditions of the power system network gets changed. These scenarios are very common in the context of micro or smart grid system.
Recently Field Programmable Gate Arrays (FPGAs) based relays are getting importance [5-12]. These FPGA based relays are reconfigurable, robust in nature and adapted to operate with higher speed, accuracy and ensure proper protection operation when operating conditions of the power system gets changed. However, the reported FPGA based relays involve either direct implementation of relaying characteristics or look up tables to store them. These crude methods are neither hardware friendly nor adaptive in nature and at the same time, requirement of resources are huge.
Thus, there has been a need for developing a new reconfigurable FPGA based over-current relay involving low-end and low-cost FPGA board which would address the limitation of the existing FPGA based relays and ensure proper protection operation when operating conditions of the power system gets changed.
Reference:
1. M. A. Manzoul, “Multiple overcurrent relays using a single microprocessor,” IEEE Trans. Ind. Electron., vol. 37, no. 4, pp. 307–309, 1990.

2. T. S. Sidhu, M. S. Sachdev, H. C. Wood, “Relay Design of a microprocessor based overcurrent,” IEEE Conf. Comput. Power Commun. Syst. Rural Environ., vol. 45, pp. 41–46, 1991.

3. M. A. Manzoul, “Interrupt-driven microprocessor-based overcurrent relay,” IEEE Trans. Ind. Electron., vol. 38, no.1, pp. 8–9, 1991.

4. F. Fadal, R. Krahe, “Microprocessor based inverse time multiple overcurrent relays,” Electric Power Syst. Res., vol. 35, no. 3, pp. 207–211, 1995.

5. M. A. Manzoul, “Overcurrent relay on FPGA,” Microelectron Reliab., vol. 35, no. 7, pp. 1017–1022, 1995.

6. Z. Guiqing, F. Tao, Z. Hang, W. Jianhua, X. Hong, G. Yingsan, Z. Shiquan, "The implementation of digital protection in power system using FPGA," 4th International Conference on ASIC Proceedings, pp. 474-477, 2001.

7. F. Tao, Z. Guiqing, W. Jianhua, G. Yingsan, Z. Hang, "A FPGA-based implementation of data acquisition and processing for digital protective relays," 4th International Conference on ASIC Proceedings, pp. 518-521, 2001.

8. Z. Guiqing, F. Tao, W. Jianhua, Z. Hang, X. Hong, G. Yingsan, Z. Shiquan, “The SOC design and implementation of digital protective relay based on IP cores,” Proceedings of international conference on power system technology, vol. 4, pp. 2580–583, 2002.

9. S. Ahuja, L. Kothari, D. N. Vishwakarma, S. K. Balasubramanian, “Field programmable gate arrays based overcurrent relays,” Elecric. Power Component Syst., vol. 32, pp. 247–255, 2004.

10. Y.Y. Hong, P.C. Chang-Chian, "Design of Universal Overcurrent Relay using FPGA," Asian Power and Energy Systems, 2007.

11. H. Imaneini, M. Sanaye-Pasand,"A New Structure for Implementation of an FPGA Based Overcurrent Relay," International Review of Electrical Engineering, vol. 7, no. 2, pp. 4314, 2012.

12. V. Maheshwari, B. Das Devulapalli, and A. K. Saxena, “FPGA-based digital overcurrent relay with concurrent sense-process- communicate cycles,” Int. J. Electr. Power Energy Syst., vol. 55, pp. 66–73, 2013.

OBJECT OF THE INVENTION:
It is thus the basic object of the present invention is to develop an adaptive over-current relay which would be adapted to involve Artificial Neural Network (ANN) based soft computing tool to realize the smart decision making logics in executing relaying operation.
Another object of the present invention is to develop an adaptive over-current relay which would be adapted to realize any relay characteristics as per definition of the user on a hardware platform and efficiently executes the relaying operation.
Another object of the present invention is to develop an adaptive over-current relay which would be adapted to include non-linear input-output comparative mapping free of exponential operations and cooperative reconfigurable integrated circuit based realization of one or more relay characteristics for evaluating line current and generate relay tripping signal upon detection of any fault in the system.
Yet another object of the present invention is to develop an adaptive over-current relay which would be adapted to realize the smart decision making logics as well as adaptively reconfigurable user defined relay characteristics on a hardware platform and efficiently executes the relaying operation upon detecting over current fault avoiding any transient current variation.

SUMMARY OF THE INVENTION:
Thus according to the basic aspect of the present invention there is provided an artificial neural network based adaptive over-current protective relay comprising
computing means disposed in operative communication with line current with embedded adaptive operational units including non-linear input-output comparative mapping free of exponential operations and cooperative reconfigurable integrated circuit based realizing one or more relay characteristics for evaluating current flowing through said line/phase and generate relay tripping signal upon detection of any fault in the line; and relaying means adapted to activate by the relay tripping signal to isolate circuit connected to the line current through the present over-current relay.

In a preferred embodiment, the present artificial neural network based adaptive over-current protective relay comprises the computing means including analog to digital converter (ADC) module for operative connection with the current line;
ROM based look-up table (LUT) outputs of said non-linear operations for various inputs; and logsigmoidal activation function based architecture involving inter-connecting weight-bias for different relay characteristics.
According to another aspect in the present artificial neural network based adaptive over-current protective relay, the computing means comprises
a Root Means Square (RMS) computing unit for evaluating RMS value of the current flowing through the current line with a trigger of RMS completion;
a Plug Setting Multiplier (PSM) unit computing the Plug Setting Multiplier (PSM) data from the evaluated rms value;
said Artificial Neuron Network (ANN) based processing unit configured to activate and with the RMS completion trigger having Artificial Neuron Network with logsigmoidal function based hidden layers and separately trained with multiple input-output data sets corresponding to relay characteristics being realized to extract weight and bias values for each relay characteristic based on the PSM data and generate tripping time value;
a Time Setting Multiplier (TSM) unit for calculating Time Setting Multiplier (TSM) value based on the tripping time value generated by the ANN based processing unit; and a Tripping Signal Generator (TSG) unit for generating the tripping signal based on the TSM value avoiding any transient fault conditions; said units of the computing means are configured to be realized on FPGA based hardware platform.

According to yet another aspect in the present artificial neural network based adaptive over-current protective relay, the RMS unit comprises
a signal generator for generating clock signal preferably having frequency of 12.8 KHz;
counter for counting preferably upto 8 bit;
2’s complement module to receive the ADC-generated data and convert it into unsigned data;
a multiplier for squaring the converted unsigned data at every rising edge of the clock signal as generated by the 12.8 KHz signal generator;
accumulator for accumulating the squared data with previously squared data till counting of maximum data point by the counter preferably 128 data points; and
a computing module to calculate mean of the accumulated data and generate square root of that mean value which corresponds to 16 bits RMS data with the RMS completion trigger.

According to another aspect in the present artificial neural network based adaptive over-current protective relay, the PSM unit comprises
a bit concatenatig module to concate two zero bits with the 16 bits RMS data as received from the RMS unit in LSB position to convert it into 18 bits data;
a multiplication factor generator for generating 18 bits plug setting multiplier value from eight different values starting from 25% to 200% in steps of 25% depending on input 3 bit plug setting value;
a multiplier module for signed multiply the plug setting multiplier value with the concated RMS data;
a bit cascading unit to bit cast the signed multiplied data for extacting the exact 18 bit PSM data.

According to a further aspect in the present artificial neural network based adaptive over-current protective relay, the ANN processing unit comprises one or more logsigmoidal function value generation units configured to activate with the RMS completion trigger, each corresponds to a relay characteristic;
said logsigmoidal function value generation unit comprises
bit casting module to divide the signed PSM data in sign value and absolute value;
a multiplier form multiplying the absolute value with 100 with an index for memory management;
wherein if the sign value is '1', the data received by this unit from the memory is transferred to output and when the sign value is '0' and the memory returned data is '0' then log sigmoidal value is referred to maximum and if, the sign value is '0' and the memory returned data is greater than '0' then logsigmoidal value is the difference of reference maximum value and memory returned value; and
wherein said ANN processing unit generates a trigger pulse after each instance of a complete processing.

According to another aspect in the present artificial neural network based adaptive over-current protective relay, the TSM unit bit cast and modify the tripping time value generated by the ANN processing unit, depending on selection of saturation level of that tripping time value;

said TSM unit post modification signed multiply the tripping time value with a multiplication factor in the range of 0.1 to 1.0 to generate the TSM value.

According to another aspect in the present artificial neural network based adaptive over-current protective relay, the TSG unit generates the tripping signal based on the TSM value avoiding any transient fault conditions when PSM is more than or equal to 1.5 by involving temporary timer value is counted by counter of the TSG unit which is configured to reset to zero in case of transient fault conditions;
wherein the tripping signal is generated if it is found that tripping time value is less or equal to the temporary timer data which is counted by a counter present in this unit, whereby if the tripping time value is greater than temporary timer data, then the difference of the tripping time value and the temporary timer data is checked repeatedly until the difference reaches to '1' and tripping signal is generated.

According to another aspect in the present artificial neural network based adaptive over-current protective relay, the ANN processing unit working on pipelining architecture, includes ROM based logsigmoidal activation function and implementation of the same in the FPGA platform.

According to another aspect in the present artificial neural network based adaptive over-current protective relay, the ANN processing unit is adapted to impletemt any user defined characteristics only by suitable selection of weights and bias including standard characteristics like Inverse definite Minimum time (IDMT), Very Inverse (VI) and Extremely Inverse (EI) characteristics with insignificant enhancement of resource.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS:
Fig 1 shows a typical Artificial Neurone.
Fig 2 shows ANN model of single hidden layer with three neurons.
Fig 3 shows a Schematic representation of ROM based Logsigmoidal Function.
Fig 4 shows various approximation of the log-sigmoid transfer function.
Fig 5 shows block representation of computing means of the present adaptive over-current relay in accordance to a preferred embodiment of the present invention.
Fig 6 shows operation of RMS unit associated with the present adaptive over-current relay in accordance to a preferred embodiment of the present invention.
Fig 7 shows operation of the subsequent PSM unit associated with the present adaptive over-current relay in accordance to a preferred embodiment of the present invention.
Fig 8 shows operation of the logsigmoidal function value generation unit associated with the present adaptive over-current relay in accordance to a preferred embodiment of the present invention.
Fig 9 shows operation of TSM unit associated with the present adaptive over-current relay in accordance to a preferred embodiment of the present invention.
Fig 10 shows operation of TSG unit associated with the present adaptive over-current relay in accordance to a preferred embodiment of the present invention.
Fig 11 shows summarized operation of the computing means in accordance to a preferred embodiment of the present invention.
Fig 12 shows graphical representations of the results obtained from the prototype adaptive over-current relay in accordance to a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION WITH REFERENCE TO THE ACCOMPANYING FIGURES:
As stated hereinbefore, the present invention discloses an adaptive over-current relay with embedded smart decision making logics. The present adaptive over-current relay advantageously involves Artificial Neural Network (ANN) based soft computing tool to realize the smart decision making logics as well as keeping provision to incorporate plurality of adaptively reconfigurable relay characteristics using same hardware resource.

The present adaptive over-current relay includes a computing means and a relaying means. The computing means is configured to be disposed in operative communication with a current line for evaluating current flowing through said current line and generate relay tripping signal upon detection of any fault in the current line. The relaying means is disposed in operative communication with the computing means for receiving the tripping signal from the computing means and accordingly isolate the power system or electronic connected to the line current through the over-current relay. The computing means includes ANN based operational units configured to realize one or more relay characteristics generating the tripping signal.

In a preferred embodiment of the present adaptive over-current relay, three main relay characteristics are incorporated in the computing means such as:

Inverse definite Minimum time (IDMT):
(1)

Very Inverse (VI):
(2)
Extremely Inverse (EI):

(3)

Where, T is operating time in sec, I is plug setting multiplier (PSM) = Actuating Current/ Pick up current, and TSM is Time Setting Multiplier.
While targeting the FPGA as the hardware platform for realizing the present adaptive over-current relay, it is difficult to implement non-linear eq. (1) directly. Under this situation the ANN plays an important role. Simply by designing an ANN model as shown in Fig. 1 with suitable weights and bias one can map any kind of non-linear characteristics. This feature of ANN has been exploited in the present invention to design the universal adaptive over current relay.

It is well known that the neural network with more hidden units can map input-output relationship with higher accuracy. However large network may cause more error at output while implemented on FPGA, since the truncation error at each neuron are propagated and accumulated at the output level. Moreover the computation process of an ANN is multiplication rich. Hence selection of large architecture would restrict its economical implementation on FPGA, as low end FPGA chips have limited numbers of “multipliers”.
In the present adaptive over–current relay, single hidden layer based feed forward ANN architecture with logsigmoidal activation function is used. The Logsigmoidal function as used in the present invention for implementing the ANN model is shown in the eq. (4) as follows

(4)
As exponential logic block or any IP cores are not universally available, direct implementation of the logsigmoidal function is very difficult to achieve. The useful approaches to approximate this function with simple FPGA designs as follows:

Piecewise linear approximation (PLAN) Based Approach:
Approximating log-sigmoidal function using PLAN has certain advantages. It can be implemented using adders, logic blocks and multiplexers without need of a divider block. However better approximation of the log-sigmoidal function ensures better accuracy of the ANN output while implemented on embedded hardware. An eight-piecewise break-up (PLAN-8) for approximating the log-sigmoid function as in Table 1 has been presented here.

TABLE 1: SIGMOIDAL APPROX. USING PLAN-8
Condition Operation
0<=|x|<1.35 f(x)=0.2228*|x|+0.5061
1.35<=|x|<2.35 f(x)=0.1186*|x|+0.6394
2.35<=|x|<3.35 f(x)=0.0530*|x|+0.7915
3.35<=|x|<4.35 f(x)=0.0211*|x|+0.8968
4.35<=|x|<6 f(x)=0.0068*|x|+0.9582
6=<|x|<7.35 f(x)=0.0031*|x|+0.9782
7.35<=|x|<9.35 f(x)=0.0012*|x|+0.9894
|x|>=9.35 f(x)=1

ROM based Look-Up Table (LUT) Approach:
In the ROM based look-up table approach (LUT) outputs of the nonlinear function for various inputs are stored in the memory locations. The schematic representation of the LUT approach is shown in Fig. 3. However, using this approach higher precision demands larger memory.

The various approximation of the log-sigmoid transfer function is shown in Fig. 4. Both PLAN and LUT based techniques are used to realize the logsigmoidal activation function and have been implemented in FPGA of Altera DE0 Nano Board (Cyclone IV E EP4CE22F17C6). A comparison among the resource, accuracy and performance for logsigmoidal activation function with 16-bit fixed point representation is furnished in the Table 2.

TABLE 2: PERFORMANCES OF HARDWARE IMPLEMENTED SIGMOIDAL FUNCTION
Logsigmoidal
Implementation Resource Utilization Timing RMS Error
ROM Based Logsig (16 bit) 4 input LUT : 1.18%
Slice : 1.82%
I/O Pin : 1.39%
18x18 Mult : 3.12%
16bit RAMB : 6.25%
2 CLK 0.0006309
PLAN-8 Based Logsig (16 bit) 4 input LUT : 1.56%
Slice : 2.54%
I/O Pin : 1.19%
18x18 Mult : 6.25%
16bit RAMB : 0.00%
1 CLK 0.0022859

Considering higher accuracy of LUT based logsigmoidal function, it has been selected in relay design. However, during design higher memory demanded by LUT has been reduced by implementing pipelining architecture.
Reference is now invited from the accompanying Fig 5 which shows block representation of the computing means of the present adaptive over-current relay. As shown in the accompanying Fig 5, the present adaptive over-current relay is disposed in operative communication with the current line though an ADC module (analog to digital converter). As shown in the accompanying Fig 5, the operational units associated with the computing means for evaluating current flowing through said current line and generate relay tripping signal upon detection of any fault in the current line includes a RMS (Root Mean Square) unit, a PSM (Plug Setting Multiplier) unit, an ANN processing unit, a TSM (Time Setting Multiplier) unit and a TSG (Tripping Signal Generator) unit. All of the operational units of the computing means are configured to be realized on the FPGA based hardware platform. Working of the operational units is further explained hereunder with the supportive illustration of the Fig 6-10.
Referring to the Fig 6, operation of the RMS unit is now explained. In the RMS unit, rms value of the current flowing through the current line is evaluated by using 128 data points as counted with the help of a 12.8 KHz signal generator and a 8 bit counter of the RMS unit. Initially, the ADC-generated data are converted into unsigned data by a binary 2’s complement module of the RMS unit and then the converted data is squared in a multiplier module of the RMS unit at every rising edge of a 12.8 kHz clock instance as generated by the 12.8 KHz signal generator. After that, the squared data are accumulated with the previously squared data (like (n+1)th squared data is accumulated with nth data) in the accumulator till the 128 data point has been counted by the counter. Then in computing module of the RMS unit, mean of the 128 data is calculated and finally, a square root of that mean value is calculated with a trigger of RMS completion.
The accompanying Fig 7 shows operation of the subsequent PSM unit. The processed RMS value from the RMS unit is fed into the PSM unit for computing the Plug Setting Multiplier data (I). In this PSM unit, the RMS unit generated 16 bit RMS data is concatenated with two zero bit in LSB position and converted to 18 bit. Then it is signed multiplied in a multiplier module of the PSM unit with a 18-bit plug setting multiplier value which is ranged from 25% to 200% in steps of 25% and generated by multiplication factor generator of the PSM unit depending on input 3 bit plug setting value. Later the signed multiplied data is bit casted by a bit cascading module of the PSM unit for extracting exact 18 bit PSM data (I) from the PSM unit.
The PSM data (I) is then forwarded to the ANN prcessing unit which includes ANN model with logsigmoidal function based hidden layers and separately trained with multiple input-output data sets corresponding to each relay characteristics which being realized by the ANN processing unit to extract the weight and bias values for each relay characteristic. The trigger of RMS completion reset the ANN processing unit. Since the present ANN processing unit is configured to extract the weight and bias values for three relay characteristic, three logsigmoidal function value generation units [LOGSIG NEURON-1, LOGSIG NEURON-2, LOGSIG NEURON-3] are used to calculate the Logsigmoidal value of the cumulative sum of the artificial neuron as given in Eq. (4). Operation of one of such logsigmoidal function value generation unit is shown in the accompanying Fig 8. As shown in the Fig 8, a trigger pulse is first send to the logsigmoidal value generating block. Then the given signed PSM data is divided into two parts by the Bit casting which consist sign value and absolute value respectively. In the next step, absolute value is multiplied with 100 to generate an index for memory management. Side by side depending on the sign value and memory returned data as generated from ROM in computing means three decisions are taken. While sign value is '1', whatever data this unit will receive from the memory will be transferred to the output. When the sign value is '0' and the memory returned data is '0' then log sigmoidal value is referred to the maximum and if, the sign value is '0' and the memory returned data is greater than '0' then log sigmoidal value will be the difference of reference maximum value and memory returned value.
The accompanying Fig 9 shows operation of the subsequent TSM unit. Tripping time value generated by the ANN block is initially bit casted here. Later, depending on the selection of the saturation level of that tripping time data, it is modified. After modification, the tripping time data is signed multiplied by a multiplication factor, which is in the range of 0.1 to 1.0. Hence the TSM value is calculated.
The TSG unit operation as shown in the Fig 10, is applicable only when the PSM (I) is more than or equal to 1.5. The ANN unit generates a trigger pulse after each instance of a complete processing. However it is very important that the relay should not be mal operated for any transient fault conditions. To ensure that, a temporary timer value is counted by a counter in the TSG unit and if any transient fault occurs, then the temporary timer value will be reset to zero. After acquiring the PSM for permanent fault, TSM unit generates tripping time data, is compared with the temporary timer data. If it is found that tripping time data is less than equal to temporary timer data, then the trip signal is generated for activating the relaying means and isolating the circuit connected to the line current through the present over-current relay. But if the tripping time data is greater than temporary timer data, then the difference of the tripping time data and temporary timer data is checked. And this process is going on til the difference reaches to '1' and the trip signal will be triggered again when that difference value will be less than equal to 1.
The entire operation of the computing means of the present over-current relay is summarized in the flow chart of the Fig 11

ANN Implementation:
In a preferred embodiment of the present invention 80 input-output data sets are generated for every relay characteristic using Eq. (1-3). The ANN network is trained with each 80 input-output data sets separately to extract the weight and bias values for each relay characteristic.

The activation function of the hidden layers is logsigmoidal function and output layer is linear function. The corresponding values of weights and biases are furnished respectively in Table 5, Table 6 and Table 7 for IDMT, VI and EI characteristics. Due to highly non-linear nature, both the VI and EI characteristics have been split into two sets for different PSM range to train the ANN, which has enhanced the accuracy of the design to a great extend. Thus, two sets of weight-bias were obtained for VI and EI. The weight-bias obtained for different relay characteristics are furnished in Table 3 - Table 5.
TABLE 3: WEIGHTS AND BIASES OF THE ANN MODEL FOR IDMT CHARACTERISTICS
Categories IDMT
Input weight -0.1904(w11), -1.7524(w12), -1.5500(w13)
Input bias -1.4430(b1), 1.9611(b2), 0.3171(b3)
Output weight 0.7258(w21), -3.7292(w22), 13.7129(w23)
Output bias 0.0683(b)

TABLE 4: WEIGHTS AND BIASES OF THE ANN MODEL FOR VI CHARACTERISTICS
Categories VI-1(For PSM 1.5 to 8) VI-2(For PSM 8 to 20)
Input weight 2.8508(w11), 0.7793(w12),
-3.4575(w13) 0.0491(w11), -0.6218(w12),
0.4995(w13)
Input bias -18.7567(b1), 0.1020(b2),
2.2968(b3) 28.0684(b1), 10.0516(b2),
-4.0656(b3)
Output weight -0.0154(w21), -1.7007(w22),
7.5225(w23) 0.3237(w21), 0.0105(w22),
-0.0530(w23)
Output bias 1.7748(b) -0.2491(b)

TABLE 5: WEIGHTS AND BIASES OF THE ANN MODEL FOR EI CHARACTERISTICS
Categories EI-1(For PSM 1.5 to 8) EI-2(For PSM 8 to 20)
Input weight -1.7439(w11), -0.5786(w12),
-4.7048(w13) -1.2500(w11), 0.4319(w12),
0.3127(w13)
Input bias 1.8861(b1), 0.7582(b2),
4.1507(b3) 23.3215(b1), -3.5233(b2),
-1.1214(b3)
Output weight 2.6235(w21), 0.7168(w22),
15.0835(w23) 0.0017(w21), 0.0110(w22),
-0.1880(w23)
Output bias 0.0259(b) 0.1819(b)
The trained optimized ANN architecture is implemented in FPGA using two approaches: (i) Parallel and (ii) Pipelining to trade-off between resource utilization and processing time.
The RMS errors of the hardware implemented ANN outputs with refer to the MATLAB are computed and furnished. The required clock cycles for computation of the above algorithms are shown in the Table 6.
TABLE 6: COMPARISON OF DIFFERENT ANN MODELS IMPLEMENTED
ANN Type Architecture Timing RMS Error
MATLAB FPGA
LUT Based
Activation Function Parallel 3 CLK 0.0404 0.0503
Pipelining 24 CLK 0.0503
PLAN-8 Based
Activation Function Parallel 3 CLK 0.678
After implementation of the ANN model in FPGA platform, the operation of the developed relay was tested using a secondary injection set as shown in Fig. 10. A 16 bit ADS1115 Analog-to-Digital Converter has been used here to convert the system current to its equivalent digital form. ADS1115 is a serial ADC and it connects with the host system via I2C protocol. The analogous current signal from the secondary injection set is sampled at 12.8 Khz to compute the R.M.S. value of the system current which is used by the relay under test.
In the proposed design eight different Plug settings starting from 25% to 200% in steps of 25% can be selected. However, automatic selection of plug setting depending on the power system network upgradation can also be incorporated to make the relay adaptive for smart grid applications. The tripping time is finally governed by the TSM unit. Ten different time settings (0.1 to 1 in steps of 0.1) are available for developed Overcurrent relay. Like PSM, system driven autometic selection may also possible to meet the demand of the present day power systems.
Though as per IEC 62055 standard three characteristics viz. Inverse definite Minimum time (IDMT), Very Inverse (VI) and Extremely Inverse (EI) characteristics have been implemented, it has provision of adding more characteristics with insignificant enhancement of resource.
The novelty of the invention over other schemes is that the ANN based algorithm is flexible enough to adapt any user defined characteristics only by suitable selection of weights and bias. The graphical representations of the results obtained from the prototype under laboratory condition are presented in Fig 12.
The results obtained are presented in Table 7. Even if with using 1×3×1 ANN Architecture, precesion of the test results are within the range of IEC 60255-3.
TABLE 7: DEVIATIONS OF THE ACTUAL OUTPUT FROM THE THEORETICAL CHARACTERISTICS
TSM IDMT VI EI
Max error % RMS error % Max error % RMS error % Max error % RMS error %
0.1 3.1408657 1.224286 3.6805556 1.595616 6.167749 2.332804
0.2 2.941567 1.069981 2.66059 1.183657 3.259604 1.30584
0.3 2.875134 1.049985 2.259356 1.087757 3.612552 1.322129
0.4 2.8419177 1.035699 2.1864149 1.024992 3.2596045 1.19676
0.5 2.423391 0.865063 1.792535 0.816028 3.259604 1.261788
0.6 2.476537 0.880255 1.821711 0.853806 3.86312 1.335042
0.7 2.5144985 0.895661 1.8425512 0.829934 3.31358 1.256591
0.8 2.592794 0.905522 1.858181 0.85502 3.86312 1.308957
0.9 2.609403 0.911404 1.870338 0.862202 3.612552 1.283371
1.0 2.423391 0.86073 1.773148 0.808141 3.997173 1.443485
The designed relay is very much adaptive for transient faults. The final tripping pulse is send to the relay only when the fault is not cleared within the tripping time as furnished in the Fig. 10.

The highlights and the major contribution of the present invention over the existing schemes are as follows:
i) Use of LUT based unique 3 neuron single layered “All in one” ANN architecture for realizing highly nonlinear Over Current Relaying characteristics, by avoiding the exponential operations, which are difficult to handle by the FPGAs.
ii) Only selection of suitable inter connecting weights among the neurons & bias values (Table 3-5) through multiplexers, are capable of realizing any over current relaying characteristics. In this sense, it is flexible and easy to make it adaptive in nature, at the cost of NO extra hardware requirement.
iii) The plug setting and Time setting Multiplier (TSM) can be governed by power system conditions. These features of the invented unit will help to coordinate the operation of the over current relay more intelligently in the context of smart grid system.
iv) Complex computations for realizing each characteristic has been avoided, making it simple, hardware friendly and general for all characteristics. Thus, usages of less hardware blocks make the relay economical and power consumption is also less.
v) Advantages of the parallel processing of FPGA has made possible to design concurrently operating building blocks of ANN in the form of digital circuits. Hence processing time of the single phase relay unit is in the order of 60ns (parallel architecture, 3clock cycle, with a clock frequency of 50 MHz) or 480ns (pipelined architecture, 24clock cycle, with a clock frequency of 50 MHz). This very fast processing time of the invented relay, as compared with the existing systems, is only been achieved due to the unique selection of the ANN design parameters.
vi) This single phase over current relay unit is easily extendable for three phase system with small amount additional resources.

WE CLAIM:

1. An artificial neural network based adaptive over-current protective relay comprising
computing means disposed in operative communication with line current with embedded adaptive operational units including non-linear input-output comparative mapping free of exponential operations and cooperative reconfigurable integrated circuit based realizing one or more relay characteristics for evaluating current flowing through said current line and generate relay tripping signal upon detection of any fault in the current line; and
relaying means adapted to activate by the relay tripping signal to isolate circuit connected to the line current through the present over-current relay.

2. The artificial neural network based adaptive over-current protective relay as claimed in claim 1, comprises the computing means including analog to digital converter (ADC) module for operative connection with the current line;
ROM based look-up table (LUT) outputs of said non-linear operations for various inputs; and
logsigmoidal activation function based architecture involving inter-connecting weight-bias for different relay characteristics.

3. The artificial neural network based adaptive over-current protective relay as claimed in claim 1 or 2, wherein the computing means comprises
a Root Square Means (RSM) computing unit for evaluating rms value of the current flowing through the current line with a trigger of RMS completion;
a Plug Setting Multiplier (PSM) unit computing the Plug Setting Multiplier (PSM) data from the evaluated rms value;
said Artificial Neuron Network (ANN) based processing unit configured to activate and with the RMS competion trigger having Artificial Neuron Network with logsigmoidal function based hidden layers and separately trained with multiple input-output data sets corresponding to relay characteristics being realized to extract weight and bias values for each relay characteristic based on the PSM data and generate tripping time value;
a Time Setting Multiplier (TSM) unit for calculating Time Setting Multiplier (TSM) value based on the tripping time value generated by the ANN based processing unit; and
a Tripping Signal Generator (TSG) unit for generating the tripping signal based on the TSM value avoiding any transient fault conditions;
said units of the computing means are configured to be realized on FPGA based hardware platform.

4. The artificial neural network based adaptive over-current protective relay as claimed in claim anyone of the claims 1 to 3, wherein the RMS unit comprises
a signal generator for generating clock signal preferably having frequency of 12.8 KHz;
counter for counting preferably upto 8 bit;
binary 2’s complement module to receive the ADC-generated data and convert it into unsigned data;
a multiplier for squaring the converted unsigned data at every rising edge of the clock signal as generated by the 12.8 KHz signal generator;
accumulator for accumulating the squared data with previously squared data till counting of maximum data point by the counter preferably 128 data points; and
a computing module to calculate mean of the accumulated data and generate square root of that mean value which corresponds to 16 bits RMS data with the RMS completion trigger.

5. The artificial neural network based adaptive over-current protective relay as claimed in claim anyone of the claims 1 to 4, wherein the PSM unit comprises
a bit concatenatig module to concate two zero bits with the 16 bits RSM data as received from the RSM unit in LSB position to convert it into 18 bits data;
a multiplication factor generator for generating 18 bits plug setting multiplier value from eight different values starting from 25% to 200% in steps of 25% depending on input 3 bit plug setting value;
a multiplier module for signed multiply the plug setting multiplier value with the concated RSM data;
a bit cascading unit to bit cast the signed multiplied data for extacting the exact 18 bit PSM data.

6. The artificial neural network based adaptive over-current protective relay as claimed in claim anyone of the claims 1 to 5, wherein the ANN processing unit comprises one or more logsigmoidal function value generation units configured to activate with the RMS completion trigger, each corresponds to a relay characteristic;
said logsigmoidal function value generation unit comprises
bit casting module to divide the signed PSM data in sign value and absolute value;
a multiplier form multiplying the absolute value with 100 with an index for memory management;
wherein if the sign value is '1 irrespective of the data this unit received from the memory is transferred to output and when the sign value is '0' and the memory returned data is '0' then log sigmoidal value is referred to maximum and if, the sign value is '0' and the memory returned data is greater than '0' then logsigmoidal value is difference of reference maximum value and memory returned value; and
wherein said ANN processing unit generates a trigger pulse after each instance of a complete processing.

7. The artificial neural network based adaptive over-current protective relay as claimed in claim anyone of the claims 1 to 6, wherein TSM unit bit cast the tripping time value generated by the ANN processing unit modifiy it depending on selection of saturation level of that tripping time value;

said TSM unit post modification signed multiply the tripping time value with a multiplication factor in the range of 0.1 to 1.0 to generate the TSM value.

8. The artificial neural network based adaptive over-current protective relay as claimed in claim anyone of the claims 1 to 7, wherein the TSG unit generates the tripping signal based on the TSM value avoiding any transient fault conditions when PSM is more than or equal to 1.5 by involving temporary timer value is counted by counter of the TSG unit which is configured to reset to zero transient fault conditions;
wherein the tripping signal is generated after acquiring the PSM data for permanent fault by comparing the TSM value with the temporary timer data and if it is found that TSM value is less or equal to the temporary timer data, whereby if the TSM value is greater than temporary timer data, then the difference of the TSM value and the temporary timer data is checked till the difference reaches to '1' and the tripping signal is generated again when that difference value will be less than equal to ‘1’.

9. The artificial neural network based adaptive over-current protective relay as claimed in claim anyone of the claims 1 to 8, wherein the ANN processing unit includes ROM based look-up table technique with pipelining architecture based impletementtion for approximation of the logsigmoid transfer function and implementation of the same in the FPGA platform.

10. The artificial neural network based adaptive over-current protective relay as claimed in claim anyone of the claims 1 to 8, wherein the ANN processing unit is adapted to impletemt any user defined characteristics only by suitable selection of weights and bias including standard characteristics like Inverse definite Minimum time (IDMT), Very Inverse (VI) and Extremely Inverse (EI) characteristics with insignificant enhancement of resource.