Claims:1. An apparatus comprising:‎
a substrate with a plurality of layers including a top layer, one or more intermediate layers and a ‎bottom layer; and
ferromagnetic material applied to a first of the one or more intermediate layers in an area ‎underneath a magnetic source disposed on an outer surface of the top layer; ‎
wherein the ferromagnetic material is to provide a shield for signal routing traces in one or more ‎other intermediate layers or the bottom layer underneath the first intermediate layer, from a magnetic ‎field produced by the magnetic source.‎
, Description:CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present patent application claims the benefit of U.S. Non-Provisional Patent Application No. 17/131,663, filed December 22, 2020, and titled: “ASSEMBLY OF 2XD MODULE USING HIGH DENSITY INTERCONNECT BRIDGES”, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD
[0002] Embodiments of the present disclosure relate to electronic packages, and more particularly to multi-chip packages with high density interconnect bridges.

BACKGROUND
[0003] The move to multi-die modules has led to the need for advanced interconnect architectures in order to accommodate the multiple dies. In one type of architecture, multiple dies are attached to an interposer that provides electrical coupling between the multiple dies. However, the area of the interposer has to be at least as large as the sum of the areas of the several dies and include an additional assembly and routing overhead. The growth of the area of the interposer increases the cost and provides manufacturability issues.
[0004] In another approach, embedded bridges are provided in the package substrate. The bridges provide high density routing in order to electrically couple the multiple dies together. However, since multiple bridge dies are needed, there is an issue with obtaining proper alignment for all of the bridge dies. Alignment is also made difficult due to warpage of the package substrate in which the bridge dies are embedded. As the number of bridge dies necessary for the package increase, alignment issues become an increasingly difficult design challenge.

BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Figure 1 is a cross-sectional illustration of a multi-chip module that comprises a bridge embedded in a mold layer to couple a first die to a second die, in accordance with an embodiment.
[0006] Figure 2A is a cross-sectional illustration of a multi-chip module that comprises solder balls over conductive pillars, in accordance with an embodiment.
[0007] Figure 2B is a cross-sectional illustration of a multi-chip module that is attached to a package substrate, in accordance with an embodiment.
[0008] Figure 2C is a plan view illustration of a multi-chip module with a plurality of dies and bridge dies connecting the dies together, in accordance with an embodiment.
[0009] Figure 2D is a cross-sectional illustration of an electronic system with a multi-chip module that is coupled to a board, in accordance with an embodiment.
[0010] Figure 2E is a cross-sectional illustration of an electronic system with a multi-chip module that is coupled to a package substrate by an interposer, in accordance with an embodiment.
[0011] Figure 3A is a cross-sectional illustration of a multi-chip module with a redistribution layer over conductive pillars, in accordance with an embodiment.
[0012] Figure 3B is a cross-sectional illustration of a multi-chip module that is coupled to a package substrate, in accordance with an embodiment.
[0013] Figure 3C is a cross-sectional illustration of an electronic system with a multi-chip module that is coupled to a board, in accordance with an embodiment.
[0014] Figures 4A-4D are cross-sectional illustrations depicting a process for assembling a multi-chip module, in accordance with an embodiment.
[0015] Figures 5A-5D are cross-sectional illustrations depicting a process for assembling a multi-chip module with a bridge die and a component die, in accordance with an embodiment.
[0016] Figures 6A-6F are cross-sectional illustrations depicting a process for assembling a multi-chip module with solder balls at least partially embedded in the mold layer, in accordance with an embodiment.
[0017] Figures 7A-7F are cross-sectional illustrations depicting a process for assembling a multi-chip module with multiple layers of dies, in accordance with an embodiment.
[0018] Figures 7G-7J are cross-sectional illustrations depicting a process for assembling a multi-chip module, in accordance with an additional embodiment.
[0019] Figures 8A-8F are cross-sectional illustrations depicting a process for assembling a multi-chip module with thin dies and a thin bridge die, in accordance with an embodiment.
[0020] Figures 9A-9D are plan view illustrations depicting interconnect architectures capable of accommodating die offsets, in accordance with an embodiment.
[0021] Figures 10A-10D plan view illustrations of bridge die architectures to accommodate die misalignments, in accordance with an embodiment.
[0022] Figure 11 is a schematic of a computing device built in accordance with an embodiment.

EMBODIMENTS OF THE PRESENT DISCLOSURE
[0023] Described herein are multi-chip packages with high density interconnect bridges, in accordance with various embodiments. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.