TECHNICAL FIELD
The present disclosure relates to an avionic architecture which combines predetermined avionic functions into a single platform.
BACKGROUND
Current Avionics systems typically consist of a multiple electronic enclosures, each of which is dedicated to controlling a particular aircraft function. Examples of aircraft functions that are controlled are the weapons sub-system, the flight control sub-system, the health monitoring and reporting sub-system, and the display control sub-system. These sub-systems are then connected via standard avionics or military standard busses such as 1553 or Arinc 429. There are multiple problems faced in today's architectures i.e. the amount of cabling, the cost of multiple electronics assemblies, and the reliability of multiple enclosures and assemblies. Even within the enclosure itself, a significant amount of cabling is required for routing aircraft inputs and outputs to the various modules that will process these I/O. This adds cost and unreliability to the assembly.
With the advent of faster control system bandwidth requirements, and faster signal processing requirements due to more complex algorithms for flight control, navigation etc, bandwidth requirements for avionics is growing rapidly. An integrated architecture with high speed busses is required in order for high performance processors to be optimally utilized. A Multi-processor architecture is required with the ability to move processing functionality if required. With multi-processor architectures also comes the need for efficient communications between processors. Finally, there is a need for redundancy in data paths as well as a need for re-usability of modules developed previously, if possible.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
Figure 1 shows the Multi-processor Multi-Function Avionics Architecture.
Figure 2 shows the block diagram of the Avionic System Architecture. Figure 3 shows the Block Diagram of Processor based carrier module. Figure 4 shows the inter processor connectivity.

Figure 5 shows the global PCI-E hierarchy.
Figure 6 shows memory map scheme with no address translation.
Figure 7 shows inter module connectivity of the avionic system.
Figure 8 shows handling aircraft I/O.
Figure 9 shows the I/O Transition Panel (IOTP) board set.
Figure 10 shows the Ethernet and USB connectivity of IOTP with the backplane.
DETAILED DESCRIPTION
The primary embodiment of the disclosure is an avionic system architecture comprising Input Output Transition Panel (IOTP) (40) to convert plurality of input/output discrete lines to single input/output interface; Backplane (60) placed in a chassis to receive the data from the input/output interface of the IOTP (40), wherein IOTP (40) is plugged into said backplane, and the backplane (60) comprises slots for placing predetermined module cards; at least one processor module (20) and/or Input/ Output (I/O) module placed on the backplane slots to send/receive data from IOTP (40), wherein each processor module (20) comprises a processor (21) with at least one 4-lane PCI-E (Peripheral Component Interface Express) interface, PCI-E switch (22), PCI-E/ PCI-X bridge (23) and PMC connector (24), wherein said processor modules (20) controls at least one predetermined function of the avionic system; and PCI-E (27) and Versa Module Euro card (VME) (30) buses to interconnect the processor modules (20) for inter-communication.
In yet another embodiment of the disclosure the single input/output interface of the IOTP (40) is PCI-E bus single lane.
In still another embodiment of the disclosure the IOTP (40) comprises I/O logic to send/receive discrete input/output (45A), Field Programmable Gated Array (FPGA) (41) to receive the input/output from the I/O logic (45) input/output, process and send out on a single PCI-E lane (XI) to the backplane (60).

In still another embodiment of the disclosure the IOTP (40) provides circuits for signal protection using active and passive circuitry for electrical protection, surge protection, EMI suppression, and for terminating general purpose I/O onto the PCI-E bus in order to reduce number of routes on the backplane (60).
In still another embodiment of the disclosure the IOTP (40) provides circuits for signal protection and for terminating general purpose I/O onto the PCI-E bus in order to reduce number of routes on the backplane (60).
In still another embodiment of the disclosure the backplane is Vita46 backplane architecture.
In still another embodiment of the disclosure the backplane comprises Versa Module Euro-card (VME) bus and PCI-E bus connectors.
In still another embodiment of the disclosure the processor module (20) is built on a VPX carrier card.
In still another embodiment of the disclosure the processor module (20) comprises at least one processor (21) with two 4-lane PCI-E interfaces (26A, 26B), said processor (21) comprising memory, DMA controller for memory transfers; PCI-E switch (22) comprising nine ports (27), said port are either 4-lane or 1-lane connection, wherein one 4-lane port is connected to the 4-lane PCI-E interface (26A) of the processor (21), other 4-lane ports are connected or reserved for predetermined processor modules (20) and 1-lane ports are connected to peripherals; a PCI-E to PCI-X bridge (23) connected to the processor (21) using 4-lane interface, wherein the bridge (23) converts serial data to parallel data for provide connectivity to predetermined cards; a PCI-X to VME bridge (25) to provide VME connectivity (30) to predetermined modules on the avionic system is connected to the PCI-E to PCI-X bridge (23); and PCI Mezzanine card (PMC) (24) connected to the PCI-E switch (22) using 4-lane port and PCI-E to PCI-X Bridge (23), wherein PMC (24) provides slots of adding predetermined cards.
In still another embodiment of the disclosure the DMA performs memory transfers between the processor memory and PCI-E memory space.

In still another embodiment of the disclosure multi-processor connectivity between processor modules takes place using PCI-E bus (27).
In still another embodiment of the disclosure the processor (21) connected to slot 1 of the backplane (60) is system controller.
In still another embodiment of the disclosure the PCI-E switches (22) of the processor module (20) connected to the backplane other than slot 1 are upstream ports or non-transparent ports (37).
In still another embodiment of the disclosure the PCI-E switches (22) of the processor module connected to the backplane other than slot 1 are upstream ports or non-transparent ports.
In still another embodiment of the disclosure non-transparent PCI-E switches and interrupts mesh on backplane are used for connecting hierarchical PCI-E bus into processor mesh.
In still another embodiment of the disclosure the PCI-E interface on the processor (21) has translation registers and multiple mapping registers.
In still another embodiment of the disclosure Memory Map Scheme is used with no Address Translation for multi processor communication.
Another embodiment of the disclosure is a method of assembling of avionic system comprising acts of fixing backplane (60) horizontally at bottom of a chassis, wherein backplane comprises slots for predetermined modules; placing processor module cards or Input/ Output (I/O) module cards on the slots of the backplane longitudinally; and connecting Input Output Transition Panel (IOTP) (40) to the backplane at a predetermined slot;
In yet another embodiment of the method the backplane comprises Versa Module Euro-card (VME) bus and PCI-E bus connectors for interconnecting the processor modules, I/O modules and the IOTP (40).

In still another embodiment of the method the IOTP (40) provides circuits for signal protection and for terminating general purpose I/O onto PCI-E bus in order to reduce number of routes on the backplane.
Another embodiment of the disclosure is an Input Output Transition Panel (IOTP) (40) comprising at least one integrated chip(IC) on the IOTP (40) to receive input signals; Input/ Output (I/O) logic (45) to receive plurality of discrete inputs from the sensors; Field Programmable Gated Array (FPGA) (41) to process the I/O logic output to generate a PCI-E (Peripheral Component Interface Express) MSI (message signaled interrupt) and send to backplane (60); An Ethernet switch to provide communication between processor modules of avionic system and external devise; and USB to Ethernet Bridge to provide access of USB connectivity to one of the processor modules.
In yet another embodiment the FPGA (41) is connected to the backplane (60) using PCI-E bus (XI).
The disclosure consists of avionics architecture with multiple processor modules, each processor module being dedicated to one or more aircraft functions, with all modules being interconnected by a high speed backplane with multiple busses for inter-module communication. The multiplicity of busses provides for redundancy and fail-safe operation as well. The busses are implemented in a passive backplane for added reliability. A high-level view of the architecture is shown in Figure 1.
The Multi-processor Multi-Function Avionics Architecture is shown in Figure 1. The details of the all the components of the architecture is shown in the figure 2. Sharing of components allows module re-use, which further reduces cost and enhances reliability. Customization of the modules is then possible for the various functions by adding plug-in modules for I/O interfacing e.g. by adding a module for interfacing to typical aircraft communications busses such as 1553 and Arinc 429, it is possible for the processor to communicate with aircraft flight control systems as an example. Or by adding a video-switching module it is possible to add intelligent video switching and video processing functionality to the same common processor based carrier module.
The Avionic System architecture uses a VME64x or higher version backplane with high end Processors, operating in the -40 to +85 °C range, and cooled via conduction.

The open system architecture approach is adopted, which will enable easy and low-cost changes to hardware and application software satisfying the desired quality attributes of modifiability and reusability, while also achieving the quality attributes of availability, performance, usability, security, and testability.
The avionic system architecture can handle all the input/ outputs (I/O) and perform the intended functions. The system has an integrated modular architecture and interfaces.
The components of the system architecture are described as follows:
Processor Module Description
The Processor Module (20) is built around the form factor of a VPX carrier card. The geographic address (GA) of the processor module (20) determines if the card functions as the system controller for VME, distributes PCI-Express clocks etc. The processor module (20) in slot 1 with GA=1, functions as the system controller. The remaining processor modules are configured differently upon power on.
Figure 3 shows the block diagram of a processor based carrier module (20). The Processor (21) has two 4-lane PCI-Express interfaces. A 9-port PCI-Express switch (22) is connected to one 4-lane port. All inter-module communication is done through this port via the PCI-E switch (22). The switch (22) connects to all other slots in the system (slots 2 through 7) via 4-lane or 1-lane connections. It also connects to an I/O Transition Panel via a single lane PCI-E connection (XI). The 4-lane connection slots (X4) are reserved for slots populated by other processor cards. The 1-lane slots are used to connect to slow-speed peripheral slots and to the spare slot. One 4-lane connection on the PCI-E switch (22) is connected to a local XMC connector (29). This provides us with the flexibility of adding a powerful processing XMC card to the carrier with a lOGbps connection for future use.
The other PCI-Express port on the Processor (21) is also connected to a PCI-Express to PCI-X Bridge (23) using a 4-lane connection (26B). This gives PCI-X connectivity to the on-board PMC (24) daughter cards which can be used for customizing the processing capability of a particular carrier card. A PCI-X to VME Bridge (25) gives VME bus (30) connectivity to all other modules in the system. The VME bus is a

redundant data bus which can be used for communicating with the other modules in the system in case of a failure on the primary PCI-E bus.
When the processor carrier card (20) is used in slots with GA greater than 1 (i.e. not a system controller), then the connection to the PCI-E switch (22) from the Processor (21) reverses direction i.e. the Processor becomes an end-point instead of a root which is shown in the figure 4. Also, in that case the PCI-E switch (22) is used as a non-transparent PCI-E switch, so that the local ports are isolated from the main Processor which is acting as the system controller.
Inter Processor Connectivity
Multi-processor connectivity takes place via PCI-Express (70) connections. Each processor (21) has DMA controllers which can do memory transfers from local DDR2 memory to PCI-Express memory space. The figure 3 shows the multi-processor connectivity. The same physical board can be configured to have the PCI-E switch (22) port connected to the processor (21) as either a downstream port (if in slot 1), or as an upstream port if in any other slot. This configuration selection is made during up power-up reset of the PCI-E switch. When the processor board is plugged into any other slot than slot 1, the root port or downstream port is the port connected to the backplane (60).
In Slot 1 (32), the PCI-E switch port (36) facing the MPC is labeled "U" for upstream, but in the other three slots, the slot facing the backplane (60) is labeled "U". Hence, the software will need to the PCI-E port in all other slots as an end-point, whereas the PCI-E port in slot 1 is configured as a root-complex. Similarly, the PCI-X to VME Bridge (25) in slot 1 is the only one configured as a system controller (21 SC).
The ability of the PCI-E switch (22) to support a non-transparent port is also taken advantage of. As shown in the figure 3, except in slot 1, the upstream port labeled "U" in slots 2, 3, and 4 is also labeled "NT" (37). When the PCI-E switch (22) is powered up in any slot other than the system controller slot (GA = 1), the upstream port is configured to be non-transparent. Hence the local processor (21) and all the downstream ports on the PCI-E switch including the port connected to the XMC

connector (29) are all locally configured and hidden from the global PCI-E space, except for the space chosen to be globally exposed by the local processor (21).
PCI-Express Hierarchy
Figure 5 shows the global PCI-E hierarchy which is derived from the above description of the PCI-Express configuration of the Processor board. The second PCI-Express port is not shown in the following diagram, since it is primarily connected to local devices and is not used for mapping the global PCI memory space.
The XMC based modules (38) on the processor cards are not available in the global space until the local processor (21) exposes the XMC module space to the global PCI-E space.
All general aircraft inputs and outputs, such as discrete signals as well as analog signals are available via the PCI-E bus to any of the Processor cards and thus these inputs and outputs do not need to be routed to particular slots. This provides the ability to share aircraft I/O between processing modules, and also provides flexibility in terms of being able to move processing functions among Processor modules (20) for proper load-balancing. Additionally, the architecture provides flexibility in terms of not having cables or wires from I/O to a particular slot. Thus, this architecture reduces the density of the backplane (60) connections.
Global PCI Memory Map
Due to the availability of outbound and inbound translation registers for the PCI-Express interface on the processor (21), it is not necessary to use non-transparent bridges or switches on the processor card. With the multiple mapping registers and both outbound and inbound address translation available, it is possible to map memory in such a way as to not require address translation on pointers that are passed from one processor (21) to another.
Figure 5 shows the Memory Map Scheme with no address translation. In the memory map as shown in figure 5, Processor (21) 0's memory space is split into a private local memory space from 0 to 192MB, and another 16 MB of shared memory space from 192MB to 208 MB. Processor (21) l's memory space is split into a private local memory space from 0 to 192 MB, and another 16MB from 208MB to 224MB. When

Processor 1 passes a memory pointer to its shared memory to Processor 2, then Processor 2 can use that memory pointer without any modification or further address translation. The reason for this is that the PCI-Express memory map window will automatically map accesses between 208MB and 224MB to PCI-Express space, and Processor 1 will decode the global PCI-E address in that range to a slave access of its own internal DDR memory. The above scheme wastes some DDR memory but has the advantage of not requiring address translations in software. This Memory Mapping scheme is simpler to code and debug and is less error prone.
Module Connectivity
The modules are inter-connected via the following 3 backplane busses:
VME (Vita 46) is a Legacy data plane bus,
PCI-Express is a data plane bus for new modules, and
I2C is a management plane.
Figure 7 shows the module data path connectivity. As shown in figure 7 the inter module connectivity, VME (30) is available as a VITA46 backplane (60) connection on all slots, and can be used as a redundant data path or for legacy cards or for connecting to off-the-shelf cards.
Aircraft I/O Handling
An 10 Transition panel (40) is used to terminate the Discrete I/Os. IOTP is a 3 layer board stacks up with efficient placement and routing to make it Cable less Design. A single PCI-E lane (XI) is available from the global PCI-E space at the IO Transition panel. . The PCI-E switch connects PCI-E to a PCI-E to Local Bus Bridge (43) to interface these I /Os (45) to the global PCI memory space. All of the four processor cards can then access these I/Os. In addition, a 6 port Ethernet switch (62) is used in IOTP (40) for communication to any processor module inside the unit to outside world as shown in the figure 10. The USB to Ethernet Bridge (63) at IOTP (40) permits any one of the processor cards to gain access through the USB connections (64) to the outside world.

Figure 8 shows the aircraft I/O handling. An FPGA (41) can generate a PCI-E MSI (Message Signaled Interrupt) to one of the processor based cards when a particular discrete or analog event occurs.
An 10 transition panel (40) that plugs into the backplane (60) is used to terminate aircraft I/O signals (45A). Signals from the aircraft are routed from the 10 transition panel (40) to connectors on the backplane (60) which will allow these signals to be further routed to the appropriate processor modules (20). Since all general aircraft discrete I/Os (45A) are terminated on the I/O transition panel (40) itself, it is not necessary to route these signals to individual processor modules.
IOTP is a 3 layer board stacks up with efficient placement and routing to make it cable less design which is shown in the figure 9.
The avionic system architecture provides the following applications:
• Digital Map generator
• Symbol Generator
• Video Format Conversion and switching
• Display Management
• Navigation and Weapon Guidance
• Sensor Management
• Bus Control and Monitor
• Redundancy Management
• Interface with all the LRUs
• Interface with HUD and UFCP via Serial Bus
• Health Monitoring
• Failure Management
The above applications functions are further partitioned based on the task, Roles and Responsibilities. The partitioned application will be hosted in the respective processor module.
Finally, while the present disclosure has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed

as limiting the invention. Various modifications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.

We claim:
1. An avionics system architecture comprising:
a. Input Output Transition Panel (IOTP) (40) to convert plurality of input/output
discrete lines to single input/output interface;
b. Backplane (60) placed in a chassis to receive the data from the input/output
interface of the IOTP (40), wherein IOTP (40) is plugged into said backplane,
and the backplane (60) comprises slots for placing predetermined module cards;
c. at least one processor module (20) and/or Input/ Output (I/O) module placed on
the backplane slots to send/receive data from IOTP (40), wherein each processor
module (20) comprises a processor (21) with at least one 4-lane PCI-E
(Peripheral Component Interface Express) interface, PCI-E switch (22), PCI-E/
PCI-X bridge (23) and PMC connector (24), wherein said processor modules
(20) controls at least one predetermined function of the avionic system; and
d. PCI-E (27) and Versa Module Euro card (VME) (30) buses to interconnect the
processor modules (20) for inter-communication.
2. The system as claimed in claim 1, wherein the single input/output interface of the IOTP (40) is PCI-E bus single lane.
3. The system as claimed in claim 1, wherein the IOTP (40) comprises I/O logic to send/receive discrete input/output (45A), Field Programmable Gated Array (FPGA) (41) to receive the input/output from the I/O logic (45) input/output, process and send out on a single PCI-E lane (XI) to the backplane (60).
4. The system as claimed in claim 1, wherein the IOTP (40) eliminates internal cabling using efficient placement and routing.
5. The system as claimed in claim 1, wherein the IOTP (40) provides circuits for signal protection using active and passive circuitry for electrical protection, surge protection, EMI suppression, and for terminating general purpose I/O onto the PCI-E bus in order to reduce number of routes on the backplane (60).
6. The system as claimed in claim 1, wherein the backplane is Vita46 backplane architecture.

7. The system as claimed in claim 1, wherein the backplane comprises Versa Module Euro-card (VME) bus and PCI-E bus connectors.
8. The system as claimed in claim 1, wherein the processor module (20) is built on a VPX carrier card.
9. The system as claimed in claim 1, wherein the processor module (20) comprises:
a. at least one processor (21) with two 4-lane PCI-E interfaces (26A, 26B), said
processor (21) comprising memory, DMA controller for memory transfers;
b. PCI-E switch (22) comprising nine ports (27), said port are either 4-lane or 1-
lane connection, wherein one 4-lane port is connected to the 4-lane PCI-E
interface (26A) of the processor (21), other 4-lane ports are connected or
reserved for predetermined processor modules (20) and 1-lane ports are
connected to peripherals;
c. a PCI-E to PCI-X bridge (23) connected to the processor (21) using 4-lane
interface, wherein the bridge (23) converts serial data to parallel data for
provide connectivity to predetermined cards;
d. a PCI-X to VME bridge (25) to provide VME connectivity (30) to
predetermined modules on the avionic system is connected to the PCI-E to PCI-
X bridge (23); and
e. PCI Mezzanine card (PMC) (24) connected to the PCI-E switch (22) using 4-
lane port and PCI-E to PCI-X Bridge (23), wherein PMC (24) provides slots of
adding predetermined cards.
10. The system as claimed in claim 1, wherein the DMA performs memory transfers between the processor memory and PCI-E memory space.
11. The system as claimed in claim 1, wherein multi-processor connectivity between processor modules takes place using PCI-E bus (27).
12. The system as claimed in claim 1, wherein the processor (21) connected to slot 1 of the backplane (60) is system controller.
13. The system as claimed in claim 1, wherein the PCI-E switch (22) of the processor module connected to slot 1 of the backplane is downstream port.

14. The system as claimed in claim 1, wherein the PCI-E switches (22) of the processor module (20) connected to the backplane other than slot 1 are upstream ports or non-transparent ports (37).
15. The system as claimed in claim 1 or 14, wherein non-transparent PCI-E switches and interrupts mesh on backplane are used for connecting hierarchical PCI-E bus into processor mesh.
16. The system as claimed in claim 9, wherein the PCI-E interface on the processor (21) has translation registers and multiple mapping registers.
17. The system as claimed in claim 1 or 9, wherein Memory Map Scheme is used with no Address Translation for multi processor communication.
18. A method of assembling of avionic system comprising acts of:
a. fixing backplane (60) horizontally at bottom of a chassis, wherein backplane
comprises slots for predetermined modules;
b. placing processor module cards or Input/ Output (I/O) module cards on the slots
of the backplane longitudinally; and
c. connecting Input Output Transition Panel (IOTP) (40) to the backplane at a
predetermined slot;
19. The method as claimed in claim 18, wherein the backplane comprises Versa Module Euro-card (VME) bus and PCI-E bus connectors for interconnecting the processor modules, I/O modules and the IOTP (40).
20. The method as claimed in claim 18, wherein the IOTP (40) provides circuits for signal protection and for terminating general purpose I/O onto PCI-E bus in order to reduce number of routes on the backplane.
21. An Input Output Transition Panel (IOTP) (40) comprising:
a. at least one integrated chip(IC) on the IOTP (40) to receive input signals;
b. Input/ Output (I/O) logic (45) to receive plurality of discrete inputs from the
sensors;

c. Field Programmable Gated Array (FPGA) (41) to process the I/O logic output to
generate a PCI-E (Peripheral Component Interface Express) MSI (message
signaled interrupt) and send to backplane (60);
d. An Ethernet switch to provide communication between processor modules of
avionic system and external devise; and
e. USB to Ethernet Bridge to provide access of USB connectivity to one of the
processor modules.
22. The IOTP (40) as claimed in claim 20, wherein the FPGA (41) is connected to the backplane (60) using PCI-E bus (XI).

Dated this 23rd day of October, 2009.

NAVEEN.C
OF K & S PARTNERS
AGENT FOR THE APPLICANT