Claims:1. A S band 7-bit GaAs MMIC digital attenuator (100), the attenuator (100) comprising:
a set of seven attenuation bits (102) electrically coupled to each other, wherein each of the attenuation bit (102) comprises one or more FET based switches (SW1, SW2), and having predefined attenuation values;
a set of first capacitors (106) having a predefined first capacitance value electrically coupled at a Radio Frequency (RF) input port (104-1) and a RF output port (104-2) of the attenuator (100), configured to block flow of Direct Current (DC) to the RF input port (104-1) and the RF output port (104-2), and facilitate impedance matching; and
a resistive matching circuit (110) comprising a thin film resistor of predefined resistance being electrically coupled at the RF output port (104-2) of the attenuator (100),
wherein the set of seven attenuation bits (102) are operatively coupled to a driver logic controller that is configured to change states of corresponding attenuation bits (102), and the attenuator (100) from 0 to 127 with a step size of 0.25dB.
2. The attenuator (100)as claimed in claim 1, wherein the set of seven attenuation bits (102) comprises:
a set of two attenuation bits (102-1, 102-7) comprising corresponding FET based switch (SW1, SW2) in shunt-topology, and the predefined attenuation values of 0.25dB, and 0.5dB, respectively;
a set of four attenuation bits (102-3, 102-4, 102-5, 102-6) comprising the corresponding FET based switches (SW1, SW2) in T-topology, having the predefined attenuation values of 1dB, 2dB, 4dB, and 8dB, respectively; and
one attenuation bit (102-2) comprising the corresponding FET based switches (SW1, SW2) in a SPDT topology, and having the predefined attenuation value of 16dB.
3. The attenuator (100) as claimed in claim 2, wherein the attenuation bit (102-2) having the SPDT topology is configured between the RF input port (104-1) and a first end of the set of four attenuation bits (102-3, 102-4, 102-5, 102-6) having T-topology, and wherein a first attenuation bit (102-1) among the set of two attenuation bits (102-1, 102-7)having shunt topology is configured between the RF input port (104-1) and a first end of the attenuation bit (102-2) having SPDT-topology, and a second attenuation bit (102-7) among the set of two attenuation bits (102-1, 102-7) having shunt topology is configured between the RF input port (104-1) and the RF output port (104-2) and a second end of the set of four attenuation bits (102-3, 102-4, 102-5, 102-6) having T-topology.
4. The attenuator (100) as claimed in claim 1, wherein the attenuator (100) comprises a set of spiral inductors (108) of predefined inductance configured on two ends of the attenuation bit (102-2) having the SPDT topology, to match impedance of the attenuation bit (102-2) having the SPDT topology with the adjacent attenuation bits (102) having the shunt-topology and the T-topology.
5. The attenuator (100) as claimed in claim 1, wherein the attenuator (100) comprises an Electro Static Discharge (ESD) protection circuit (400) on bit control lines and supply lines to prevent the attenuator (100) from electro static discharge.
6. The attenuator (100) as claimed in claim 5, wherein the protection circuit (400) comprises a plurality of forward biased diodes (D1-D5), and a plurality of reveres biased diodes (D6-D7) configured with the bit control lines of the attenuator(100), wherein the plurality of forward biased diodes (D1-D5) comprises a set of five series connected diodes connected between the bit control lines and a ground, and the plurality of reverse biased diodes (D6-D7) comprises a set of two series connected diodes connected to between the bit control lines and the ground.
7. The attenuator (100) as claimed in claim 1, wherein the attenuator (100) is fabricated using a 0.25 µmGallium Arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT), and the attenuator (100) is adapted for S band range of 3 to 3.6 GHz.
8. The attenuator (100) as claimed in claim 1, wherein each of the one or more FET based switches (SW1, SW2) have bigger periphery to provide input third order intercept point (IIP3) of 45dBm across the S band, and wherein a gate of each of the one or more FET based switch (SW1, SW2) has a MESA resistor of 3 Kilo Ohm to prevent RF leakage to DC control circuitry of the attenuator (100).
9. The attenuator (100) as claimed in claim 1, wherein the attenuator (100) comprises two series resistors having resistance greater than 500 Ohms being configured at the RF DC crossover of the attenuator (100) to restrict RF signal coupling to DC lines; and
wherein the set of first capacitors (106) have the predefined first capacitance value of 40pF.
10. The attenuator (100) as claimed in claim 1, wherein the set of seven attenuation bits (102) are controlled by the driver logic controller using gate voltage of the corresponding FET based switches (SW1, SW2), and
wherein the attenuator (100) comprises a 5 kilo Ohm MESA resistor configured between ground and RF transmission lines to ensure 0V potential at source and drain of the set of FET based switches (SW1, SW2) to control switching ON and OFF of the FET based switches (SW1, SW2) without going to an unknown state.
, Description:TECHNICAL FIELD
[0001] The present disclosure relates to the field of communication system. More particularly, the present disclosure relates to a better IIP3, low insertion phase shift, well matched S-band 7 bit GaAs MMIC digital attenuator.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Phased array antennas are known for their capability to steer the beam pattern electronically in an effective manner achieving minimal side lobe levels and narrow beam widths. A digital attenuator is an essential component of the phased array system that provides the necessary attenuation to each element in the antenna array. Many digital attenuators with smaller size and low power consumption are required to realize a single phase array system. The digital attenuator offers signal level adjustments, better linearity and high attenuation accuracy. GaAs (Gallium Arsenide) Digital attenuator Monolithic microwave integrated circuit (MMICs) achieves small size, less weight and less power consumption at lower cost. The digital attenuators will help to balance the signals between different channels and supply amplitude conditioning.
[0004] GaAs pseudomorphic High-Electron-Mobility Transistor (pHEMT) process with high frequency responses and attenuator topologies with low phase shift are adopted in design to achieve high performance. Faster switching is possible using pHEMT switches. In a digital attenuator, various individual bits are cascaded to achieve the desired value of attenuation. In a digital attenuator, Least Significant Bit (LSB) determines minimum resolvable level and Most Significant Bit (MSB) determines the range of attenuation.
[0005] The United States Patent Document Number US6489856 discloses a circuit to improve frequency response and reduce insertion loss of a multi bit digital attenuator. The cited prior art document provides an additional shunt circuit in the middle of a temperature compensation circuit. This provided the flexibility to combine bits using a single series FET, so that frequency response can be maintained, with reduced reference state insertion loss. However, the circuit may deteriorate phase performance across the states of digital attenuator.
[0006] Another United Patent Document Number US9787286 discloses a wide band Radio Frequency (RF) digital attenuator by utilising quarter wave transmission lines at the signal interface of every attenuation. Low phase shift is achieved in the digital attenuator by utilizing a switched signal path attenuator topology with multiple distributed transmission line elements per signal path to get broadband operation and this will improve isolation to get higher attenuation at higher frequencies with minimal phase shift. However, this approach leads to lengthy transmission lines, which may impact on miniaturization of the attenuator.
[0007] The Korean Patent Document Number KR101030050B1 encompasses a digital attenuator with low phase variation by connecting a low pass filter with a serial resistance to a series switch in parallel. Generally, in a digital attenuator, difference in the parasitic components according to turn –on or turn-off of switching transistor brings phase difference. Low pass filter section with a series resistance, connected in parallel to switch will remove parasitic components. However, the cited prior art document does not give detail about techniques for high return loss and IIP3.
[0008] The PCT Number WO2017095519A1 discloses a wideband attenuator that has reduced impact on the phase of an applied signal when switched between attenuation state and non-attenuation reference. Low phase is achieved with multiple distributed transmission lines between the stages. However, the cited prior art document is not feasible for narrow band, lower frequency monolithic digital attenuator.
[0009] Another United Patent Document Number US9444432 discloses a method to improve phase variation of digitally controlled attenuator. To control relative phase variation, in each bit of attenuator has a series inductor between input and resistor of the cell to fix pole location of that bit transfer function. Compensation capacitors are also helped to control pole location. However, the cited prior art document does not aid in low frequency compact designs.
[0010] Therefore, there is a need in the art for providing a better IIP3, low insertion phase shift, well matched S-band 7 Bit GaAs MMIC digital attenuator. Particularly, the present invention provides 0.25µm GaAs pHEMT based S band 7 bit MMIC digital attenuator to address and solve the above mentioned limitations. The proposed digital attenuator provides compact and low cost solutions for AESA RADAR applications.

OBJECTS OF THE PRESENT DISCLOSURE
[0011] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.
[0012] It is an object of the present disclosure to provide better IIP3, low insertion phase shift, well matched S-band 7 Bit GaAs MMIC digital attenuator.
[0013] It is an object of the present disclosure to provide inductive matching of individual bits using transmission line to get better return loss. Further, lengthy transmission line is required to be avoided as a part of layout optimization.
[0014] It is an object of the present disclosure to obtain improved return loss near the RF port.
[0015] It is an object of the present disclosure to achieve a better IIP3 requirement by using bigger device peripheries in attenuation bits.
[0016] It is an object of the present disclosure to handle RF to digital circuit leakage for faster switching and without compromising on insertion loss.

SUMMARY
[0017] The present disclosure relates to the field of communication system. More particularly, the present disclosure relates to a better IIP3, low insertion phase shift, well matched S-band 7 bit GaAs MMIC digital attenuator.
[0018] An aspect of the present disclosure pertains to the S band 7-bit GaAs MMIC digital attenuator.Theattenuator comprises a set of seven attenuation bits electrically coupled to each other. Further, each of the attenuation bit comprises one or more FET based switches which are associated with predefined attenuation values. The attenuator comprises a set of first capacitors having a predefined first capacitance value. The set of first capacitors are electrically coupled at a Radio Frequency (RF) input port and a RF output port of the attenuator. The set of first capacitors are configured in order to block the flow of Direct Current (DC) to the RF input port and the RF output port and facilitate impedance matching. The attenuator comprises a resistive matching circuit comprising a thin film resistor of predefined resistance being electrically coupled at the RF output port of the attenuator. The set of seven attenuation bits are operatively coupled to a driver logic controller that is configured to change states of corresponding attenuation bits, and the attenuator from 0 to 127 with a step size of 0.25dB.
[0019] In an aspect,a set of two attenuation bits amongthe set of seven attenuation bits are corresponding FET based switch in shunt-topology. The predefined attenuation values of the set of two attenuation bits are 0.25dB, and 0.5dB, respectively. Further, a set of four attenuation bits among the seven attenuation bitscomprises the corresponding FET based switches in T-topology. The predefined attenuation values of the set of four attenuation bits are 1dB, 2dB, 4dB, and 8dB, respectively. Finally, one attenuation bit among the seven attenuation bitscomprises the corresponding FET based switches in a SPDT topology. The predefined attenuation value of the set of one attenuation bit is 16dB.
[0020] In an aspect, the attenuation bit comprises the SPDT topology configured between the RF input port and a first end of the set of four attenuation bits having T-topology. A first attenuation bit among the set of two attenuation bits having shunt topology is configured between the RF input port and a first end of the attenuation bit having SPDT-topology. A second attenuation bit among the set of two attenuation bits having shunt topology is configured between the RF input output port and a second end of the set of four attenuation bits having T-topology.
[0021] In an aspect, the attenuator comprises a set of spiral inductors of predefined inductance which are configured on two ends of the attenuation bit having the SPDT topology. The spiral inductors of the attenuator are configured in order to match impedance of the attenuation bit having the SPDT topology with the adjacent attenuation bits having the shunt-topology and the T-topology.
[0022] In an aspect, the attenuator comprises an Electro Static Discharge (ESD) protection circuit on bit control lines and supply lines to prevent the attenuator from electro static discharge.
[0023] In an aspect, the protection circuit of the attenuator comprises a plurality of forward biased diodes, and a plurality of reveres biased diodes configured with the bit control lines of the attenuator. The plurality of forward biased diodes comprises a set of five series connected diodes connected between the bit control lines and a ground. Further, the plurality of reverse biased diodes comprises a set of two series connected diodes connected to between the bit control lines and the ground.
[0024] In an aspect, the attenuator is fabricated using a 0.25 µmGallium Arsenide (GaAs) pseudomorphic High Electron Mobility Transistor (pHEMT) with die size of 2.6 mm X 2.5 mm in X and Y respectively, with on chip DC- blocking capacitor at the RF input port and the RF output port, and the attenuator is adapted for S band range of 3 to 3.6 GHz.
[0025] In an aspect, each of the one or more FET based switches have bigger periphery to provide Input third order Intercept Point (IIP3) of 45dBm across the S band. A gate of each of the one or more FET based switch has a MESA resistor of 3 Kilo Ohm to prevent RF leakage to DC control circuitry of the attenuator.
[0026] In an aspect, the attenuator comprises two series resistors having resistance greater than 500 Ohms being configured at the RF DC crossover of the attenuator to restrict RF signal coupling to DC lines. The set of first capacitors have the predefined first capacitance value of 40pF.
[0027] In an aspect, the set of seven attenuation bits are controlled by the driver logic controller using gate voltage of the corresponding FET based switches. The attenuator comprises a 5 kilo Ohm MESA resistor configured between ground and RF transmission lines to ensure 0V potential at source and drain of the set of FET based switches to control switching ON and OFF of the FET based switches without going to an unknown state.

BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0029] The diagrams are for illustration only, which thus is not a limitation of the present disclosure, and wherein:
[0030] FIG. 1 illustrates an exemplary circuit diagram of the proposed S band 7-bit GaAs MMIC digital attenuator, in accordance with an exemplary embodiment of the present disclosure.
[0031] FIG. 2 illustrates an exemplary circuit comprising series resistors added across RF–DC crossoversin the attenuation bits of the proposed attenuator, in accordance with an exemplary embodiment of the present disclosure.
[0032] FIG. 3 illustrates an exemplary connection of high value shunt resistors added on RF lines of the proposed attenuator, in accordance with an exemplary embodiment of the present disclosure.
[0033] FIG. 4 illustrates an exemplaryElectro Static Discharge (ESD) protection circuit of the propsoed attenuator, in accordance with an exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION
[0034] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0035] Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[0036] In some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[0037] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0038] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0039] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.
[0040] The present disclosure relates to the field of communication system. More particularly, the present disclosure relates to a better IIP3, low insertion phase shift, well matched S-band 7 bit GaAs MMIC digital attenuator.
[0041] According to an aspect, the present disclosure pertains to the S band 7-bit GaAs MMIC digital attenuator (100). The attenuator(100)can include a set of seven attenuation bits (102-1, 102-2, 102-3, 102-4, 102-5, 102-6 and 102-7) (also collectively referred as (102), herein)electrically coupled to each other. Further, each of the attenuation bit (102) can include one or more FET based switches (SW1, SW2) which are associated with predefined attenuation values. The attenuator (100) can include a set of first capacitors (106) having a predefined first capacitance value. The set of first capacitors (106) can be electrically coupled at a Radio Frequency (RF) input port (104-1) and a RF output port (104-2) of the attenuator (100). The set of first capacitors (106) can be configured in order to block the flow of Direct Current (DC) to the RF input port (104-1) and the RF output port (104-2) and facilitate impedance matching. The attenuator (100) can includea resistive matching circuit (110) including a thin film resistor of predefined resistance being electrically coupled at the RF output port (104-2) of the attenuator (100). The set of seven attenuation bits (102) can be operatively coupled to a driver logic controller that is configured to change states of corresponding attenuation bits (102), and the attenuator (100) from 0 to 127 with a step size of 0.25dB.
[0042] In an embodiment, a set of two attenuation bits (102-1, 102-7) among the set of seven attenuation bits (102) can becorresponding FET based switch(SW1, SW2) in shunt-topology. The predefined attenuation values of the set of two attenuation bits (102-1, 102-7) can be0.25dB, and 0.5dB, respectively. Further, a set of four attenuation bits (102-3, 102-4, 102-5, 102-6) among the seven attenuation bits(102) can includethe corresponding FET based switches(SW1, SW2) in T-topology. The predefined attenuation values of the set of four attenuation bits (102-3, 102-4, 102-5, 102-6) can be1dB, 2dB, 4dB, and 8dB, respectively. Finally, one attenuation bit (102-2) among the seven attenuation bits (102) can include the corresponding FET based switches (SW1, SW2) in a SPDT topology. The predefined attenuation value of the set of one attenuation bit (102-2) can be16dB.
[0043] In an embodiment, the attenuation bit (102-2) can include the SPDT topology configured between the RF input port (104-1) and a first end of the set of four attenuation bits (102-3, 102-4, 102-5, 102-6) having T-topology. A first attenuation bit among the set of two attenuation bits (102-1, 102-7) having shunt topology can be configured between the RF input port (104-1) and a first end of the attenuation bit (102-2) having SPDT-topology. A second attenuation bit among the set of two attenuation bits (102-1, 102-7) having shunt topology can be configured between the RF input port (104-1) and the RF output port and a second end of the set of four attenuation bits (102-3, 102-4, 102-5, 102-6) having T-topology.
[0044] In an embodiment, the attenuator (100) can include a set of spiral inductors (108) of predefined inductance which are configured on two ends of the attenuation bit (102-2) having the SPDT topology. The spiral inductors of the attenuator can be configured in order to match impedance of the attenuation bit (102-2) having the SPDT topology with the adjacent attenuation bits (102) having the shunt-topology and the T-topology.
[0045] In an embodiment, the attenuator can include an Electro Static Discharge (ESD) protection circuit (400) on bit control lines and supply lines to prevent the attenuator from electro static discharge.
[0046] In an embodiment, the ESDprotection circuit (400) of the attenuator (100) can include a plurality of forward biased diodes (D1-D5), and a plurality of reveres biased diodes (D6-D7) configured with the bit control lines of the attenuator (100). The plurality of forward biased diodes (D1-D5) can include a set of five series connected diodes connected between the bit control lines and a ground. Further, the plurality of reverse biased diodes (D6-D7) can include a set of two series connected diodes connected between the bit control lines and the ground.
[0047] In an embodiment,the attenuator (100)can be fabricated using a 0.25 µmGallium Arsenide (GaAs) pseudomorphic High Electron Mobility Transistor (pHEMT), and the attenuator is adapted for S band range of 3 to 3.6 GHz.
[0048] In an embodiment, each of the one or more FET based switches (SW1, SW2) can have bigger periphery to provide Input third order Intercept Point (IIP3) of 45dBm across the S band. A gate of each of the one or more FET based switch (SW1, SW2) can have a MESA resistor of 3 Kilo Ohm to prevent RF leakage to DC control circuitry of the attenuator (100).
[0049] In an embodiment, the attenuator (100) can include two series resistors having resistance greater than 500 Ohms being configured at the RF DC crossover of the attenuator to restrict RF signal coupling to DC lines. The set of first capacitors (106) can have the predefined first capacitance value of 40pF.
[0050] In an embodiment, the set of seven attenuation bits (102)can be controlled by the driver logic controller using gate voltage of the corresponding FET based switches(SW1, SW2). The attenuator (100)can include a 5 kilo Ohm MESA resistor configured between ground and RF transmission lines to ensure 0V potential at source and drain of the set of FET based switches (SW1, SW2) to control switching ON and OFF of the FET based switches (SW1, SW2) without going to an unknown state.
[0051] FIG. 1 illustrates an exemplary circuit diagram of the proposed S band 7-bit GaAs MMIC digital attenuator, in accordance with an exemplary embodiment of the present disclosure.
[0052] As illustrated in FIG. 1, the S band 7-bit GaAs MMIC digital attenuator (100)(also referred as attenuator (100), herein)can includevarious components such as a set of seven attenuation bits (102), FET based switches(SW1, SW2), a set of spiral inductors (108), a set of first capacitors (106), a resistive matching circuit (110), a Radio Frequency (RF) input port (104-1) and a RF output port (104-2). Theset of seven attenuation bits (102) can be electrically coupled to each other. Each of the attenuation bit (102) comprises one or more FET based switches (SW1, SW2). Also, the attenuation bits (102) can have predefined attenuation values.
[0053] In an embodiment, a set of two attenuation bits (102-1, 102-7) among the set of seven attenuation bits (102) can have the corresponding FET based switch (SW1, SW2) in shunt-topology. The predefined attenuation values of the set of two attenuation bits (102-1, 102-7) can be0.25dB, and 0.5dB, respectively. A first attenuation bit among the set of two attenuation bits (102-1, 102-7) having shunt topology can be configured between the RF input port (104-1) and a first end of the attenuation bit (102-2) having SPDT-topology. Further, a second attenuation bit among the set of two attenuation bits (102-1, 102-7) having shunt topology can be configured between the RF input port (104-1) and the RF output port (104-2) and a second end of the set of four attenuation bits (102-3, 102-4, 102-5, 102-6) having T-topology.
[0054] In an embodiment, a set of four attenuation bits (102-3, 102-4, 102-5, 102-6) among the seven attenuation bits (102) can have the corresponding FET based switches (SW1, SW2) in T-topology. The predefined attenuation values of the set of four attenuation bits (102-3, 102-4, 102-5, 102-6) can be1dB, 2dB, 4dB, and 8dB, respectively. The attenuation bits (102-3, 102-4, 102-5, 102-6) having the SPDT topology can be configured between the RF input port (104-1) and a first end of the set of four attenuation bits (102-3, 102-4, 102-5, 102-6) having T-topology
[0055] In an embodiment, one attenuation bit (102-2) among the seven attenuation bits (102) can have the corresponding FET based switches (SW1, SW2) in a SPDT topology. The predefined attenuation value of the set of one attenuation bit is 16dB.The attenuation bit (102-2) having the SPDT topology can be configured between the RF input port (104-1) and a first end of the set of four attenuation bits (102-3, 102-4, 102-5, 102-6) having T-topology.A first attenuation bit (102-1) among the set of two attenuation bits(102-1, 102-7) having shunt topology can be configured between the RF input port (104-1) and a first end of the attenuation bit (102-2) having SPDT-topology, and a second attenuation bit (102-7) among the set of two attenuation bits (102-1, 102-7) having shunt topology can be configured between the RF input port (104-1) and the RF output port and a second end of the set of four attenuation bits (102-3, 102-4, 102-5, 102-6) having T-topology.
[0056] In an exemplary embodiment, each of the one or more FET based switches (SW1, SW2) can have bigger periphery to provide input third order intercept point (IIP3) of 45dBm across the S band. A gate of each of the one or more FET based switch (SW1, SW2) can have a MESA resistor of 3 Kilo Ohm to prevent RF leakage to DC control circuitry of the attenuator (100).
[0057] In an embodiment, the set of first capacitors (106) of the attenuator (100) having a predefined first capacitance value electrically coupled at a Radio Frequency (RF) input port (104-1) and a RF output port (104-2) of the attenuator (100), configured to block flow of Direct Current (DC) to the RF input port (104-1) and the RF output port (104-2), and facilitate impedance matching. The set of first capacitors (106) can have the predefined first capacitance value of 40pF.
[0058] In an exemplary embodiment, the resistive matching circuit (110) can includea thin film resistor of predefined resistance being electrically coupled at the RF output port (104-2) of the attenuator (100). The set of seven attenuation bits (102) can be operatively coupled to a driver logic controller that is configured to change states of corresponding attenuation bits, and the attenuator from 0 to 127 with a step size of 0.25dB.
[0059] In an embodiment, the attenuator (100) can include a set of spiral inductors (108) of predefined inductance, which can be configured on two ends of the attenuation bit (102-2) having the SPDT topology. The set of spiral inductors (108) can be configured to match impedance of the attenuation bit (102-2) having the SPDT topology with the adjacent attenuation bits (102) having the shunt-topology and the T-topology.
[0060] In an embodiment, the attenuator (100) comprises two series resistors having resistance greater than 500 Ohms being configured at the RF DC crossover of the attenuator (100) to restrict RF signal coupling to DC lines.
[0061] In an embodiment, the set of seven attenuation bits (100) can be controlled by the driver logic controller using gate voltage of the corresponding FET based switches(SW1, SW2). In an exemplary embodiment, the attenuator (100) comprises a 5 kilo Ohm MESA resistor which can be configured between ground and RF transmission lines to ensure 0V potential at source and drain of the set of FET based switches (SW1, SW2), thereby enabling switching ON and OFF of the FET based switches (SW1, SW2) can be controlled without going to an unknown state.
[0062] In an embodiment, the attenuator (100) can be fabricated using a 0.25 µm Gallium Arsenide (GaAs) pseudomorphic High Electron Mobility Transistor (pHEMT), and the attenuator is adapted for S band range of 3 to 3.6 GHz.
[0063] The proposed attenuator (100) achieves enhanced attenuation accuracy better than ±0.35dB typical over all 127 states across S-Band frequency range. Typical measured IIP3 (Third order input intercept point) of 45dBm across the band. Further, return losses are computed better than 18dB at the RF input port (104-1) and the RF output port (104-2) in full band for 127 attenuation states typically. An un-calibrated Root Mean Square (RMS) attenuation error is better than 0.15dB in the band. Calibrated RMS phase error is better than 0.72 degree in the band. Typical Phase variation across the S-band is in the range from -3 to 1 degree. Typically, supply voltages for operation can be +5V, -5V with current consumption of 11 mA. Further, RF pad size can be 160um x160um in order to accommodate minimum 2 bond wires at the RF input port (104-1) and the RF output port (104-2). DC pad dimension of 100um x100um can be used for controlling external voltage interface.
[0064] FIG. 2 illustrates an exemplary circuit comprising series resistors which are added across RF –DC crossoversin the attenuation bits of the proposed attenuator, in accordance with an exemplary embodiment of the present disclosure.
[0065] As illustrated in FIG. 2, the circuit (200) illustrates RF-DC crossover, which can include two series resistors (201,202). The series resistors (201,202) can be added at RF to DC crossover (200) to reduce leakage. DC-RF crossovers can be allowed in the attenuator (100)to avoid RF signal coupling to DC lines, series resistors (201,202), higher than 500Ohm, are used in RF–DC crossover areas (200) on control lines. Also, the series resistors (201, 202) can be used in RF–DC crossover areas to avoid coupling. Further, high value resistors to ground are used to prevent floating of the switch.FET based switches (SW1, SW2). 3KiloOhm resistors are used at the gate of each FET based switches (SW1, SW2) to getter better switching speed and to prevent RF signal leakage to digital circuit without too much degradation in insertion loss.
[0066] FIG. 3 illustrates an exemplary connection of high value shunt resistors added on RF lines of the proposed attenuator, in accordance with an exemplary embodiment of the present disclosure.
[0067] In an embodiment, the FET based switches (SW1, SW2) can be controlled using Gate voltage. The high value shunt resistors can be added on RF lines. The high value 5KiloOhm MESA resistors to ground (300), which can be connected in RF transmission lines, to ensure 0V potential at source and drain of the FET. Thus, ON and OFF states of the FET based switches (SW1, SW2) can be ensured based on gate control without going to unknown state.
[0068] FIG. 4 illustrates an exemplary Electro Static Discharge (ESD)protection circuit of the propsoed attenuator, in accordance with an exemplary embodiment of the present disclosure.
[0069] In an embodiment, the ESD protection circuit(400) of the propsoed attenuator is discloses. The ESD protection circuit can inlcude ESD diodes (D1-D7) being added onbit supply lines and control lines of the attenuator (100) to prevent the attenuator (100) from electro static discharge as shown in FIG. 4.The ESD protection circuit (400) includes a plurality of forward biased diodes (D1-D5), and a plurality of reveres biased diodes (D6-D7) configured with the bit control lines of the attenuator (100). The plurality of forward biased diodes (D1-D5)can include a set of five series connected diodes connected between the bit control lines and a ground, and the plurality of reverse biased diodes (D6-D7) can include a set of two series connected diodes connected to between the bit control lines and the ground.
[0070] Existing digital attenuatorsin the art requires lengthy transmission lines and does not disclose regarding high return loss and IIP3. In addition, switching transistor i.e. turn –on or turn-off results in phase difference. Most importantly, low phase is achieved by the digital attenuatorsby using multiple distributed transmission lines between the stages.
[0071] In order to overcome the above technical problem, the present invention provides a novel design approach to avoids conventional digital attenuators,by using a better IIP3, low insertion phase shift, well matched S-band 7 bit GaAs MMIC digital attenuator.
[0072] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGS OF THE INVENTION
[0073] The proposed invention provides inductive matching of individual bits using transmission line to get better return loss. Further, lengthy transmission line are avoided as a part of layout optimization.
[0074] The proposed invention obtains improved return loss.
[0075] The proposed invention achieves a better IIP3 requirement by using bigger device peripheries in attenuation bits.
[0076] The proposed invention handles RF to digital circuit leakage for faster switching and without compromising on insertion loss.
[0077] The proposed invention avoids RF signal coupling to DC lines.
[0078] The proposed invention achieves better return loss with a resistive matching network without sacrificing heavily on insertion loss. Resistor matching circuit is added near RF port, to improve return loss.
[0079] The proposed invention avoids the risk of damage caused due to Electro Static Discharge (ESD) by using ESD protection circuit on control lines and supply lines.