BIASED SENSING MODULE Field of the Invention
The present invention relates to sensing schemes for non-differential signals and more specifically to a biased sensing scheme for enhancing matching characteristics with an improved response time.
Background of the Invention
A differential amplifier circuit is used to compare two signals for detecting a differential signal or to offset the noise of two simultaneously input signals, and is a basic circuit essentially used in most of the electronic circuits. A balanced differential amplifier employs a need based strategy of matching the two limbs of the differential pair (need is to have minimum offset). In the case of balanced differential amplifier, any noise that is generated due to high capacitances is cancelled out. In conventional unbalanced difference amplifiers one of the differential input nodes is connected to a reference node and the other is connected to a stimulus. The reference is not in synchronization with the actual charge feeding or sinking of the limb connected to the stimulus. This creates additional offset over and above the offset introduced by asymmetric devices. Thus, a conventional unbalanced amplifier is highly susceptible to failures due to mismatches between the differential limbs feeding it.
FIGURE 1 illustrates a circuit diagram 100 of a conventional biasing circuit. The circuit 100 includes a core block 102, pre-charge modules, such as 104A, 104B and 104C, a multiplexer module 106, a latch circuit 108, two PMOS pass transistors 110 and 112 connected to the latch nodes SAT and SAF. In an embodiment the core block 102 can be a HAND block, where input non differential stimuli are allowed to enter a limb. The pre-charge modules 104A, 104B and 104C consist of PMOS transistors. The latch circuit 108 consists of two PMOS transistors 114 and 116 and two NMOS transistors 118 and 120.
The transistors 114 and 118 and the transistors 116 and 120 are individually connected to form two inverters. The two invertors are cross coupled to form the latch circuit 108. A pull down transistor 122 is connected to the latch circuit 108. A drain terminal of the pull down transistor 122 is coupled to the source terminals of the NMOS transistors 118 and 120 and the source terminal is coupled to a ground terminal. The gate terminal is controlled by a control signal SON A source terminal of the PMOS pass transistor 110 is connected to a node NET A, a drain terminal is connected to a latch output node SAT and the gate terminal is controlled by the control signal SON. A source terminal of the PMOS pass transistor 112 is connected to a node NET B, a drain terminal is connected to a latch output node SAF and the gate terminal is controlled by the control signal SON.
Non differential input stimuli can enter the limb only, when a clock signal CK is enabled. The non differential input stimuli is multiplexed and is passed on to the latch output node SAT through the PMOS transistor 110. A reference signal is given to the latch output node SAF through the PMOS transistor 112. The non differential stimuli are read in three phases. First, the limbs, the reference line and latch output nodes SAT and SAF are pre-charged before any read or resolving cycle. Second, when the control signal CK is enabled all the pre-charge circuits are turned off, as their input goes high. However, the reference pre-charge will not be turned off It is permanently in an on state. One of multiplexer pass transistors is turned on (i.e., its input turns low) depending on the multiplexer address and the input stimuli gets connected to the latch output node SAT or SAF. A control signal SON is turned high and the pull down transistor is turned on and latch output nodes are decoupled from the external stimuli. The sense amplifier immediately resolves the initial difference created between SAT and SAF.
However, due to the inherent mismatch in the devices connected to the differential limbs, the conventional method presents several problems at different stages of manufacturing as well as in the circuitry or architecture, where the non differential amplifier is employed. It suffers from active and poly masking problems like, ST1 (Shallow Trench Isolation) matching, mask misalignment, doping gradient and poly shadowing It suffers from device level problems like, large figure size, gate/drain/metal capacitance
mismatches and physical effects , like, individual signal and supply cap differences, charge feed through internal node capacitance and pass transistor shared node capacitance differences between the differential nodes.
Therefore, there is a need for a novel sensing scheme for a low swing non differential stimulus with a low input referred offset, so that the robustness of the whole system is improved.
Summary of the Invention
It is an object of the present invention to provide a biased sensing circuit for sensing non differential signals with enhanced matching characteristics.
It is another object of the present invention to provide a biased sensing circuit with an improved response time.
To achieve the aforementioned objectives, the present invention provides a biased sensing circuit for sensing non differential signals comprising:
a first pre-charge module operatively coupled to a first core block for charging,
a first multiplexer module operatively coupled between the first pre-charge module and a first pass transistor;
a second pre-charge module operatively coupled to a second core block for charging;
a second multiplexer module operatively coupled between the second pre-charge module and a second pass transistor;
a sense amplifier circuit operatively coupled between the first multiplexer module and the second multiplexer module for receiving differential inputs through the first pass transistor and the second pass transistor to provide an output;
a third pre-charge module operatively coupled to said differential inputs of the sense amplifier circuit; and
an output module operatively coupled to said sense amplifier for providing an output signal.
Further the present invention provides a sense amplifier circuit comprising:
a latch circuit having a first inverter circuit cross coupled to a second inverter circuit,
a first pull down transistor operatively coupled to said latch circuit for receiving a first control signal;
a first pass transistor operatively coupled to said first inverter circuit;
a second pass transistor operatively coupled to said second inverter circuit; and
a second pull down transistor operatively coupled to said first pass transistor and said second pass transistor for receiving a second control signal
Further the present invention provides a read only memory (ROM) comprising: a plurality of memory blocks for storing data bits; and
a biased sensing circuit coupled to the plurality of memory blocks for providing enhanced matching characteristics, said biased sensing circuit comprising:
a first pre-charge module operatively coupled to a first core block for charging;
a first multiplexer module operatively coupled between the first pre-charge module and a first pass transistor;
a second pre-charge module operatively coupled to a second core block for charging;
a second multiplexer module operatively coupled between the second pre-charge module and a second pass transistor;
a sense amplifier circuit operatively coupled between the first multiplexer module and the second multiplexer module for receiving differential inputs through the first pass transistor and the second pass transistor to provide an output;
a third pre-charge module operatively coupled to said differential inputs of the sense amplifier circuit; and
an output module operatively coupled to said sense amplifier for providing an output signal
The present invention further provides a method of sensing non differential signals through a biased sensing circuit comprising:
precharging input nodes, output nodes and sensing limbs of the biased sensing circuit;
selecting one of a first core block and a second core block through a selection line;
applying a clock signal to turn off pre-charge modules to conduct through a selected multiplexer module for allowing an input stimuli to enter into one of the first core block and the second core block;
inverting the input stimuli, when the input stimuli enters in the second core block; and
multiplexing the output lines with a select signal, when the input stimuli not enters in the second core block.
Brief Description of Drawings
FIGURE 1 illustrates a circuit diagram of a conventional biased sensing scheme.
FIGURE 2 illustrates a circuit diagram of a biased sensing scheme according to the present invention.
FIGURE 3 illustrates a circuit diagram of a sense amplifier according to the present invention.
FIGURE 4 illustrates a flow diagram of a method for sensing non-differential signals for providing minimum mismatching according to the present invention.
Detailed Description of the Invention
The preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the preferred embodiments. The present invention can be modified in various forms. The preferred embodiments of the present invention are only provided to explain more clearly the present invention to the ordinarily skilled in the art of the present invention. In the accompanying drawings, like reference numerals are used to indicate like components
The present invention provides a biased sensing module for minimizing the mismatch with an enhanced response time.
FIGURE 2 illustrates a circuit diagram 200 of a biased sensing circuit according to the present invention. The circuit 200 includes a first core block 202A, a second core block 202B, a first pre-charge module 204A, a second pre-charge module 204B, a third pre-charge module 204C, a first multiplexer module 206A, a second multiplexer module 206B, a sense amplifier circuit 208, a first PMOS transistor 210, a second PMOS transistor 212 and an output module 214.
The first core block 202A and the second core block 202B are NAND blocks, where input non differential stimuli are allowed to enter. The first core block 202A is connected to the pre-charge module 204A. The first pre-charge module 204A is connected to the first multiplexer module 206A. The first multiplexer module 206A is connected to the first PMOS transistor 210 through a node NET A. The second core block 202B is connected to the second pre-charge module 204B. The second pre-charge module 204B is connected to the second multiplexer module 206B. The second multiplexer module 206B is connected to the second PMOS transistor 212 through a node NET B. The third pre-charge module 204C is connected to sensing limbs SAT and SAP of the sense amplifier circuit 208.
The third pre-charge module 204C comprises three PMOS transistors 216, 218 and 220. A source terminal of the PMOS transistor 216 is connected to a voltage source, a drain terminal is connected to the sensing limb SAT of the sense amplifier circuit 208 and a gate terminal is connected to a node Nl. A source terminal of the PMOS transistor 218 is connected to the voltage source, a drain terminal is connected to the sensing limb SAF of the sense amplifier circuit 208 and a gate terminal is connected to the gate terminal of the PMOS transistor 216 through the node Nl. A source terminal of the PMOS transistor 220 is connected to the drain terminal of the PMOS transistor 218, a drain terminal is connected to the drain terminal of the PMOS transistor 216 and a gate terminal is connected to the gate of the PMOS transistor 216 and the PMOS transistor 218 through the node Nl.
The output module 214 comprises multiplexed output lines An output from the true sensing limb (SAT) of the sense amplifier circuit 208 is given to one output line Two NOT gates are connected to the output line. An output from the false sensing limb (SAF) of the sense amplifier circuit 208 is given to another output line. The two output lines are multiplexed using a PMOS transistor 218 and an NMOS transistor 216 to provide an output.
The non differential multiplexed stimuli have been split into a first core block 202A and a second core block 202B. Before the start of the cycle all nodes SAT, SAF, NET A, NETB and all input lines are pre-charged. Before the arrival of a clock signal CK, selection of the core block is made by select lines, which also change the bias (on which side, i.e., SAT or SAF, the weaker pull down is to be connected in the sense amplifier circuit 208).
At the arrival of clock signal CK, all pre-charge modules are turned off and selected multiplexer pass transistor is turned on irrespective of their connection to the SAT or SAF limb. This is done in order to ensure similar (miller or parasitic) charge feeding or sinking at the differential nodes, both before and after sense pass transistors 210 and 212. Any kind of input referred offset from the input limbs has now been nullified.
FIGURE 3 illustrates a circuit diagram of a sense amplifier circuit 208. The circuit 208 consists of two PMOS transistors 302 and 304 and two NMOS transistors 306 and 308. The NMOS transistor 306 is a weak transistor compared to the NMOS transistor 308.The transistors 302 and 306 and the transistors 304 and 308 are individually connected to form two inverters. The two inverters are cross coupled to form a latch circuit. A pull down transistor 310 is connected to the latch. A drain terminal of the pull down transistor 310 is connected to the source terminals of the NMOS transistors 306 and 308 and the source terminal is connected to a ground voltage level. The gate terminal is controlled by a control signal SON1. Two NMOS transistors 312 and 314 are connected to the latch circuit. A drain terminal of the NMOS transistor 312 is connected to a latch, output node N2 and the source terminal is connected to a drain terminal of a pull down transistor 316. A gate terminal of the transistor 312 is connected to the gate terminals of the transistors 302 and 306. The gate terminal of the transistor 312 is also connected, to the drain terminal of the PMOS transistor 304 and to the drain terminal of the NMOS transistor 308. A drain terminal of the NMOS transistor 314 is connected to a latch output node N3 and the source terminal is connected to a drain terminal of a pull down transistor 316. A gate terminal of the transistor 314 is connected to the gate terminals of the transistors 304 and 308. The gate terminal of the transistor 314 is also connected to the drain terminal of the PMOS transistor 302 and to the drain terminal of the NMOS transistor 306. The transistor 312 is a strong transistor as compared to the transistor 314. A source terminal of the pull down transistor 316 is connected to the ground voltage level and a gate terminal is controlled by a control signal SON2.
The two control signals SON1 and SON2, depending on which multiplexer bunch is to be selected, are used to select the bias created by the weak transistor 306 or 314 on one side and the strong transistor 308 or 312 at the other. If a control signal Selectl is applied, the first core block 202A will be selected and the control signal SON1 will be enabled and the stimulus at the SAT limb will be resolved. If a control signal Select2 is applied, the second core block 202B will be selected and the control signal SON2 will be
enabled and the stimulus at the SAP limb will be resolved. The sense is perfectly balanced in terms of the load and capacitive coupling at the two differential limbs.
If an input from an upper or lower bunch is to be read (depends on select signal Select 1 or Select!). After the differential voltage development phase, control signals Sonl or Son2 goes high, so that the side being read is pulled down slower as compared to the other side .The voltage difference for a read -0 (bit line discharge) has to be sufficient enough to offset this difference in transistor strengths for correct read-0 operation (read-1 operation is anyhow favored by the bias).
No differentiation is done at the multiplexer pass transistor level on whether a stimulus From limb connected to SAT or SAP is to be resolved, but the differentiation is shifted to two different levels. First, inside the sense amplifier circuit 208, where the select signal decides whether a stimulus at the SAT limb has to be resolved or a stimulus at the SAP limb has to be resolved. Second, at the core block level, where select signal is mixed with the clock signal CK, which decides whether the stimulus from the limb connected to SAT or SAP should be allowed to enter.
The input stimuli on the second core block 202B are inverted. This has to be done if if an input from the lower half is to be resolved, a low swing on that input should suing the sense in the same direction as that if a low swing on an input from upper half is to be resolved.
The above method may not be possible in some applications. Then the other viable solution is to multiplex the output lines with the select signal through the output module 214.
FIGURE 4 illustrates a flow diagram of a method for sensing non-differential signals with minimized mismatch according to the present invention. At step 402, input nodes, output nodes and sensing limbs of the biased sensing circuit are pre-charged. At step 404, one of a first core block and a second core block is selected through a selection line. At
step 406 a clock signal is applied to turn off pre-charge modules to conduct through a selected multiplexer module for allowing input stimuli to enter into one of the first core block and the second core block. At step 408, the input stimuli are inverted, when the input stimuli enter the second core block. At step 410, output lines are multiplexed with a select signal.
The present invention offers many advantages. First, robustness of the whole system is improved as the input referred offset is very low. Second, the speed is increased as a lower voltage difference has now to be ensured which is attributed to a lower input referred offset. The increase in speed is further attributed to a lower capacitance due to a split multiplexer circuit. Third, there is reduction in power as the input lines reduce the swing required to detect a zero. Fourth, the effort in making a layout is reduced as the structure is now fully differential. Fifth, a reduction in area as the reference limb has not been managed.
Although the disclosure of system and method has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the disclosure.

We Claim:
1. A biased sensing circuit for sensing non differential signals comprising:
a first pre-charge module operatively coupled to a first core block for charging;
a first multiplexer module operatively coupled between the first pre-charge module and a first pass transistor;
a second pre-charge module operatively coupled to a second core block for charging,
a second multiplexer module operatively coupled between the second pre-charge module and a second pass transistor,
a sense amplifier circuit operatively coupled between the first multiplexer module and the second multiplexer module for receiving differential inputs through the first pass transistor and the second pass transistor to provide an output;
a third pre-charge module operatively coupled to said differential inputs of the sense amplifier circuit; and
an output module operatively coupled to said sense amplifier for providing an output signal.
2 The circuit of claim 1, wherein said first pre-charge module comprises one or more PMOS transistors.
3. The circuit of claim 1, wherein said second pre-charge module comprises one or
more PMOS transistors.
4. The circuit of claim 1, wherein said first pass transistor comprises a PMOS
transistor.
5. The circuit of claim 1, wherein said second pass transistor comprises a PMOS
transistor.
6. The circuit of claim 1, wherein said third pre-charge module comprises:
a third pass transistor having a source terminal connected to a voltage source, a drain terminal connected to a first differential input of the sense amplifier and a gate terminal connected to a node;
a fourth pass transistor having a source terminal connected to said voltage source, a drain terminal connected to a second differential input of the sense amplifier and a gate terminal connected to the gate terminal of the third pass transistor through the node; and
a fifth pass transistor having a source terminal connected to the drain terminal of the fourth pass transistor, a drain terminal connected to the drain terminal of the third transistor and a gate terminal connected to the gate of the third pass transistor and the fourth pass transistor through said node.
7. The circuit of claim 1, wherein said third pass transistor comprises a PMOS
transistor.
8. The circuit of claim 1, wherein said fourth pass transistor comprises a PMOS
transistor.
9. The circuit of claim 1, wherein said fifth pass transistor comprises a PMOS
transistor.
10. A sense amplifier circuit comprising:
a latch circuit having a first inverter circuit cross coupled to a second inverter circuit;
a first pull down transistor operatively coupled to said latch circuit for receiving a first control signal;
a first pass transistor operatively coupled to said first inverter circuit;
a second pass transistor operatively coupled to said second inverter circuit; and
a second pull down transistor operatively coupled to said first pass transistor and said second pass transistor for receiving a second control signal.
11. The circuit of claim 10, wherein said first pull down circuit comprises an NMOS
transistor.
12. The circuit of claim 10, wherein said second pull down circuit comprises an
NMOS transistor.
13. The circuit of claim 10, wherein said first pass transistor comprises an NMOS
transistor.
14. The circuit of claim 10, wherein said second pass transistor comprises an NMOS
transistor.
15. A read only memory (ROM) comprising:
a plurality of memory blocks for storing data bits; and
a biased sensing circuit coupled to the plurality of memory blocks for providing enhanced matching characteristics, said biased sensing circuit comprising:
a first pre-charge module operatively coupled to a first core block for charging;
a first multiplexer module operatively coupled between the first pre-charge module and a first pass transistor,
a second pre-charge module operatively coupled to a second core block for charging;
a second multiplexer module operatively coupled between the second pre-charge module and a second pass transistor,
a sense amplifier circuit operatively coupled between the first multiplexer module and the second multiplexer module for receiving differential inputs through the first pass transistor and the second pass transistor to provide an output;
a third pre-charge module operatively coupled to said differential inputs of the sense amplifier circuit; and
an output module operatively coupled to said sense amplifier for providing an output signal.
16. A method of sensing non differential signals through a biased sensing circuit comprising:
precharging input nodes, output nodes and sensing limbs of the biased sensing circuit,
selecting one of a first core block and a second core block through a selection line;
applying a clock signal to turn off pre-charge modules to conduct through a selected multiplexer module for allowing an input stimuli to enter into one of the first core block and the second core block;
inverting the input stimuli, when the input stimuli enters in the second core block; and
multiplexing the output lines with a select signal, when the input stimuli not enters in the second core block.
17. A biased sensing circuit for sensing non-differential signals substantially as herein
described with reference to and as illustrated in the accompanying drawings.
18. A sense amplifier circuit substantially as herein described with reference to and as
illustrated in the accompanying drawings.
19. A read only memory (ROM) substantially as herein described with reference to
and as illustrated in the accompanying drawings.
20. A method of sensing non-differential signals through a biased sensing circuit substantially as herein described with reference to and as illustrated in the accompanying drawings.