Field of the invention
The invention relates to the field of telecommunications, in particular to a bit-interleaver and a
method of bit-interleaving for an optical line terminal of an optical access network.
Background
Optical access networks are these days a prominent solution, for transmitting data from an
optical line terminal to multiple optical network units. The optical line terminal is located at a
central office, wherein the optical line terminal acts as an interface between the optical access
network and a core network for data transmission. The optical line terminal receives data from
the core network and transmits this in downstream direction towards the optical network units
(ONU), to which customers may connect their equipment for data transmission. The
downstream signal generated by the optical line terminal is transmitted into an optical feeder
fiber, to which a remote node is connected. This remote node splits the downstream signal
onto different optical branches, to which the different optical network units are connected.
One solution for transmitting different data streams assigned to different optical network units
is, to allocate within the downstream signal for each optical network unit one or more time
slots, within which multiple data bits of the data stream assigned to the respective optical
network unit are placed by the optical line terminal. In such a solution, the respective optical
network unit needs to receive within such a time slot data at a certain data rate, while during
other time slots, assigned to other optical network units, the respective optical network unit
does not need to receive data at any data rate. This implies, that the optical network unit has
to be able to receive data within the designated time slot at a data rate, which is higher than
the overall average data rate, by which the assigned data stream is transmitted from the
optical line terminal to the respective optical network unit.
An alternative solution, within which an optical network unit may receive data from an optical
line terminal at a constant data rate, is provided by a bit-interleaving protocol of a so-called
bit-interleaving passive optical network (BIPON). In such a BIPON, the bit data of different
data streams assigned to different ONUs are interleaved within a global frame, such that the
resulting data rate of each data stream for each ONU has a respective constant value. A
global frame may contain for example up to 8*1 9,200 Bytes = 153,600 Bytes, which is equal
to 1,228,800 Bits. The bits of one specific data stream are placed within the global frame
equidistantly to each other, which leads to a resulting constant data rate for this data stream.
A global frame is then followed by further successive global frames for an ongoing data
transmission.
The data rate for a specific data stream is defined by the number of bit positions, by which the
bits of this data stream are spaced, assuming a given time duration of the global frame. By
placing the bits of different data streams with different respective equidistant spacing within
the global frame, different data rates are realized. The advantage of a BIPON is, that an ONU
needs to receive data not at the overall data rate provided by the global frame, but at a lower
data rate, which is defined by the time duration of the global frame and the rate, at which the
bits of this specific data stream of this ONU are placed inside the global frame. This allows for
operation of an ONU at a lower data rate than the maximum data rate realized by the
successive global frames of a BIPON.
Even furthermore, by changing the rate at which data bits of a specific data stream are placed
inside the global frame, a changed data rate is thus realized for the associated optical network
unit.
Within a BIPON, an optical line terminal thus has to perform reception of different data
streams assigned to different optical network units, and also has to perform a proper bitinterleaving
of the bits of the different data streams into successive global frames, such that
different pre-determined data rates are realized for the respective different optical network
units.
Summary
It is an objective of the invention to improve the known methods for bit-interleaving of different
data streams at an optical line terminal.
Proposed is a bit-interleaver for an optical line terminal of an optical access network. The
optical access network is preferably a passive optical network of the type BIPON.
The proposed bit-interleaver contains different sub-devices.
The bit-interleaver contains a memory reader, that is able to receive a number of M data
streams assigned to respective optical network units. The memory reader provides these data
streams at bit level to a space-time switch, which is a further sub-device of the bit-interleaver.
The space-time switch is able to read within one input cycle up to N respective bit sets from the
respective M data streams.
Furthermore, the space-time switch is able to switch within one writing cycle up to N bits of the
data streams onto up to N respective output ports. The respective output ports provide
respective output vectors. The space-time switch performs switching of the respective bit sets at
bit level.
The bit-interleaver contains furthermore N OR-function elements, that are able to determine
within the writing cycle respective single output bits based on the respective output vectors.
Thus, an OR-function element determines from one output vector the resulting single output
bit, by combining the different bits of one output vector by a boolean OR-function.
The bit-interleaver contains furthermore N memory elements, which in turn contain each at
least L bit sub-elements, wherein these bit sub-elements have respective sub-element
addresses. The N memory elements are each operable to write within the one writing cycle a
respective one of the respective single output bits into a respective one of their bit subelements.
The bit-interleaver contains furthermore a control unit that is able to control the reading of the
M data streams by the space-time switch. Furthermore, the control unit is able to control the
switching of the bits by the space-time switch onto the output ports of the space-time switch.
Even furthermore, the control unit is able to control a choice of the writing addresses. The
writing addresses are those addresses, at which the resulting single output bits are written into
the respective bit sub-elements.
In order to grasp the advantages of the proposed bit-interleaver, the following aspects have to
be taken into consideration.
When having to interleave bits of different data streams at an optical line terminal into a
global frame of a bit-interleaving protocol, a simple solution would be, to write the different
bits of the different data streams into one large memory according to the desired bitinterleaving
pattern. Next, all the different bits of the global frame would be read out from the
one large memory, after having written all the bits into the global memory. The result of this
would be, that the first bit of the global frame could not read out from this large memory
before the last bit has been written into this memory. Thus, all the data streams written into the
single large memory holding the total global frame would experience a latency, that is equal
to the time duration of the global frame.
The proposed bit interleaver has the advantage, that less than B data bits of the different M
data streams can be written into the N memory elements and then be read out, after these bits
have been written into these N memory elements. The number N of the memory elements is
smaller than the maximum number B of bits present within a global frame. For example,
within one writing cycle, N bits may be written into respective ones of the N memory elements,
while after the completion of this writing cycle these N bits may be read out within a reading
cycle, which may start just after the writing cycle has finished.
As previously mentioned, the number N of the memory elements is smaller than the maximum
number B of bits present within a global frame. By reading out sets of N bits from the N
memory elements at successive reading cycles, the resulting sets of N bits of the different
reading cycles can be concatenated as a bit stream that forms the bit stream of the global
frame. Thus, writing and reading of N interleaved bits using the N memory elements can be
performed for the purpose of data transmission even before all B bits of the global frame have
been written into the memory elements. This reduces the latency of the bit interleaver to a
great extent in comparison to the previously described simple method using only one single
memory device.
Even furthermore, since the control unit controls the reading of the different data streams by
the space-time switch, the switching by the space-time switch and also the choice of the writing
addresses used for writing resulting single bits into the bit sub-elements of the memory
element, the control unit is able to easily change the different data rates for the different data
streams, which in turn achieves a great flexibility.
To summarize the above, the proposed bit-interleaver realizes high-speed bit-interleaving with
low latency and great flexibility. Even furthermore, due to the fact, that only N memory
elements have to be used, the power consumption is reduced in comparison to the proposed
simple method of using one large memory for holding all the B bits of a global frame within
this one large memory.
Brief description of the Figures
Figures l a, b and c show a bit-interleaving principle for different data streams at same data
rates.
Figures 2a, b and c show a bit-interleaving principle for different data streams at different
data rates.
Figures 3a, b and c show resulting output vectors with different memory states for different
memory elements at different time instances for the bit-interleaving method realizing same
data rates for the different data streams.
Figures 4 a, b and c show different resulting output vectors together with different states of
different memory elements at different time instances for the bit-interleaving method realizing
different data rates for the different data streams.
Figures 5 and 6 show resulting data streams obtained by reading sets of bits from the memory
elements.
Figure 7 shows a proposed bit interleaver according to a preferred embodiment.
Description of embodiments
Figure 7 shows a proposed bit-interleaver Bl.
The bit interleaver Bl contains a FIFO-reader FR, which receives M different data streams OD1 ,
... OD4. The FIFO-reader is one example of a memory reader that can be used for receiving
and reading the different data streams OD1 , ... OD4. Alternative types of memory readers
may be used instead.
In this example, the number M of the data streams is chosen to M=4 without any limitation.
The FIFO-reader FR provides the different data streams OD1 ,OD4, to a space-time switch
STS. The different data streams OD1 , OD4 are data streams assigned to respective optical
network units.
The space-time switch STS receives within a reading cycle up to M respective bit sets BS1 , ...
BS4, which are extracted from the respective data streams OD1 ,..., OD4. Each of the bit sets
BS1 , ... BS4 contains K bits. In this example, the number K of the bits within a bit set is chosen
to K=8 without any limitation.
The space-time switch STS may receive within one reading cycle a set of K= 8 bits from each of
the data streams OD1 , ... OD4. In this case, the data rate, at which the different data streams
OD1 OD4 are read, is the same for all data streams. For realizing different data rates for
the different data streams OD1 , OD4, the space-time switch STS may read within different
successive reading cycles different numbers of bit sets from the different data streams OD1 ,
OD4. For example, within a first reading cycle, the space-time switch STS may read from
each of the data streams OD1 , ... OD4 respective bit sets BSl , BS4, while in the next
following reading cycle the space-time switch STS reads respective bit sets BSl , BS2 only from
the data streams OD1 , OD2. The result of such reading of bit sets within different reading
cycles by the space-time switch is, that the data streams OD1 , OD2 experience a reading at a
data rate, that is twice the data rate, at which the data streams OD3, OD4 are being read.
The space-time switch STS switches within one writing cycle up to N bits onto up to N output
ports of the switch STS. At each of the N output ports, a respective output vector vO, v(N-l )
is provided. In which way the switch STS switches the bits of the data streams into the output
vectors vO,..., v(N-l ) will be described in detail later on.
A control unit CU is connected to the switch STS and the reader FR. Thus, the control unit CU
controls the reading of the data streams from the reader FR by the space-time switch STS.
Furthermore, the control unit CU controls, in which way the switch STS switches the read bits
onto the output ports and thus into the respective output vectors vO,..., v(N-l ).
The resulting output vectors vO,..., v(N-l ) are then provided to respective OR-function
elements O0, 0(N-1 ) . The output vectors vO,..., v(N-l ) are of a bit length of J= 3. The bit
length of the output vectors is chosen in this example to J= 3 without any limitation.
The OR-function element O 0 determines within one writing cycle a single output bit bO based
on the output vector vO. For this, the OR-function element 0 0 combines all bits present within
the vector vO by a boolean OR-function. The respective further OR-function elements O l ,
0(N-1 ) determine from the respective vectors v l v(N-l ) respective single output bits b l ,
b(N-l ) .
The control unit CU controls the reading addresses used for reading up to N bits from the
respective N memory elements within one reading cycle.
The reason, why such a reduction of the output vectors vO,..., v(N-l ) to the output bits bO,
b(N-l ) is necessary, is that within one writing cycle, each of the vectors vO, v(N-l ) contains
only one bit that is switched by the switch STS. The reason for this in turn is, that using a
space-time switch STS for switching the bits of the bit streams onto output vectors at the
different output ports is a prominent solution, but due to internal scheduling properties of such
a switch STS, it cannot be guaranteed that at each instance of a writing cycle one of the bits of
the data streams can be switched into exactly the first bit position of a n output vector vO,
v(N-l ) . In the case, that not all bits of a bit set BSl , BS4 are switched onto respective
output ports of the switch STS within a same writing cycle, one or more bits of such a bit
sequence BS1 , BS4 has to be delayed internally by the space-time switch STS, which in turn
causes such a delayed bit to be placed inside one of the output vectors v0,..., v(N-l ) at a bit
position that is different from the first bits position of the output vector. However, using a
space-time switch with output vectors v0,..., v(N-l ) for the bit-interleaver Bl is a favorable
solution, since such a switch STS is a prominent device for switching bits from different input
ports to different output ports. The resulting shift of a switched bit to a resulting bit-position
within an output vector is compensated for by the OR-function elements OO, O(N-l ) .
The determined single output bits bO, b(N-l ) are then provided to respective memory
elements MO, M(N-1 ) . Each of the N memory elements MO, M(N-1 ) comprises at least
L bit sub-elements with respective addresses. Within one writing cycle, a memory element MO,
M(N-1 ) writes a respective single output bit bO, b(N-l ) into one of its sub-elements at
bit level. The choice of the writing address, which determines to which bit sub-element a
memory element MO, M(N-l ) writes the respective received output bit bO, b(N-l ), is
chosen by the control unit CU. This choice of the writing address in detail will be described
later on.
The proposed bit-interleaver Bl is able to provide within one writing cycle up to N output bits at
the respective memory elements MO, M(N-l ), from which these output bits can be read out
as a whole within one reading cycle. Thus, after having written within one writing cycle up to N
bits into the memory elements MO, M(N-1 ), these N bits can then be read out within a
reading cycle just after the N-th bit has been written into one of the memory elements MO,
M(N-l ) . The bit-interleaver Bl does not have to perform writing of all B bits of a global frame
into a large memory, before extracting the whole global frame.
The bit-interleaver Bl may process writing of up to N bits each within successive writing cycles
into the memory elements and may then read out successive sets of N bits in following reading
cycles for forming successive bits of a corresponding global frame. Thus, the proposed bitinterleaver
Bl achieves a reduced latency in comparison to the solution when writing all bits of
a global bit-interleaving frame into a whole memory and then reading out the whole global
frame after having written all bits into the single large memory.
Even furthermore, since the rates, at which the switch STS reads the bit-sets BS1 BS4 of the
data streams OD1 , OD4, is controlled by the control unit CU, and since furthermore the
switching properties of the switch STS as well as the reading and the writing addresses of the
memory elements MO, M(N-1 ) are controlled by the control unit CU, the proposed bitinterleaver
is a solution of great flexibility, allowing the control unit CU to achieve different
data rates for the different data streams OD1 , OD4 with a low latency at high speed bitinterleaving.
Even furthermore, since only N memory elements MO, M(N-l ) are used, the
power consumption imposed by the proposed bit-interleaver Bl is smaller than a solution, in
which a whole global frame of B bits has to be written into a memory holding these B bits.
Preferably, the control unit CU is provided with pre-determined data rates R(i), wherein the
index i of a data stream in this example ranges from i= l , M=4. The control unit CU uses
these pre-determined data rates R(i), for controlling the reading of the bits sets BS1 ,..., BS4 by
the space switch STS from the FIFO reader FR. Furthermore, the control unit CU is provided
with pre-determined offset values o(i), with index i, which define an offset of the different bits
of the different data streams OD1 , OD4 within a global frame. The function of these
offsets will be described in detail later on.
Even furthermore, the control unit CU is provided with a pre-determined value B of bits
present within a global frame and also the number N of the memory elements, as well as the
number L of the bit sub-elements of a memory. Thus, the control unit CU chooses the output
port and the writing addresses in dependence on pre-defined data-rates, pre-defined offset
values, a maximum number B of bits present within a frame, the number N of memory
elements and the number L of bit sub-elements.
Figure 1a shows different bit streams OD1 , OD4 together with the bits A l , A8, Bl ,
B8, CI , C8, Dl , D8 as sequences over time t .
Figure 1b shows a bit-interleaving pattern of a global frame GF, in which the different bits of
the data streams from the Figure l a are interleaved. Figure 1b shows the interleaving of the
different bits of the data streams for the case, that the data rates R(l ), R(2), R(3), R(4) are all
equal to 1/8 for all the data streams. In other words, all data streams have same rates R(l ),
R(4). The maximum number B of bits present within the global frame GF may be for
example 1,228,800 bits. Such a global frame may have a time duration of 122 microseconds.
The first bit of the data stream OD1 , which is the bit A l , is placed at the bit position 0 of the
global frame GF. Due to the fact, that the rate R(l ) chosen for the bit stream OD1 is 1/8, the
next bit A2 of the data stream OD1 is placed 8 further bits apart from the first bit A l , such that
the bit A2 is placed in the bit position 8. Further bits A3, A4, A5 of the data stream OD1
follow at next bit positions 16, 24, 32 within the global frame GF.
For the shown BIPON bit-interleaving scheme placing bits within a global frame, the bit
position bp(x(i),i) of the x-th bit of the data stream with index i can be in general determined,
by using the reciprocal value r(i) = l/R(i) of the rate R(i), an offset value o(i) and an integer
value x(i). The integer value x(i) corresponds to the index number of the x-th bit and is thus an
integer number ranging from x(i)=0 up to the integer value x(i) = in†(B/r(i)). Thus, the bit
position bp(x(i),i) of the x-th bit of the data stream with index i can be determined for decimal
numbers as
bp(x(i),i) =o(i) + r(i)*x(i) .
Thus, the control unit CU determines for the x-th bit of the i-th data stream a corresponding
bit-position within the global frame as described above in detail.
In this example, the offset value o(l ) is chosen to o(l )=0 for the data stream OD1 .
In Figure l b, it is also shown the relationship of the bits Dl , D2, ... of the data stream OD4
within the global frame GF. Due to the fact, that the rate R(4) is also chosen as R(4) = l/8 for
this bit-interleaving scheme, also the bits Dl , D2, ... of the data stream OD4 are each spaced
8 bit positions apart within the global frame GF. The offset value o(4) is chosen as the value
0 4 = 3 in this example. The offset values for the bits of the data streams OD2, OD3 are not
explicitly shown in the Figure 1b, but it can be said, that the offset value o(2) is chosen to the
value o(2) = l , while the offset value o(3) is chosen to the value o(3) = 2.
Looking at Figure 1b, it becomes clear, that optical network units receiving this global frame
GF may perform reception of bits of one of the data streams at a data rate, which is equal to
data rate of the global frame GF divided by 8.
Figure l c shows an alternative bit pattern ABP, in which the different bits of the global frame
shown in Figure 1b are split into sets of N bits. Over time, different sets of N bits may be read
out from the memory devices MO, M(N-1 ) shown in Figure 7, and later on be successfully
transmitted for realizing a transmission of a bit sequence corresponding to the global frame
GF shown in Figure 1b.
The first set, which has to be read in a first reading cycle from the memories MO, M(N-l )
shown in Figure 7, is the set SI . The bits of this set SI correspond to those bits, which are
stored within the bit positions 0 to 15 of the global frame GF of Figure 1b.
Within a next reading cycle, the next set of bits S2, shown in the Figure l c, shall be read out
from the memory elements MO, M(N-1 ) shown in Figure 7. These are the bits allocated to
the bit positions 16 to 3 1 of the global frame GF shown in Figure 1b.
Within a third reading cycle, the set of bits S3, shown in Figure l c, shall be read out from the
memory elements MO, M(N-1 ) shown in Figure 7. These are the further bits starting at the
bit positions 32 of the global frame GF shown in Figure 1b.
It will be now explained in detail, in which way different bits of different data streams are to be
switched by the switch STS and written to the memories MO, M(N-l ), shown in Figure 7,
and furthermore also read from these memories.
It shall be assumed, that the switch STS reads within one input cycle bit sets BS1 , BS4 of
K=8 bits each from the fiber reader FR. Within a writing cycle, the space time switch STS
switches the first and the second bit of the bit sets BS1 , BS4 onto respective output ports
and thus into the respective vectors vO, v l 5, as shown in Figure 3a. Due to internal
scheduling properties of the switch STS, the switched bits are present within first bit positions,
with the index 0, within the output vectors vO, v l 5 . As an example, the bit length of the
output vectors vO, v l 5 is chosen to J= 3 as a non-limiting example.
The number of the output port and thus also the number of the corresponding output vector,
to which the switch STS switches at specific bit, is controlled by the control unit CU. The control
unit CU determines the number of the output port, and thus the number of the output vector
and also the resulting number of the memory M0, M(N-1 ), to which a bit is switched, as
the port number pn(x(i),i) = bp(x(i),i) mod N for decimal numbers. For each bit, the bit
position bp may be determined by the control unit CU as previously described above.
Figure 3a shows furthermore the different states of the different memory elements M0,
M l 5 at a time instance t=0. The different OR-function elements reduce the different output
vectors vO, v l 5 to single output bits bO, b(N-l ), which are then written into respective
bit-sub-elements of respective memories M0, M(N-l ), wherein these bit-sub-elements are
of a same writing address. In this example, the writing address is equal to 0 . The control unit
CU determines within one writing cycle for the x-th bit of the i-th data stream the writing
address wa in dependence on the bit position of the x-th bit of the i-th data stream and the
number L. In detail, the writing address wa of the x-th bit of the i-th data stream can be
determined for decimal numbers as
wa(x(i),i) =int( bp(x(i),i)/L ) .
Looking at the memory elements MO, M l 5 at the time instance t=0, an appropriate set of
N bits, shown as the bit set SI in Figure l c, can be read from the memories, by reading out all
the memories MO, M l 5 at one time instance with a same reading address. In this
example, the reading address is equal to the value 0.
This reading has not to be performed exactly at a time instance at which the bits have finally
been written into the memory elements MO, M l 5, but may be performed at a later point in
time. The reading of the bits from the memory elements MO, M l 5 with the appropriate
reading address is controlled and determined by the control unit CU shown in Figure 7.
Within a next writing cycle, the switch switches bits of the different data streams onto output
ports and into corresponding output vectors vO, v l 5 at the time instance t=l , as shown in
Figure 3b. The placement of the bits A3, D4 at a bit position 0 within the vectors vO,
v l 5 is caused by internal scheduling properties of the switch.
As previously described, the mentioned OR-function elements OO, ... , O(N-l ), shown in
Figure 7, generate single output bits, which are then written at this time instance t=l into
respective bit sub-elements of the memory elements MO, Ml 5, as shown in Figure 3b.
Within this next writing cycle, the control unit CU determines for the x-th bit of the i-th data
stream the number of the output port and thus the number of the memory element, to which
the resulting output bit is written, as the port number pn in dependence on the bit-position
bp(x(i),i). In detail, the control unit CU determines for the x-th bit of the i-th data stream the
port number pn for decimal numbers as
pn(x(i),i) =bp(x(i),i) mod N.
Furthermore, using the respective bit positions bp of the different bits A3, D4, the control
unit CU of Figure 7 determines the writing address wa for decimal numbers as
wa(x(i),i) =int( bp(x(i),i)/L ) .
By looking at Figure 3b, it becomes evident, that a next set of N = l 6 bits can be read out from
the memory elements M0, Ml 5, by reading out the 16 bits present within these memory
elements at same reading addresses, which is in this example are the reading address of the
value 1.
Thus, when having to read successive sets of N bits from the different memory elements, for
forming a bit sequence corresponding to a global frame of a BIPON scheme, one may simply
read out such N bits from the N memory elements, using a same reading address for all of
these N memory elements within a same reading cycle and then simply increasing the reading
address for the next reading cycle.
For the further bits A5, D6, the Figure 3c shows for a next time instance t=2, in which way
the proposed choice for switching these bits and writing these bits into the memories MO,
M l 5 leads to a placement of the bits within the memory elements at specific bit sub-elements.
A resulting bit sequence RBS, shown in Figure 5 , results from reading sets of N bits from the N
memory elements with a same reading address within each respective reading cycle. By
comparing the resulting bit sequence RBS of Figure 5 with the initially desired bit sequence of
the global frame GF in Figure 1b, it become clear, that the proposed bit-interleaver Bl in
Figure 7 is able to perform the desired bit-interleaving of a global frame shown in Figure 1b.
Figure 2a shows once again the different data streams ODl , OD4.
Figure 2 b shows a desired bit sequence of a global frame GF2 in the case, that the data
stream ODl shall be interleaved at a rate of 1/8 and also the data stream OD4 shall be
interleaved at a rate 1/8, while the data stream OD2 shall be interleaved at a rate of 1/1 6
and the data stream OD3 shall be interleaved at rate of 1/32.
The offset values of the different data streams are chosen as previously described with regard
to Figure 1b.
Figure 2c shows the corresponding alternative bit pattern ABP2 with sets of N = l 6 bits over
time t . The resulting sets of bits SI 1, SI 2, SI 3 are such, which shall be present within the
memory elements MO, M(N-1 ) at bit sub-elements of same addresses, as shown in Figure
7.
Figure 4 a shows the resulting placement of the different bits A l , D2 within the output
vectors vO, v l 5 , as well as the memory element MO, M l 5 .
At the next time instance t = 1, the bits of the set SI 2 shown in Figure 2c have to be placed
within the output vectors vO, v l 5 , as shown in Figure 4b.
Due to the fact, that the bit B2 has to be switched by the space time switch STS, shown in
Figure 7, the internal scheduling properties of this switch STS cause a placement of this bit B2
within the bit position of the value 1 in the output vector v l . As previously described in detail,
the OR-function elements achieve a reduction of the respective output vectors vO, v l 5 to
respective output bits bO, b(N-l ), as shown in Figure 7.
The resulting single output bits are then written within one writing cycle corresponding to the
time instance t= 1 into bit sub-elements of the writing address wa(x(i),i) =in†( bp(x(i),i)/L ) .
For the next further time instance t=2, Figure 4c shows the placement of the different bits
within the output vectors vO, v l 5 as well as within bit-sub-elements of a same writing
address, equal to the value 2, of the memory elements MO, M l 5 .
By looking at Figure 4c at the right hand side, it becomes evident, that it is now possible to
read out at successive reading cycles respective sets of N bits from the different memory
elements MO, M l 5, wherein within one reading cycle a same reading address is used for
choosing the bit sub-element of each memory element MO, M l 5 .
By reading out sets of N bits from the memory elements as previously described above within
successive reading cycles, a resulting bit pattern RBS2 can be achieved, as shown in Figure 6.
By comparing the bit sequence RBS2 of Figure 6 with the desired bit sequence of bits of the
global frame GF2 of Figure 4b, it becomes evident, that the proposed bit-interleaver Bl shown
in Figure 7 achieves the desired method of bit-interleaving needed for a BIPON.
The choice of the number of bit sub-elements to L=3 is only an exemplary choice. Preferably
the number of bit-sub-elements present within a memory element is chosen to L= 1024.
For achieving an overall data rate of 10 gigabit per second, one may choose the number of N
to 64, while reading out such sets of N bits at a rate or frequency of f = 156,25 MHz. As an
alternative example, sets of N = 32 bits may be written and read at a frequency of f=31 2,5
MHz for achieving the same bit rate of 10 gigabit per second. Even alternatively, one may
choose the number of N to N = l 28 with a reading frequency of f = 78, 25 MHz.
It is a n evident advantage of the proposed bit-interleaver Bl shown in Figure 7, that the global
latency of the system is low, since the reading process of interleaved bits from the memory
elements M0, M(N-l ) can be started, before all the interleaving processes of all bits
forming a global frame is finished.
Preferably, the different sub-devices of the bit-interleaver Bl shown in Figure 7 are
implemented within a single field programmable gate array (FPGA), in the case that th
memory reader is a FIFO-reader.
The functions of the various elements shown in the Figure 7, including any functional blocks
labeled as 'control unit', may be provided through the use of dedicated hardware as well as
hardware capable of executing software in association with appropriate software. When
provided by a processor, the functions may be provided by a single dedicated processor, by a
single shared processor, or by a plurality of individual processors, some of which may be
shared. Moreover, explicit use of the term 'control unit' should not be construed to refer
exclusively to hardware capable of executing software, and may implicitly include, without
limitation, digital signal processor (DSP) hardware, network processor, application specific
integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for
storing software, random access memory (RAM), and non volatile storage. Other hardware,
conventional and/or custom, may also be included. Similarly, any switches shown in the FIGS
are conceptual only. Their function may be carried out through the operation of program
logic, through dedicated logic, through the interaction of program control and dedicated
logic, or even manually, the particular technique being selectable by the implementer as more
specifically understood from the context.

WE CLAIMS:-
1) Bi†-ln†erleaver for a n Optical Line Terminal of a n Optical Access Network, comprising
- a memory reader (FR), operable to receive and provide a number of M data streams (OD1 ,
OD4) assigned to respective optical network units,
- a space-time switch (STS), which is
operable to read within one input cycle up to M respective bit-sets (BS1 , BS4) from
said respective M data streams,
and furthermore operable to switch within one writing cycle up to N bits of said data
streams (OD1 , OD4) onto up to N respective output ports providing respective
output vectors (vO, v(N-l ),
- N OR-function elements (Ol , O(N-l ), each operable to determine within said one
writing cycle respective single output bits (bO, b(N-l )) based o n one of said respective
output vectors (vO, v(N-l ),
- N memory elements (MO, M(N-l ), each comprising at least L bit sub-elements having
respective sub-element addresses, and each being operable to write within said one writing
cycle a respective one of said respective single output bits (bO, b(N-l )) into a respective
one of its bit sub-elements,
comprising furthermore a control unit (CU), which is operable to control
the reading of said M data streams (MO, M(N-l )by said space-time switch (STS),
- the switching of said bits by said space-time switch (STS) onto said output ports,
and a choice of the writing addresses of said bit sub-elements,
wherein said control unit (CU) is operable to choose said output ports and said writing
addresses in dependence o n
predefined data rates,
- predefined offset values,
a maximum number B of bits within a bit-frame, and
the number N,
and the number L.
2) Bit-lnterleaver according to claim 1,
wherein said control unit (CU) is operable to control said space-time switch (STS), such that
said data streams (OD1 , OD4) are read at pre-defined data rates,
and wherein said control unit (CU) is operable to choose within said one writing cycle said
writing addresses of said bit sub-elements to a same address value.
3) Bit-lnterleaver according to claim 1,
wherein each of said respective bit-sets (BS1 , BS4) read from said respective data streams
contains K bits.
4 ) Bit-lnterleaver according to claim 1,
wherein said control unit (CU) is furthermore operable to control respective reading addresses
for reading within one reading cycle respective N bits from said N memory elements.
5) Bit-lnterleaver according to claim 1,
wherein said control unit(CU) is operable to choose within said one reading cycle said reading
addresses to a same address value.
6) Optical Line Terminal for a n Optical Access Network,
comprising a Bit-lnterleaver (Bl) according to one of the claims 1 to 6 .
7) Method of bit-interleaving for a n Optical Access Network, comprising
- receiving and providing a number of M data streams (OD1 , OD4) assigned to
respective optical network units,
- reading within one input cycle up to M respective bit-sets (BS1 , BS4) from said respective
M data streams, using a space-time switch (STS),
- switching within one writing cycle up to N bits of said data streams (OD1 , OD4) onto up
to N respective output ports providing respective output vectors, using said space-time switch,
- determining within said one writing cycle respective single output bits (bO, b(N-l )) based
o n one of said respective output vectors (vO, v(N-l ),
- writing within said one writing cycle a respective one of said respective single output bits (bO,
b(N-l )) into a respective bit sub-element of respective N memory elements (MO, M(N-
1), wherein said respective bit-sub-elements have respective sub-element addresses,
comprising furthermore controlling
- the reading of said M data streams (MO, M(N-l ) by said space-time switch (STS),
the switching of said bits by said space-time switch (STS) onto said output ports,
and a choice of the writing addresses of said bit sub-elements.