PRIOR ART
EEPROM's Electrical erasability is valuable as EEPROM can be erased and reprogrammed without popping them out of their socket.
Each write instruction in EEPROM means erasing its entire content and reprogramming every bit allover again. Changing any one bit in an EEPROM means life of every bit of storage of EEPROM is shortened.
FIELD OF INVENTION
The invention relates to the memory management and write cycle management of non volatile memory of EEPROM.
OBJECTS OF THE INVENTION
An object of the present invention is to provide an improved write cycle technique for an EEPROM.
Another object of the present invention is to provide an EEPROM with improved longer endurance in comparison to the existing endurance.
Another object of the present invention is to provide an EEPROM with increased number of write cycles.
Another object of the present invention is to provide an EEPROM with reduced write cycle time.
Another object of the present invention is to provide an EEPROM with increased write cycles but with minimal erase cycle.
SUMMARY OF THE INVENTION
The present invention of performing write and read instructions to memory blocks of a EEPROM is performed by maintaining an active check sequence pattern.

The active check sequence pattern registers the status of the memory block and indicates the next write location.
DESCRIPTION OF THE INVENTION
The invention is now described beginning from a typical EEPROM, wherein a typically real EEPROM guarantees 10k write cycles for each byte. It is attempted in this invention to obtain a higher number for cycling endurance with the same number of erase cycles.
All ECU uses the EEPROM or Flash to write run time data for example seat position of the position of the mirror for driver 1 end of line data for example whether car is left hand drive or right hand drive. All faults which occur in regular operation mode have to be stored (a max. of 15 faults at a time) for at least 80 ignition cycles. They are stored in an EEPROM etc... This data is written in EEPROM and read during the normal run time of the ECU. Some of the EEPROM is having limited write cycles e.g. EEPROM cell is capable of 10.000 write/erase cycles. In our case that would mean we could store fault information up to 10.000 ignition cycles, which would be insufficient. Therefore we developed a strategy to increase the life expectancy more than 10.000 ignition cycles. We call this strategy as block rotation mechanism. Means a method which can be used to rotate the block so that data can be written more than 10000 times.
An EEPROM is divided into several clocks, a status register, which is a register that holds configuration and status information and the page latches which temporarily is the holding area for data being written.
Typically in an EEPROM each block is composed of plurality of memory cells. Each block is composed of plurality of pages, each page comprising plurality of bytes, the page is considered to be the minimum set of data that can be updated in an EEPROM. The user may update less bytes than the page size but internally the algorithm always performs the full page update.
In the present invention an EEPROM device is envisaged including a memory section, which is composed of plurality of blocks for data storage, each of the said blocks having identical storage capacity to each of the others of said blocks,

and having endurance characteristic determining the number of times that data may be erased from and written to the respective blocks and also includes the memory control section for programming the device to configure and designate at will the sequence of write cycle amongst the plurality of blocks.
Each bit of the non volatile memory cannot be over written from a first logical state (0) to a second logical state (1) without prior erase.
Each bit of the non volatile memory can be over written from a second logical state (1) to a first logical state (0) without prior erase.
Some controller provides for bit programming means if there is transition from 1 to 0 then no need to erase the page means writing can be done without erasing. But if there is transition from 0 to 1 then first erase then write.
One such controller is MC68HC908AZ60A from Motorola.

When an EEPROM is new all the cells contain the data for example: FF.
The unique aspect of the present invention is that an active-check sequence pattern for example an 8-bit pattern maintains the status of the blocks of the EEPROM.
For explanation as shown in table 1, let us consider an EEPROM with 8 blocks. The status of each block is maintained by 8-bit active check sequence pattern.

The EEPROM when new the active check sequence pattern is 11111111. In order to write a new data, as the EEPROM is new the first data is written in the first block and the active check sequence is updated to 11111110.
When a next data has to be written, the active check sequence indicates that the previous data was written in the 1st block, so the current new data will be written in 2nd block and the active check sequence will be updated to 11111100. The process of writing new data will continue from 1st block to 8th block and the active check sequence will be updated after each write instructions. On completion of write instructions in the 8th block the active check sequence pattern will be updated as 00000000.
In order to continue writing new data to the blocks, the active check sequence pattern has to be erased and the process of writing the data in the 1st block and simultaneous updating of active check sequence is performed as earlier. The erasing operation is performed only once after data are written to all 8 blocks. The check sequence pattern will be updated after writing all the data including the checksum so that during power failure either the default data or the previously written data is retained.
The updating of the active check sequence indicates the block to which the new data has been written and in-turn indicates the next block to which the subsequent data has to be written. According to the present invention only one bit is used to indicate the active status of the EEPROM.
With the present invention the status of an active block is identified by only one byte for 8 blocks. As a result the memory consumption is reduced and execution time is also reduced as only one erase operation is required after 8 write instructions.
Assuming that for one full erase of all blocks, 8 updating operations are required and that the endurance of 10k cycle is guaranteed then the maximum cycling for each byte is 8 x 10k i.e. 80 k cycles

The plurality of non volatile data blocks in EEPROM are such that each one of the blocks is selectively programmable as per predetermined sequence of write cycles and erase cycles.
EEPROM is herein arranged in plurality of blocks each having plurality of bits. Programming is carried out block wise i.e. every single block has to be programmed separately. The erase cycle includes fully programming each bit in the block to be erased.
EEPROM is normally used to store data and variable values that the program will use while it is running and programs may also reside in the EEPROM. The EEPROM being electrically erasable will erase its own ROM and download new data to be written into it. This allows new programs and data to be downloaded into the chip. Also because it is ROM, when the processor is powered down its program or data does not go away.
The chip erase mode of an EEPROM according to the present invention herein allows the array to be in "1" state, which is useful when the entire device can be erased very rapidly. The first state relates to the change of pattern of the active check sequence from '0' to *1'.
By this methodology of rotating the blocks for write cycle there is a minimizing of erase cycle of the memory by choosing the blocks in predetermined sequence such that the writing into blocks is without prior erase and the erase is limited only as all chip erase.
The active check sequence pattern acts as the directory or the controller which logs the history of the data blocks to which data is written or read and manages the data blocks including the initialization for each sequence of operation.
The active check sequence pattern area shall have different states representing and corresponding to active state of plurality of data blocks.
It is illustrated in the description and the drawings herein that the most important feature of the present invention is that the data is written by rotating the blocks in

a particular sequence. The memory may be filled in definite sequence, may be from first block, second block, third block, etc i.e. one end to the other end as illustrated. However, since the blocks may be randomly accessed, it could be written or filled in any prescribed order. All these are within the scope of this invention.
In the first embodiment it is so programmed that there is only one erase cycle after plurality of write cycles equivalent to plurality of data blocks. Here each block is written once before the write cycle goes to the next block.
The EEPROM device herein has a data memory composed of plurality of blocks of equal capacity and having means for selectively identifying one of the plurality of blocks for writing without prior erasure just immediately before writing and selectively identifying the sequence of selecting the blocks.
Instead of overall block of cells in EEPROM, each one of which can be addressed by its own row and column number, multi block system is attempted to split the storage of each EEPROM chip into a number of separate blocks and the blocks are interconnected through another memory area that can access and control each block individually and simultaneously.
In another embodiment wherein the microcontroller does not support the bit programming then as follows it is so programmed that there is only one erase cycle after write cycles equivalent to predetermined number of write cycles in each of the plurality of blocks. Here the block may be written more than once before the write cycle moves to the next block. It is so programmed that the write cycle is as per predetermined sequence of write cycle amongst plurality of blocks.
The life cycle of the EEPROM has been attempted to increase herein to rotate in predetermined sequence the plurality of blocks to write data repeatedly, such that writing is done from one block to the next block and so on without prior erasing, by capturing the active block and thereafter only after plurality of write cycles onto the data blocks, a single erase - write cycle will erase the entire chip and

initialize the chip simultaneously for commencing the next sequence of write cycle.
The EEPROM size applicable and the block size applicable is flexible within the limits and constraints of availability and feasibility of the application. The status of the blocks is maintained by byte active check sequence. Each block for example here is assigned to a byte pattern FF.
The rotation may be done by using byte pattern as one of the embodiments which is illustrated in table 2.
Here 1st writing will be done in the first block, 2nd writing will be done in second block and 3rd writing will be done in third block etc. Bit programming is not supported by the controller so we can use 1 byte to find the active block. This byte should be written after writing all the data including checksum. If the byte pattern is updated in the beginning of write cycle then in case of power failure we could have either default data or oldest data. So this byte must be written at the end of data write cycle.


As the EEPROM is new the active check sequence of all blocks is FF. During the 1st write cycle, the data is written to the first block and subsequent data is also written to the first block. This continues for a predetermined time and the active check sequence is updated to AA. After updating the data to be retrieved will be obtained from 1st block and incase of next write operation, the data will be written in the 2nd block.
It is to be noted that irrespective of the type of programming and the mechanism adopted, the object of rotating the blocks for sequence of writing without interruption of erase has been achieved in all the embodiments. Due to the deletion, elimination or reduction of this erase cycles, there is a substantial increase in the write cycle of the EEPROM thereby enhancing the life cycle of the EEPROM.

WE CLAIM
1. A method of writing/reading from a EEPROM having a configurable
controller comprising a sequential writing onto subsequent block for each
subsequent write cycle, the method comprising of steps:-
a. providing a plurality of blocks;
b. providing a block active-check sequence such that each block is
associated to one bit of the block active check sequence;
c. associating each write cycle with one bit of the block active check
sequence;
d. reading the block wherein the latest write cycle is performed based
on the block active-check sequence;
e. identifying the next block for a write cycle based on the block
active-check sequence; and
f. updating the block active-check sequence after each write cycle to
enable commencement of next write cycle.
2. A method of writing/reading from EEPROM according to claim l,
a. updating the block active-check sequence after each write cycle to
enable commencement of next write cycle; and
b. performing the erasing operation only once after all the blocks have
completed the write operation.
3. A method of writing/reading from EEPROM having a configurable
controller comprising a sequential writing onto subsequent block for each
subsequent write cycle, the method comprising of steps:-
a. providing a plurality of blocks;
b. providing a block active-check sequence such that each block is
associated to one byte of the block active check sequence;
c. reading the block wherein the latest write cycle is performed based
on the block active-check sequence;
d. identifying the next block for a write cycle based on the block
active-check sequence; and

e. updating the block active-check sequence after each write cycle to enable commencement of next write cycle.
A method of writing onto EEPROM according to claim 3,
a. updating the block active-check sequence after each write cycle to
enable commencement of next write cycle; and
b. performing the erasing operation only once after all the blocks have
completed the write cycle.