BOND PAD POLLING CIRCUIT
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to the field of configuring integrated circuit devices during power-up. More particularly, the present invention relates to a polling circuit for configuring electronic memory devices such as dynamic random access memories (DRAMs) and other integrated circuit devices.

BACKGROUND OF THE INVENTION
Conventional integrated circuits are often designed as configurable chip devices that can be configured in different operating modes. Usually, special bond pads are provided for the purpose of choosing a particular configuration by way of connecting the bond pad to a predefined logic level. Such bond pads are called "option pads." Before packaging such chip devices, option pads are connected to either the positive or negative power rail, typically with expensive gold wires, such that the internal circuitry of the chip devices can use the logic high or low levels of the option pad, respectively, to permanently configure silicon devices within the chip to function in one of two possible ways. As such, chip manufacturing costs are significantly reduced in that the same mask set can be used to manufacture two functionally similar but slightly different chip devices.
Designers often use a technique called "polling" at the initialization or "power-up" of a chip device to avoid the necessity of having to connect option pads to either of the power rails. Polling is performed by external circuitry attached to the option pad. At power-up, the polling circuit determines whether the option pad is floating in the sense that it is not connected to any power rail. Thus, the output of the polling circuit presents two different logic levels to the internal circuitry .of the chip depending on whether the option pad is connected or not connected. This way, the requirement of connecting an option pad to either a positive or negative rail is reduced to the requirement of connecting the option pad to either one of the power rails, or not connecting it at all, thereby leaving the option pad floating. Thus, for example, an integrated circuit can be configured in one of two ways when an option pad is connected to the negative power rail, and differently when it is left floating. Advantageously, the cost of gold wires, which can be very high in mass production, is significantly reduced.
Polling circuits, however, often require a sufficient pulse width generated at power-up for correct operation. Consequently, conventional polling circuits often fail due to inadvertently shortened pulses. A power-up pulse may get shortened due to a variety of reasons depending on how the circuit generates such a pulse. For example, in

Dynamic Random Access Memory (DRAM) devices, where substrate voltage levels are used to generate such pulses, power-up pulses may be significantly shortened when power-down and power-up happens in quick succession.
In addition, since option pads are usually large in dimension with respect to the semiconductor integrated circuit, an option pad can create a parasitic capacitance that worsens the performance of the polling circuit.

SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an electronic circuit for reliable bond pad polling during power-up and initialization.
Another object of the present invention is to provide an electronic circuit for bond pad polling using power-up pulses having narrow pulse widths as compared to the conventional circuits.
Still another object of the present invention is to provide an electronic circuit for properly initializing the mode configuration by way of a polling option pad for integrated circuits including DRAMS.
Accordingly, a bond pad polling circuit is provided which overcomes the afore described limitations and inadequacies of conventional polling circuits. In accordance with a preferred embodiment of the present invention, the bond pad polling circuit includes: a first inverter for receiving and inverting a power-up signal; a first pull-up device coupled to the first inverter for providing a first logic signal; a second inverter coupled to the first pull-up device for inverting the first logic signal and for providing a corresponding second logic signal at the output the circuit; and a second pull-up device coupled to the first pull-up device and the second inverter for feeding back the second logic signal to the second inverter. The bond pad polling circuit further includes a third pull-up device coupled to the bond pad, the first inverter and the first pull-up device for applying a third logic signal to the bond pad; and an isolating device coupled to the first inverter, the first pull-up device, the second pull-up device and the bond pad for electrically isolating the bond pad from the second logic signal.
Further objects, features and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying figures showing illustrative embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS
For a complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein:
FIG. 1 is a schematic representation of conventional bond pad polling circuit; and
FIG. 2 is a schematic representation of bond pad polling circuit according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION
In order to adequately describe the present invention, reference is made to a conventional polling circuit as shown in FIG. 1.
FIG. 1 shows a schematic representation of a conventional bond pad polling circuit 10. The conventional bond pad polling circuit 10 includes a bond pad 11 attached to an electronic device, a first inverter 20 for inverting a power-up signal, and first pull-up device 16 connected to the first inverter 20 at node n3. As shown in FIG. 1, the bond pad 11 is assumed to be floating and the first and second pull-up devices 16 and 18 are p-MOS transistors having their drains coupled at node n3 and their source terminals coupled to a positive rail Vcc. The conventional polling circuit 10 also includes a second inverter 24 connected to the second pull-up device 18 via a feedback loop 23 between the input and output of the second inverter device 24.
According to the conventional polling circuit of FIG. 1, the power-up signal is a monoshot pulse generated elsewhere in the integrated circuit (not shown) coupled to the input of the first inverter 20. The power-up signal goes to a logic high level during power-up of the integrated circuit, and is set at a logic low level for the remainder of the time power is applied to the integrated circuit.
At power-up, when the power-up signal goes to a logic high .level, the output of the first inverter 20 goes to a logic low level along with the logic state at the gate of the first pull-up device 16. As such, the first pull-up device 16 is turned on and current is allowed to flow through the first pull-up device 16 from the positive rail 30 (+VCC). This causes the charging of the bond pad's parasitic capacitance, shown in FIG. 1 as capacitor 12, to the logic high level made possible by the positive rail. The second inverter 24 inverts the logic level at node n3, which causes a logic low level to appear at the output of the second inverter 24. The logic low at the output of the second inverter 24 is fedback and applied to the gate of the second pull-up device 18, which in turn activates the second pull-up device 18 for supplying current to the node n3. During normal power-up of the integrate circuit, the second pull-up device 18 and the second inverter 24 of the conventional polling circuit together act as a latch

structure for driving the voltage Vbp at the bond pad 11 to a logic high level.
When the power-up signal returns to a logic low level, the gate of the first pull-up device 16 goes to a logic high level and the first pull-up device 16 stops conducting current to the node n3. If the bond pad 11 is floating, Le,, in the sense that it is not connected to any of the power rails, the second pull-up device 18 remains "on," the output of the second inverter 24 remains at a logic low level, and the node n3 along with the potential at the bond pad 11 remain at a logic high level.
In the case that the bond pad 11 is coupled to a negative power rail, e.g., ground (not shown), then the current from the node n3 and the bond pad 11 flows to the negative rail and the second pull-up device 18 cannot supply enough current to keep the potential at node n3 and the bond pad 11 at a logic high level. Eventually, after the power-up signal returns to a logic low, the potential at the node n3 returns to a logic low and the output of the second inverter 24 returns to a logic high. The second pull-up device 18 is thus turned off after the initial power-up of the integrated circuit.
Accordingly, the only function of the power-up signal is to charge-up the node n3 and the bond pad 11 at the power-up of the integrated circuit. If the bond pad 11 is floating and not connected to any power rail at the time of power:up, then the charge and the logic level present at the bond pad 11 during power-up, a logic high level in this case, remains and the output of the polling circuit 10 is set to a logic low level. Otherwise, if the bond pad 11 is connected to a power rail, for example the negative rail, then the charge and logic level remaining after the power-up signal returns to a logic low level is determined by the power rail. In the case of the bond pad coupled to the negative rail, the output of the polling circuit 10 would be a logic high level. This way of determining the logic state of the bond pad is known as "polling."
The potential shortcomings of the polling circuit shown in FIG. 1 are apparent in cases where the power-up signal does not remain at a logic high level for a sufficient period of time. The duration of the power-up pulse is especially important

due to the fact that the parasitic capacitance associated with the bond pad is considerably high. When the logic high period of the power-up signal is too short, the first pull-up device 16 does not have enough time to sufficiently charge the node n3 and the bond pad 11 to a logic high level, thus not allowing the inverter 24 and the second pull-up device 18 to go into a latched state.
Power-up pulses may be shortened for various reasons depending upon how it is generated. For example, in DRAM devices where power-up pulse are generated based upon a substrate voltage level, pulse shortening can occur when an integrated circuit is powered-on immediately after being powered-down. In such cases, where the bond pad is floating (not connected to any power rail) and the power-up pulse is shortened, the first pull-up device 16 cannot conduct enough charge to establish a logic high level at the node n3. Consequently, the voltage level at the output of the second inverter 24 cannot be guaranteed by design. If the voltage at the output of the second inverter 24 happens to be at a logic high level, the second pull-up device 18 will not turn on and the output of the second inverter 24 will remain at a logic high level after the power-up signal returns to a logic low level. This is a malfunction of the polling device since by keeping the bond pad 11 floating, a logic low level is implied at the output of the second inverter 24. In such a case, the conventional polling circuit 10 of FIG. 1 thus fails to successfully "poll" the state of the bond pad 11.
Therefore, the polling circuit 10 of FIG. 1 is problematic when the power-up signal is characterized by a narrow pulse width, in which case the second pull-up device 18 may not turn on in time before the power-up signal returns to a logic low level.
FIG. 2 shows a schematic representation of an improved polling circuit 100 for bond pad polling according to a preferred embodiment of the present invention. The polling circuit 100 is similar to the conventional polling circuit 10 of FIG. 1, but in addition includes a third pull-up device 22 for separately powering-up the bond pad 11, and an isolating device 14 coupled between the first and third pull-

up devices 16 and 22 at node n3 for electrically isolating the first and third pull-up devices 16 and 22 from each other.
As further shown in FIG.2, the first and third pull-up devices 16 and 22, respectively, are p-channel metal-oxide-semiconductor (p-MOS) transistor devices whose gates are coupled together at node nl to the output of the first inverter 20 and to the gate of the isolating device 14, which is an n-channel MOS (n-MOS) connected between the drains of the first and third pull-up devices 16 and 22. When the power-up signal is a logic high signal, the potential at the node nl is at a logic low level and the isolating device 14 is cut-off. As such, the isolating device 14 serves to electrically isolate the bond pad 11 from the node n3 when the power-up status signal is a at a logic high level.
Accordingly, when the power-up signal is at a logic high level, the output of the first inverter 20 at node nl is at a logic low level and thus the gates of the first and third pull-up devices 16 and 22 are at a logic low. Consequently, the third pull-up device 22 is turned on and thus the voltage Vbp at the bond pad 11 is pulled high. The gate of the isolating device 14, however, remains at a logic low level, which serves to keep the isolating device 14 in an off state during power-up. Accordingly, the first pull-up device 16 only has to charge-up according to the parasitic capacitance at node n3, since the current supplied by it does not flow to the bond pad 11 since the isolating device 14 is in an off state. Since the capacitance at the node n3 is significantly less than that at the bond pad 11, the node n3 charges up to a logic high level very quickly as compared to the logic state at node nbp.
As a result, when the power-up signal is at a logic high level, the output of second inverter device 24 goes to a logic low level very quickly and the second pull-up device 18 turns on. At the same time, the third pull-up device 22 is turned on and current is conducted through the third pull-up device 22 to independently charge the bond pad 11.
When the power-up signal returns to a logic low level, the gates of the first and third pull-up devices 16 and 22 are set to a logic high level, thus turning off

the first and third pull-up devices 16 and 22 and turning on the isolating device 14. As such, when the power-up signal is at a logic low level, the isolating device 14 serves to electrically couple the bond pad 11 with the node n3. In addition, because of the threshold voltage V, drop of the n-MOS isolating device 14, the node n3 is less susceptible to charge sharing with the bond pad 11 after the power-up signal returns to a logic low level. At this stage the second pull-up device 18 is turned on so that even if the bond pad 11 is not fully charged to a logic high level (by the third pull-up device 22), then the second pull-up device 18 continues charging the bond pad 11.
In addition, in the case where the bond pad 11 is coupled to a negative power rail, j^e., the bond pad is not floating and for example connected to ground, then the node n3 eventually discharges and the output of the second inverter 24 goes to a logic high level. This causes the second pull-up device 18 to turn off since the negative rail can sink far greater current than the second pull-up device 18 can source. Consequently, more charge is drained to the negative rail than is replenished by the second pull-up device 18, and thus the node n3 is finally discharged and returned to a logic low level.
In summary, the polling circuit 100, as shown in FIG. 2, eliminates the shortcomings of the prior art in that the circuit guarantees that the second pull-up device 18 will turn on when the power-up signal is characterized by a relatively short pulse width. The polling circuit 100 of FIG.2 is characterized in that the time required to charge up the node n3 is on the order of 100 times less than the time required to charge node n3 in the conventional polling circuit 10 of FIG. 1. Since the second pull-up device 18 is guaranteed to turn on before the power-up pulse transitions to a logic low level, the success of the polling circuit is greatly enhanced.
Although the present invention has been described in connection with particular embodiments thereof, it is to be understood that such embodiments are susceptible of modification and variation without departing from the inventive concept disclosed. All such modifications and variations, therefore, are intended to be

included within the spirit and scope of the appended claims.

1. An electronic circuit for polling a bond pad comprising:
a first inverter for receiving and inverting a power-up signal;
a first pull-up device coupled to said first inverter for providing a first logic signal;
a second inverter coupled to said first pull-up device for inverting said first logic signal and for providing a corresponding second logic signal at the output of said circuit;
a second pull-up device coupled to said first pull-up device and said second inverter for feeding back said second logic signal to said second inverter;
a third pull-up device coupled to said bond pad, said first inverter and said first pull-up device for applying a third logic signal to said bond pad; and
an isolating device coupled to said first inverter, said first pull-up device, said second pull-up device and said bond pad for electrically isolating said bond pad from said second logic signal.
2. The electronic circuit according to claim 1, wherein said isolating device activates said second pull-up device and said third pull-up device charges said bond pad separately from said first pull-up device.
3. The electronic circuit according to claim 1, wherein said power-up signal is a monoshot signal defined by a power-up pulse having a pulse width corresponding to a logic high level, and wherein said power-up signal transitions to a logic low level after said power-up pulse.
4. The electronic circuit according to claim 3, wherein said isolating device is a n-MOS transistor device and said first, second and third pull-up devices are p-MOS transistor devices.

5. The electronic circuit according to claim 3, wherein said bond pad is floating and said third logic signal remains unchanged after said power-up signal transitions from said logic high level to said logic low level.
6. The electronic circuit according to claim 3, wherein said bond pad is coupled to a power rail and said third logic level is determined by said power rail after said power-up signal transitions from said logic high level to said logic low level.
7. The electronic circuit according to claim 6, wherein said bond pad is coupled to a negative power rail and said third logic level is at said logic low level after said power-up signal transitions from said logic high level to said logic low level.

8. An electronic circuit for polling a bond pad substantially as herein described with reference to the accompanying drawings.