FORM 2
THE PATENTS ACT 1970
[39 OF 1970]
COMPLETE SPECIFICATION
[See Section 10]
"BROKEN STACK PRIORITY ENCODER"
INTEL CORPORATION, a Delaware Corporation, 2200 Mission College Boulevard, Santa Clara, California 95052, United States of America
/
The following specification particularly describes the nature of the invention and the manner in which it is to be performed :-


Broken Stack Priority Encoder
Field The present invention relates to circuits, and more particularly, to priority encoder circuits.
Background
Priority encoders provide signals indicative of the leading one ("1") or zero ("0") in a binary word. Lfsually, a priority encoder will have as many output lines as the length or number of bits in a binary word, and the voltages on the output lines indicate the leading one or zero in the binary word. For example, a priority encoder to indicate the leading one in an 8-bit word may have eight output lines in which at most one output line has a HIGH voltage (the others are at a LOW voltage), where the one output line with a HIGH voltage indicates the position of the leading one.
Within a priority encoder circuit, there may be one or more groups (or stacks) of serially connected transistors which bring various nodes to a LOW (ground) voltage, depending upon the bit values of the word. To discharge (or pull down) a node to LOW, a transistor stack provides a conducting path between the node and ground. An output circuit coupled to these nodes may then provide the necessary signals indicating the leading zero or one in the word.
In a domino (or dynamic) type priority encoder circuit, the nodes are charged (or pulled up) to a HIGH voltage during a pre-charge state or phase of a clock signal, and then some or all of the nodes are discharged by various transistor stacks during an evaluation state or phase of the clock signal. The speed at which a domino priority encoder can operate may be limited by the speed at which the various nodes can be discharged. For a given technology, this speed may be increased (i.e., discharge time is decreased) if the stack depths of the transistors (i.e., the number of serially connected transistors in a conducting path between a node and ground) are reduced. For a static type priority encoder circuit, it also may be desirable to reduce the stack depths to increase speed. Also, for CMOS (Complementary Metal Oxide Semiconductor) technology, reducing stack depths may be desirable due to the so-called body effect.
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Therefore, it is desirable to reduce the transistor stack depths in priority encoder circuits.
Brief Description of the Drawing
Fig. 1 is an embodiment of a dynamic type broken stack priority encoder.
Fig. 2 is an embodiment of a static type broken stack priority encoder. Detailed Description of Embodiments
We begin with terminology. The two-element Boolean algebra is relevant to switching circuits. For any point in a circuit, the term LOW will denote a set of voltages that map into one of the two Boolean elements, and the term HIGH will denote a set of voltages that map into the other of the two Boolean elements. The particular range of voltages that map into the Boolean elements depends upon the technology used, and may be different for different parts of a single circuit. To avoid dealing with set terminology, we shall say that a voltage is LOW (HIGH) if it belongs to the set LOW (HIGH). We also follow the convention that for any given node within a circuit, LOW voltages are less than HIGH voltages.
For the particular embodiments described herein, we shall incur a slight (but usual) abuse of notation by allowing the terms HIGH and LOW, which have been defined as voltages, to do double duty, so that HIGH and LOW also represent the two Boolean elements of the two-element Boolean algebra. It will be clear from context when HIGH or LOW represent a voltage or a Boolean clement. It is customary to identify HIGH with the identity element for the binary Boolean operation AND and to identify LOW with the identity element for the binary Boolean operation OR, and this custom is followed here. Such an identification is pedagogically useful, but arbitrary, and it should be appreciated that the present invention is not limited by this particular identification of voltages with Boolean elements.
Let an 8-bit word W be expressed as (B1 B6 ... B0)where B' is the ith bit of word W. 7 and °are, respectively, the most significant bit and the least significant bit of word W. We incur another slight abuse of notation and let B' also denote a voltage and Boolean element, and without loss of generality we take B' to be HIGH if the /th bit
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of word W is 1 and to be LOW if the /ith bit of word W is 0. The term "word" is not to be confused with the wordlength of a computer system. Here, a word simply refers to a binary tuple.
Shown in Fig. 1 is an embodiment priority encoder 100 for word W. The output
of Fig. 1 is the set , where an ■ represents either a voltage or a
Boolean element, depending upon context. In Fig. 1, a set of values such that
E. = LOW for all i = k and Ek _ HIGH indicates that the leading zero of word W is the
bit * .If - = L0W for all /, then word Whas no leading zero, i.e., all the bits for W are ones.
In Fig. 1, represent voltages or Boolean elements, depending
upon context. As voltages, they represent gate voltages for nMOSFETs (n-Metal Oxide Semiconductor Field Effect Transistor) 114, 116, and US, respectively. When
considered as Boolean elements, ', and - are given by the Boolean expressions

where • denotes logical (Boolean) AND. In Fig. 1, domino gates 122, 124, and 126 are used to provide , although other types of logic gates may be employed.
A set of 8 nodes is labeled in Fig. 1. In addition to being a
label, the symbol • is also used to indicate the voltage or Boolean value of node •,
depending upon context. When clock signal CLK is LOW ( »or ground), pMOSFETs 102 are ON and nMOSFET 103 is OFF, so that all nodes arc charged (pulled up) to
HIGH ( «). This is the pre-chaige state (phase). The evaluation state (phase) is characterized by CLK being HIGH. During an evaluation phase, pMOSFETs 102 are OFF and nMOSFET 103 is ON, causing some of the nodes to be pulled down to LOW
depending upon the values for
The gates of nMOSFETs 104, 106, 108, 110, and 112 are at voltages , i= 1, 3, 4, 6, and 7, respectively, and the gates of nMOSFETs 114, 116, and 118 are at

voltages A ' ,i = 0, 1, and 2, respectively. During an evaluation phase, it can be seen
from Fig. 1 that the value for node N, expressed in terms of the bit values B, i= 0,1,-7, isgivenby

where the over-bar denotes Boolean complement and the product indicates the Boolean AND operation.
The above expression assumes that a node, if not discharged to ground via a conducting path of transistors, will hold its charge during the evaluation phase. This assumption depends upon the capacitance of a node and the switching frequency of CLK. If needed, in some embodiments half-keepers may be employed at the nodes to keep them charged HIGH if they are not discharged to ground potential via a conducting path of transistors.
Note that in Fig. 1 the path from any node to ground (not counting nMOSFET 103) is only three transistors.,It is desirable to keep these paths as small as possible because the discharge time for any node is dependent upon the number of serially connected transistors discharging the node to ground. In a sense, the stack of transistors
104, 106, 108, 110, and 112 is "broken" at nodes N', i = 0, 2, and 5, so that some or all of transistors 114, 116, and 118 provide a bypass path between these nodes and ground. Hence the name "broken stack" priority encoder.
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The outputs Ei, / = 0, 1. ... 6, are indicative of the node voltages via logic gates 120. In terms of node Boolean values, the values for ire given by

In terms of the Boolean or bit inputs , the are given by

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The above two Boolean expressions are equivalent to the statement that ' = HIGH if
and only if = LOW and axe all HIGH. Therefore, tfve embodiment
of Fig. 1 is seen to be a priority encoder.
An entire class of embodiments for any word W of arbitrary word length N+l,
denoted b> may be described as follows. Choose a set
integers with such that

Define the K+2 sums
Note that
Partition the set of ordered integers disjoint sets
1,... K, of ordered integers where

Note that the number of elements in the set l is "l. Label the elements in *, from
left to right, as - - . Define a set of A'+l values (Boolean or
voltage where

Note that A* is the logical AND of nt terms.
Using the above formalism, an embodiment can now be described as follows for
any chosen integer set /. There are N+l node; , a by-pass stack of K+l
nMOSFETs connected in series, and a broken stack of ( nMOSFETs. The broken
Stack comprises groupsof serially connected nMOSFETs.
Group comprises serially connected nMOSFETs labeled as

The gate voltage of nMOSFET where to
avoid subscripts with subscripts we have set (This last statement may
perhaps be more easily visualized by noting that deleting bits , from
the word yields a vector whose values arc the gate voltages of the
nMOSFETs in the broken stack.) The drain of nMOSFET is connected to (or
defines) node . Label the K+l nMOSFETs in the by-pass stack as
. The gate voltage of nMOSFET , the drain of
nMOSFET defines node , and the source of nMOSFET is connected
to the source of nMOSFET
To continue the description of the above embodiment for the chosen integer set /, an pMOSFET is connected to each node and has a gate controlled by a clock signal
CLK, and an nMOSFET is connected to the source ol and has a gate
controlled by the clock signal CLK. There are N output circuits
each having an output voltage . Each output circuit has two
inputs labeled as having voltages and , respectively.
(Again, our notation is performing a double duty.) For any output circuit
its output voltage is given by , input is
connected to node •', and input is connected to nodeThe embodiment
also has an output voltage defined as the output voltage of node
In terms of the Boolean or bit inputs , it can be shown that the
are given by

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The above two Boolean expressions are equivalent to the statement that = HIGH if
and only if = LOW and are all HIGH. Therefore, the above
formalism describes a priority encoder.
An optimum integer set can be defined as that integer set which minimizes a cost function. One particular cost function is the maximum stack depth of transistors connecting each node to ground, including the number of terms in each expression for
•. For simplicity, we do not. include any clocked transistors in the stack depth.
Including in a cost function the number of terms in each Boolean expression for is warranted if these voltages are obtained by domino logic gates performing logical
ANDs applied to the appropriate terms , for then the number of such terms is
indicative of the stack depth of such domino logic gates used to obtain A1.
Such a cost function is obtained as follows. The stack depth for nodes
. The stack depth for
node: . Note, however, that the maximum stack
depth for the nodes is clearly the total number of
nMOSFETs in the by-pass stack. The number of terms in the Boolean expression forA' is n1. Thus, we can write a cost function as

Then, given N, a particular optimum integer set is a set where such that

The above integer set is the so-called "min-max" solution. It can be verified that for a word length of 8 (i.e., N ~ 7), the min-max integer set for the above cost criterion or
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function is unique Fie. 1.

/ ={ 3 3} .
and is , which is the integer set for the embodiment of

Other cost functions may be chosen. For example, if the voltages ' arc obtained by circuits in which the stack depths are relatively small, then the following cost function may be of utility:

Other cost functions may be based upon an average stack depth, rather than the maximum stack depth. The average may weight the stack depths according to a weighting factor if there is a priori information thai some nodes arc more likely to be discharged than others. The min-max approach may be the more conservative approach, but clearly many cost functions may be utilized.
ft should be noted that if the integer set is chosen such that for all
, the resulting priority encoder degenerates to the case in which there is only one stack (one by-pass stack and no broken stack, excluding any
stacks to obtain , and the stack depth for node . Thus, for there to be a
broken stack, there should be at least one integer n• in the integer set for which
Several priority encoder embodiments as described herein may be combined together into a single priority encoder for handling large word lengths. For example, for a 64-bit word, four priority encoders for N = 7 as described herein may be used to encode eight 8-bit blocks of the 64-bit word in a parallel fashion. Relatively simple logic gates may be employed to indicate the leading one or zero of the 64-bit word based upon the outputs from the N -7 priority encoders.
Various modifications may be made to the above disclosed embodiments. For example, clocked nMOSFETs may not be needed if the gate voltages arc obtained from other domino logic gates in which inverters are used between the domino logic gates and the priority encoder, for then all gate voltages will be LOW during the pre-charge phase. In this case, the source of the last transistor in the broken stack is connected to
ground. On the other hand, if the voltages ' are not obtained via domino logic gates,
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then a clocked nMOSFET may be needed at the source of the last transistor in the by¬pass stack.
It should be appreciated that the embodiments described above arc of the domino (or dynamic) type, in that various nodes are pre-charged (pulled up) HIGH before possibly being discharged (pulled down) by stacks of serially connected transistors. However, other embodiments may include static type (dual-rail) circuits.
In the static case, the clocked transistors arc not needed, and for each relevant node one or more pMOSFETs arc connected in parallel to pull up the node HIGH when any of the pMOSFETs axe ON. Whereas in the dynamic case all relevant nodes are pulled up HIGH during a pre-chargc phase and a subset of the relevant nodes is pulled down LOW during an evaluation phase, in the static case all relevant nodes are either LOW or HIGH (after some settling or delay time interval) depending upon the current gate voltages of the various nMOSFETs and pMOSFETs. To avoid cumbersome terminology, we shall say that a stack of nMOSFETs pulls down a node LOW if the stack brings the node voltage from HIGH to LOW, or, if it keeps the node LOW if the node is already LOW. A similar statement applies to pMOSFETs that pull up (or keep) a node HIGH.
A static embodiment is easily obtained by modifying a dynamic embodiment as follows. Remove all clocked pMOSFETs and all clocked nMOSFETs from the dynamic embodiment, where transistor sources that were connected to a clocked nMOSFET arc
now connected to ground. For each ■ connected to a transistor stack of depth n, add n
pMOSFETs, each with a drain connected to • and a source connected to a HIGH voltage source, where each pMOSFET belonging to the added pMOSFETs has a gate connected to one and only one of the gates of the nMOSFETs within the transistor stack
for"*.
An example of a static priority encoder corresponding to the dynamic priority encoder of Fig. 1 is provided in Fig. 2, where corresponding elements in Figs. 1 and 2 have the same label. Fig. 2 is similar to Fig. 1, except that the source of nMOSFET 112 is connected to ground, all clocked transistors are deleted, and pullup pMOSFETs have been added as explained above.
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It should also be appreciated that other embodiments may include technology other than CMOS. For example, other types of IGFETs (Insulated Gate Field Effect Transistor), or FETs (Field Effect Transistors), may be employed instead of the nMOSFETs and pMOSFETs described above. More generally, other types of transistors, such as bipolar transistors, may be employed instead of the nMOSFETs and pMOSFETs.
In other embodiments, the outputs E' may be complemented, in which case a LOW output signal provides information indicative of the leading zero bit. Furthermore, any leading zero priority encoder is easily convened into a leading one priority encoder by complementing the word W. Therefore, the term priority encoder encompasses circuits which provide output signals indicative of either the leading one or leading zero of a word.
Consequently, it is clear that many modification may be made to the embodiments described herein without departing from the scope of the invention as claimed below.
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What is claimed is:
1. A priority encoder comprising:
a by-pass stack comprising first, second, and third nMOSFETs; a broken stack of nMOSFETs comprising first, second, and third groups, wherein:
the first group comprises an nMOSFET having a source coupled to the source of the first nMOSFET in the by-pass stack;
the second group comprises first and second nMOSFETs serially coupled to each other, where the second nMOSFET in the second group has a source coupled to the source of the second nMOSFET in the by-pass stack: and
the third group comprises first and second nMOSFETs serially coupled to each other, where the second nMOSFET in the third group has a source coupled to the source of the third nMOSFET in the by-pass stack.
2. The priority encoder as set forth in claim 1, further comprising:
an output circuit to provide at least one voltage indicative of the leading zero of
a binary word if
the gate voltage of the nMOSFET in the first group is indicative of
the gate voltage of the first nMOSFET in the second group is indicative of ; the gate voltage of the second nMOSFET in the second group is indicative of

D
the gate voltage of the first nMOSFET in the third group is indicative of 6;
the gate voltage of the second nMOSFE in the third group is indicative of
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the gate voltage of the first nMOSFET in the by-pass stack is indicative of the
Boolean expression where • denotes logical AND;
the gate voltage of the second nMOSFET in the by-pass stack is indicative of
the Boolean expressioi . and
the gate voltage of the third nMOSFET in the by-pass stack is indicative of the
Boolean expression
3. The priority encoder as set forth in claim 1, further comprising:
an output circuit to provide at least one voltage indicative of the leading one of a
binary word if
the gate voltage of the nMOSFET in the first group is indicative of
the gate voltage of the first nMOSFET in the second group is indicative of the gate voltage of the second nMOSFET in the second group is indicative of
the gate voltage of the first nMOSFET in the third group is indicative of
the gate voltage of the second nMOSFET in the third group is indicative of ' the gate voltage of the first nMOSFET in the by-pass stack is indicative of the
Boolean expression where • denotes logical AND;
the gate voltage of the second nMOSFET in the by-pass stack is indicative of
the Boolean expression ; and
the gate voltage of the third nMOSFET in the by-pass stack is indicative of the
Boolean expression
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4. The priority encoder as set forth in claim 1, further comprising:
at least one clocked transistor to charge the drains of all said nMOSFETs to HIGH if a clock signal is in a first state, wherein, based upon gate voltages of all said nMOSFETs, a subset of the drains of all said nMOSFETs is discharged to LOW if the clock signal is in a second state complementary to the First state.
5. The priority encoder as set forth in claim 4, further comprising:
an output circuit to provide at least one voltage indicative of the leading zero of
a binary word if
the clock signal is in the second state;
the gate voltage of the nMOSFET in the first group is indicative of '
the gate voltage of the first nMOSFET in the second group is indicative of the gate voltage of the second nMOSFET in the second group is indicative of
the gate voltage of the first nMOSFET in the third group is indicative of
the gate voltage of the second nMOSFET in the third group is indicative of the gate voltage of the first nMOSFET in the by-pass stack is indicative of the
Boolean expression where • denotes logical AND;
the gate voltage of the second nMOSFET in the by-pass stack is indicative of
the Boolean expression ind
the gate voltage of the third nMOSFET in the by-pass stack is indicative of the
Boolean expression
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6. The priority encoder as set forth in claim 4, further comprising:
an output circuit to provide at least one voltage indicative of the leading one of a
binary word if
the clock signal is in the second state;
the gate voltage of the nMOSFET in the first group is indicative of
the gate voltage of the first nMOSFET in the second group is indicative of the gate voltage of the second nMOSFET in the second group is indicative of
^
the gate voltage of the first nMOSFET in the third group is indicative of
the gate voltage of the second nMOSFET in the third group is indicative of ; the gate voltage of the first nMOSFET in the by-pass stack is indicative of the
Boolean expression /here • denotes logical AND;
the gate voltage of the second nMOSFET in the by-pass stack is indicative of
the Boolean expression and
the gate voltage of the third nMOSFET in the by-pass stack is indicative of the
Boolean expression
7. A priority encoder comprising:
a set )f A'+l nodes;
a by-pass stack of serially connected K+1 IGFETs ; and


a broken stack of [GFETs, the broken stack comprising K+l groups
of serially connected IGFETs, each group comprising serially connected IGFETs
wherein the integer sc. and A' arc such that:

wherein for each , the drain of IGFET is
connected to node where , where is the z'th clement (counting
from zero, left to right) of the ordered set of integers

where ^• ■ k = °' '•"" K + ', arc such that

wherein for each , the drain of IGFET is connected to node
, and the source of IGFET is connected to the source of IGFET

8. The priority encoder as set forth in claim 7, wherein the integer set / minimizes a cost function.
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9. The priority encoder as set forth in claim 8, wherein the cost function is

10. The priority encoder as set forth in claim 7, further comprising:
an output circuit to provide at least one voltage indicative of the leading zero of
a binary N+1 bit word if
for each , the gate voltage of nMOSFET

for each , the gate voltage of nMOSFET is indicative of
where

where product denotes logical AND.
11. The priority encoder as set forth in claim 7, further comprising:
an output circuit to provide at least one voltage indicative of the leading one of a
binary N+\ bit word '5* 5"-' '" BQ> if
for each , the gate voltage of nMOSFET
is indicative of
for each , the gate voltage of nMOSFET is indicative of
where
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where product denotes logical AND.
12. The priority encoder as set forth in claim 7, further comprising:
N output circuits each having a first input having voltage
and a second input having voltage each output circuit having its first
input connected to node and its second input connected to node ;o provide an
output voltage indicative of where • denotes logical AND and the over-
bar denotes logical complement.
13. The priority encoder as set forth in claim 12, wherein the integer set / minimizes a cost function.
14. The priority encoder as set forth in claim 13, wherein the cost function is
\(K+[). {#it.Jt=0,l,.••*:},
C(/) = max r .
{(nL-i + K~k),i= 12,■■■(>h -1); k =0,1,—K)
15. A priority encoder comprising:
a set \No'Ni'"'N"SofN+\ nodes; K+\ transistors H[k]' k~0A,— K: and
groups of transistors, each group comprising
transistors
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wherein the integer set nd K are such that:


wherein for each the transistor * ^ is
coupled to node to pull down node LOW if transistors
arc ON, where the latter set is null if is the ith element
(counting from zero, left to right) of the ordered set of integers

where , arc such that

wherein for each , the transistoris coupled to node
to pull down node LOW if transistors- arc ON.
16. The priority encoder as set forth in claim 15, wherein the integer set / minimizes a cost function.
17. The priority encoder as set forth in claim 16, wherein the cost function is
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18. The priority encoder as set forth in claim 15, further comprising:


and a second input having voltage . each output circuit having its first
input coupled to node ■ and its second input coupled to node •"*' to provide an
output voltage indicative of where • denotes logical AND and the over-
bar denotes logical complement.
19. The priority encoder as set forth in claim 18, wherein the integer set / minimizes a cost function.
20. The priority encoder as set forth in claim 19, wherein the cost function is

21. The priority encoder as set forth in claim 15, further comprising:
an output circuit to provide at least one voltage indicative of the leading zero of
a binary MM bit word
for each ' '"' *"'' ' = l»-••"("* ~ 1)j transistor *^ is responsive
l0Bnu).
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for each transistor is responsive of . vhere

where product denotes logical AND.
22. The priority encoder as set forth in claim 15, further comprising:
an output circuit to provide at least one voltage indicative of the leading one of a
binary bit word if
for each , transistor is responsive
of
for each is responsive of ', where

where product denotes logical AND.
23. The priority encoder as set forth in claim 21. wherein the integer set / minimizes
a cost function, where the cost function is

24. The priority encoder as set forth in claim 22, wherein the integer set / minimizes
a cost function, where the cost function is

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25. The priority encoder as set forth in claim 15, further comprising:
at least one clocked transistor to pull up all nodes in the set
HIGH if a clock signal is in a first state, wherein, the transistors
and re coupled to the nodes to pull a subset of
the nodes LOW based upon which of the transistors , and
, are ON if the clock signal is in a second state complementary to the first state.
26. The priority encoder as set forth in claim 15, further comprising:
for each ' ~ ' ''" , at least one transistor coupled to node • to pull up node HIGH if and only if transistors , and
, are such as to not pull down node LOW.
27. A priority encoder to provide at least one voltage indicative of the leading zero
or one of a binary word the priority encoder comprising:
a by-pass stack of transistors to provide at least one voltage indicative of the
logical AND of at least one subset of the Boolean values and
a broken stack of transistors to provide at least voltage indicative of the logical
AND of at least one proper subset of the Boolean values
28. A priority encoder comprising:
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a by-pass stack comprising first, second, and third nMOSFETs; a broken stack of nMOSFETs comprising first, second, and third groups, wherein:
the first group comprises an nMOSFET having a source connected to the source of the first nMOSFET in the by-pass stack;
the second group comprises first and second nMOSFETs serially connected to each other, where the second nMOSFET in the second group has a source connected to the source of the second nMOSFET in the by-pass stack; and
the third group comprises first and second nMOSFETs serially connected to each other, where the second nMOSFET in the third group has a source connected to the source of the third nMOSFET in the by-pass stack.
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