The present invention relates to Calibration of analog signals which are being
digitized by analog to digital convertor. The invention provides the capability to
address the tolerance of electronic equipments and a more accurate value of
the signal is obtained.
BACKGROUND OF THE INVENTION
The analog input to ADC gives digitized value of the signal. The accuracy is
subjected to the gain and offset errors from ADC and other electronics
components in the signal chain. These errors must be compensated to get the
output in the required range .The correction factors were calculated manually
for every single unit by noting the values from the recorder corresponding to
the voltage values sent to recorder and then plotting the graph. This can be
implemented by applying the correction factors.
In the present invention, the Analog module based on 12‐bit ADC has provision
of 16 analog inputs. Multiplexers are provided for selecting the analog inputs
to be converted to digital for processing. The channel selection logic is
programmable. This module is interfaced with the CPU external bus.
All analog inputs are fed through signal conditioning circuits and suitable
scaled in hardware in the range of ‐10 Volt to +10 Volt. If a signal of ‐10 Volt is
fed to ADC, the digitized value would be 0x000 (minimum), while a signal of
+10V fed to ADC would result in a digitized value of 0xFFF (maximum).
This present invention is concerned with the calibration of the digitized value
of the analog signals to be recorded in the flight data recorder.
Summary of present invention
In accordance with one aspect of present invention, is to provide for the
correction factors gain and offset for the 16 analog channels.
ANNEXURE II
In accordance with second aspect of the present invention, is to provide for
accurate value of the digitized data for more precise and accurate analysis of
aircraft parameters.
In accordance with another aspect of the present invention, is to provide for
re‐configurable calibration capability.
In order to address inherent tolerance in the electronic components, used for
scaling the analog inputs, certain correction factors are to be applied in reconfigurable
manner, after the signal is digitized.
The configuration data, which is used for performing the required corrections
are predefined and stored in an Serial EPROM, located on the analog Input
module.
BRIEF DESCRIPTION OF THE DRAWINGS
The features of the present invention will become more apparent and descriptive
when considered together with figure1.
Figure 1 is an interface between the flight data recorder and the test rig which
communicate among each other.
Figure 2 describes format of calibration for single data to be stored in the serial
EPROM.
DETAILED DESCRIPTION
Refering to figure 1, the flow for calculating the gain and offset is as follows:
1. Switch On the SSFDR Power Supply.
2. For each of the 16 analog parameters, the range is divided into 15 part.
3. The test rig sends query to SSFDR for each of the 15 divided values of
respective analog signal.
4. SSFDR returns the value to test rig corresponding to the set value of the
analog signal in the test rig.
5. The test rig compares the set value and the corresponding readback value
of the analog signal for all the 15 values in the range of the analog signal.
6. The test rig then calculates the gain and offset for that particular analog
channel.
7. Similarly, it calculates the gain and offset of the remaining analog Channels.
8. This gain and offset will be written in file and finally this file will be sent to
EEPROM through RS232.
9. Switch off the SSFDR.
ANNEXURE II
The Analog input module comprises of sixteen (16) channels . Scaling data is
available separately for each channel individually. Each channel requires the
following parameters:
‐ Offset (C)(Signed Integer)
‐ Gain (Multiplication factor ‐ M)
‐ Gain (Division factor ‐ D)
Ideally, if there is no tolerance or error in the electronic components, then M
would be 1, D would be 1 and C would be zero. This result in the corrected
RAW value to be exactly the same as the RAW value read from the ADC. If gain
needs to be applied to a certain input, then M would be greater than D, while
if the signal needs to be attenuated, then M would be less than D.
For each channel, the values of the parameters – M, D and C – are stored on
the serial EPROM.
Following points should be considered for the gain and offset values and the
resultant corrected value of the channel:
1. If the result of the corrected RAW value is negative, result is set to lowest
value of the channel.
2. If the result of the corrected RAW value is positive, result is set to greatest
value of the channel.
3. The offset factor 'C' may be positive or negative. If the most significant bit in
the MSB byte is '0', 'C' is to be considered as positive value, while if it is '1',
'C' is to be considered as negative value. For the purpose of the magnitude
or absolute value, consider only LS 15‐bits.
4. If the offset validity byte indicates 0, there is no need to perform the offset
part of the operation. Similarly, if the gain validity byte indicates 0, there is
no need to perform the gain part of the operation
5. Care must be exercised to verify for non‐zero value of 'D', before
ANNEXURE II
computation.
6. To avoid floating point calculations Multiplication and Division factor are
provided to get the required slope (actual gain).

WE CLIAMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved.

We Claim that:

1. The said system comprising
- A computing device capable of interfacing with a customised hardware,
- An hardware with atleast one interface for generation of analog signal,
- A processing embedded unit capable of taking generated analog signal and convert it into digital value &
- Looms and cable to connect each other.
2. According to claim 1, the system is capable of generation of atleast 16 analog signals in the range of -10V to +10V.
3. According to claim 1, the system is capable of receiving the digital value equivalent to analog signals as generated.
4. According to claim 1, the system is capable of running calibration logic to improve the accuracy of atleast one converted signal.
5. According to claim 1, the system is capable of uploading the results generated from calibration logic into the memory of processing embedded unit for future use without disturbing its configuration.
6. According to claim 1, the calibration logic addresses the inherent tolerance of electronic components and thus allows use of comparatively low tolerance components thereby reducing the cost of system.
7. According to claim 1, the calibration logic holds good for all the data acquisition system with atleast one analog signal. ,TagSPECI:As per Annexure-II