THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE NATURE OF THE INVENTION

CHARGE PUMP USING REVERSE BATTERY PROTECTED MOSFET SWITCHES

A) TECHNICAL FIELD

[0001] The present invention generally relates to a switching power supply and particularly to charge pump used for supplying power to portable battery operated appliances like cell phones, portable radios and playback units, personal digital assistants, etc. The present invention more particularly relates to a protection circuit for battery power supply and to prevent reverse current flow into the power supply.

B) BACKGROUND OF THE INVENTION

[0002] The battery operated appliances have proliferated throughout the world. Cell phone handsets, portable radios and playback units, personal digital assistants provide only a few of the many examples of such appliances These portable devices are generally powered by a battery which maybe rechargeable, such as nickel-Cadmium and Lithium Ion. All of these batteries loose their charge overtime, and consequently do not produce a single, constant output voltage. Usually, a DC-DC converter is used to regulate the various driving voltages for different loads. Sometimes, boosted forms of input voltage are read to drive loads. This is achieved by using an inductive DC-DC converter or a charge pump.

[0003] The switching power supply such as a charge pump, comprises of switching circuit, around a set of capacitors and is connected in series between a power source such as a battery and a load. The switching circuit is a network of switches and charge storage capacitors also known in the art as bucket caps or flying caps. The switches of these switching circuits are controlled in such a manner so as to successively charge and discharge the capacitors to provide a buck or boosted output voltage. Moreover, in a battery driven application, the battery voltage continues to drop when the load is active, which may necessitate the switching between different modes so as to regulate output voltage or output current for the load.

[0004] There could be several modes of buck or boost operation to provide different ratios of input and output voltages such as Ix, 2x, 3x. These could be fractional ratios such as 1.33x, 1.5x, 1.66x as well. Several buck modes could include l/2x, l/3x, 2/3x and so on. Such similar circuits are also known DC-DC converters.

[0005] There are several embodiments of the inherent switching circuit. Generally the switching circuit comprises of one or more charge storage capacitors and output capacitors which are mounted off chip.

[0006] The various switches of the Switching Circuit can be selectively actuated to configure charge storage capacitors in differential configurations or circuit topologies with respect to the input (Vin) and output voltages (Vout) to get various forms of buck and boosted output voltages with respect to the input voltage.

[0007] These various configurations will be described as related to "modes and phases". The term modes refer to a set of configuration that together produce a fixed gain or ratio of output to input voltage. In each of these buck or boost modes, the capacitors are alternately charged by the input voltage and discharged to the output load. These repetitive switched configurations within a mode are referred to as phases.

[0008] In a battery driven application the battery voltage continues to drop when the load is active, which may necessitate the switching between different modes so as to regulate output voltage or output current for the load.

[0009] Switches control mode of the charge pump. However, in any given mode, reverse bias condition across the switches could occur during certain phases, leading to the damage of the battery. The reverse bias condition arises, when one of the charge storage capacitor is charged to a voltage level higher than input voltage source Vin (2xVin in 2x mode) and is being isolated from a lower input voltage source (Vin in this exemplary case). The parasitic diodes turn ON and conduct large current into the input voltage source.

[0010] This current without any form of reverse current protection can potentially damage the battery and lead to the occurrence of a latch up condition. Most importantly the reverse current flow into the battery will pull down the output voltage of the charge pump to a value much lower than the one the switch configurations in a given mode intend to.

[0011] Such a reverse current occurs through switch because of non-proper bias voltages on the Gate and Bulk of MOSFET configured as a switch in a charge pump.

[0012] Generally the gate and bulk are driven through some processing circuits which include blocks like comparators and level shifters to avoid reverse bias condition. Sometimes the bulk of all the PMOS switches are shorted to the output of charge pump since it is the highest potential in the circuit. Sometimes the diodes or parasitic BJT's are also used in series with the switches to avoid reverse flow of currents. However such circuits consume a lot of voltage headroom and are not ideal for low voltage applications. Bulk tie up could lead to latch up of switches during the startup of charge pump. Each of these prior forms of art has inherent issues to deal with and most often the pre-processing blocks could turn out larger and more significant than the charge pump itself

[0013] Thus none of the presently available devices provides a simple but effective circuit to provide the proper bias voltages on the gate and bulk terminals of a MOSFET switch to provide a desired output voltage in a given boost mode.

[0014] Hence there is a need to develop a system and method to provide the proper bias voltages on the gate and bulk terminals of a MOSFET switch so as to allow the output voltage at the charge pump to reach the value which the switch configuration of a given boost mode intends to.

C) OBJECTS OF THE INVENTION

[0015] The primary object of the present invention is to develop a system and method to provide proper bias voltages on the gate and bulk terminals of a MOSFET switch to acquire a desired output voltage at the charge pump in a given boost mode.

[0016] Another object of the present invention is to develop a system and method to provide a reverse battery protection to the DC power supply or to a power source in a charge pump using a simple logic switch circuit.

[0017] Yet another object of the present invention is to develop a system and method to provide a reverse battery protection to the DC power supply or to a power source in a charge pump to prevent damage to the battery.

[0018] Yet another object of the present invention is to develop a system and method to provide a reverse battery protection to the DC power supply or to a power source in a charge pump to prevent the latch up condition.

[0019] Yet another object of the present invention is to develop a system and method to provide a phase controlled switch logic to configure the gate and bulk drive voltages of a switch to avoid reverse bias conditions.

[0020] Yet another object of the present invention is to develop a system and method to provide a reverse battery protection using a phase controlled switch logic thereby eliminating the need for a pre-processing circuit.

[0021] Yet another object of the present invention is to develop a system provided with a logic switch circuit to achieve complete isolation and to prevent reverse current flow to the battery thereby preventing the damage to the battery and to the MOSFET.
[0022] Yet another object of the present invention is to develop a system provided with a simple logic switch circuit to systematically control the switches of a charge pump so as to achieve a boosted mode voltage.

[0023] Yet another object of the present invention is to develop a system provided with a simple logic circuit which can be designed easily without much effort to provide a reverse battery protection to the DC power supply or to a power source in a charge pump.

[0024] Yet another object of the present invention is to develop a system and method to provide a reverse battery protection for MOS IC in automotives and high voltage IC drivers.

[0025] Yet another object of the present invention is to develop a system provided with logic switch circuit to prevent the latch up of the switches during the start up of charge pump.

[0026] These and other objects and advantages of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings.

D) SUMMARY OF THE INVENTION

[0027] The above mentioned shortcomings, disadvantages and problems are addressed herein and which will be understood by reading and studying the following specification.

[0028] The various embodiments of the present invention provide a system and method to provide a reverse battery protection to a power supply in a charge pump to avoid the reverse flow of current in a power source to avoid damage to the battery and to achieve desired output voltage from the power source in a given power mode. According to one embodiment an intelligent logic provides the necessary gate and bulk drive voltages to the switches of a charge pump so that the reverse bias condition can be avoided for proper operation of the charge pump. The system is provided with an intelligent logic switch circuit to provide the necessary and sufficient gate and bulk voltages. To achieve complete isolation and avoid reverse current to the battery and subsequently avoid damage to the MOSFET or latch up occurrence, an intelligent logic switch configuration is presented.

[0029] According to one embodiment of the present invention, a charge pump circuit with reverse battery protection comprises a first switch and a second switch that are connected through a capacitor usually called bucket or flying capacitor. A third switch connects the input power supply to both the flying capacitor and the second switch. A fourth switch connects the flying capacitor to the output capacitor. The output capacitor holds the boosted output voltage. A logic switch circuit each is connected to both the first switch and the fourth switch to provide the necessary gate and bulk drive voltages to prevent the reverse bias condition. Each switch is a MOSFET switch. Each logic switch circuit is connected to both the gate and to the bulk of the first switch and the fourth switch to provide necessary gate and bulk drive voltages to prevent reverse bias condition.

[0030] These and other objects and advantages of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings.

E) BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The other objects, features and advantages will occur to those skilled in the art from the following description of the preferred embodiment and the accompanying drawings in which:

[0032] FIGURE. 1 shows a block circuit diagram of a charge pump in 2x mode, according to one embodiment of the present invention.

[0033] FIG. 2 shows the block circuit diagram of a charge pump in phase O of the 2x mode, according to one embodiment of the present invention.

[0034] FIG. 3 is a cross sectional view of the PMOS switch used in charge pump according to one embodiment of the present invention.

[0035] FIG. 4 shows the parasitic diodes of the PMOS switch with its bulk tied to the potential at source, in a charge pump according to one embodiment of the present invention.

[0036] FIG. 5 is a simplified block diagram of PMOS switch of FIG. 4 showing the parasitic diode between drain and source which causes the reverse current to flow into the battery.

[0037] FIG. 6 shows the block circuit diagram of a charge pump in phase 0 of the 2x mode, according to one embodiment of this present invention.

[0038] FIG. 7 shows the PMOS switch with appropriate potential on gate and bulk terminals, used in a charge pump according to one embodiment of the present invention, to avoid reverse current flow.

[0039] FIG. 8 shows a block circuit diagram of a switch logic for a PMOS switch in a charge pump according to one embodiment of the present invention, to achieve the required gate and bulk drive voltages on a PMOS switch in a 2x mode of the charge pump to avoid reverse current.

[0040] FIG. 9 shows a block circuit diagram of a logic switch circuit for one PMOS switch in a charge pump according to one embodiment of the present invention, used to drive the bulk terminal to the highest potential in the circuit during both phases of the clock in a 2x exemplary mode.

[0041] FIG. 10 shows the block circuit diagram of an additional circuit for a PMOS switch in a charge pump according to one embodiment of the present invention, to drive the bulk terminal to the highest potential in the circuit during both phases of the clock in a 2x exemplary mode.

[0042] FIG. 11 shows the block circuit diagram of an additional circuit for a PMOS switch in a charge pump according to one embodiment of the present invention, to drive the bulk terminal to the highest potential in the circuit during both phases of the clock in a 2x exemplary mode.

[0043] FIG. 12 shows the block circuit diagram of a logic switch circuit for a PMOS switch in a charge pump according to one embodiment of the present invention, to avoid reverse bias condition and to avoid the current leakage path in a charge pump circuit during both phases of the clock in a 2x exemplary mode.

[0044] FIG. 13 shows a block circuit diagram of the complete logic switch circuit for one PMOS switch (SW 1) in a charge pump, according to one embodiment of the present invention, to avoid reverse bias condition, when the PMOS switch is used in 2x mode.

[0045] FIG. 14 is a cross sectional view of the NMOS switch used in a charge pump, according to one embodiment of the present invention.

[0046] FIG. 15 shows a block circuit diagram of the logic switch circuit for another PMOS switch (SW 4) in a charge pump, according to one embodiment of the present invention, to avoid reverse bias condition, when the PMOS switch is used in 2x mode.

[0047] FIG. 16 shows a complete block circuit diagram of a charge pump with logic switch circuit in 2x mode, according to one embodiment of the present invention to prevent reverse bias condition.

[0048] Although specific features of the present invention are shown in some drawings and not in others. This is done for convenience only as each feature may be combined with any or all of the other features in accordance with the present invention.

F) DETAILED DESCRIPTION OF THE INVENTION

[0049] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which the specific embodiments that may be practiced is shown by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments and it is to be understood that the logical, mechanical and other changes may be made without departing from the scope of the embodiments. The following detailed description is therefore not to be taken in a limiting sense.

[0050] The various embodiments of the present invention provide a system and method to provide a reverse battery protection to a power supply in a charge pump thereby avoiding the reverse flow of current into a power source to avoid the damage to the battery and to achieve desired output voltage from the power source in a given boost mode. According to one embodiment an intelligent logic provides the necessary gate and bulk drive voltages to the switches of a charge pump so that the reverse bias condition can be avoided for proper operation of the charge pump. The system is provided with an intelligent logic switch circuit to provide the necessary and sufficient gate and bulk voltages. To achieve complete isolation and avoid reverse current to the battery and subsequently avoid damage to the MOSFET or latch up occurrence, an intelligent logic switch configurations is presented.

[0051] According to one embodiment of the present invention, a charge pump circuit with reverse battery protection comprises a first switch and a second switch that are connected through a capacitor usually known as bucket or flying capacitor. A third switch connects the input power supply to both the flying capacitor and the second switch. A fourth switch connects the bucket capacitor to the output capacitor. The output capacitor holds the boosted output voltage. A logic switch circuit each is connected to both the first switch and the fourth switch to provide the necessary gate and bulk drive voltages to prevent the reverse bias condition. Each switch is a MOSFET switch. Each logic switch circuit is connected to both the gate and to the bulk of the first switch to provide necessary gate and bulk drive voltages to prevent reverse bias condition. A logic circuit is connected to both the gate and to the bulk of the fourth switch to provide the necessary gate and bulk drive voltages to prevent reverse bias condition, to avoid damage to the battery and to prevent the latch up condition to provide the proper operation of the charge pump.

[0052] Each logic circuit has two switches SW13 and SW14 connected between the source and the drain of the switch SW1. The bulk and the source of the switch SW 13 are connected respectively to the bulk and the source of the switch SW 14 to drive the bulk terminal of the switch SW1 to the highest potential. The bulk of the switch SW1 is connected in common to the bulks and the sources of the switches SW 13 and switch SW14. A switch SW1 5 is connected between the bulk of the switch SW1 and the gate of the switch SW13 so that the source of the switch SW 15 is connected to the gate of the switch SW13, while the bulk and the drain of the switch SW15 are connected to the source of the switches SW 13 and SW 14. An additional switch SW 16 is connected to the gate of the switch SW 13 so that the drain of the switch SW 16 is connected to the gate of the switch SW 13.

[0053] A pair of two interconnected N MOSFET and P MOSFET switches are connected to the gate of the switch SW 15, while another pair of two interconnected N MOSFET and P MOSFET switches are connected to the gate of the switch SW 14. Each pair of interconnected switches has their gates connected to each other. The drain of one switch in the pair is connected to the source of another switch. The bulk is connected to the source and Vss in one of the two interconnected switches, while the bulk is connected to the drain and to Vin in the other switch.

[0054] According to a preferred embodiment of the present invention, a charge pump operating in 2x mode with Clock (O) and Clock-bar (0) phases is explained in detail below. However it should be understood that the various modes (Boost) or phases experience the similar issues discussed in the 2x mode and therefore the solution presented in the preferred embodiment of the present invention may be employed for all modes (buck^oost) and their phase configurations.

[0055] While the preferred embodiment of the present invention is described here in with respect to a particular mode (2x), it will be apparent to anyone skilled ordinarily in this art, that the invention is applicable to all modes of a charge pump.

[0056] FIGURE. 1 shows a block circuit diagram of a charge pump operating in 2x mode, according to one embodiment of the present invention. With respect to the FIG. 1, the switches SW1 and SW2 are closed forming a path, during the phase O, to charge the top plate of capacitor Cfiy to input voltage Vin. During the phase 0, SW3 and SW4 are closed to pull the top plate of Cfiy from Vin to 2x Vin, thereby providing a doubled input voltage at the output of the charge pump. With respect to FIG. 1, switches may be formed by MOSFET's or similar structures on Integrated circuits. These switches are either PMOS or NMOS FET's in particular with the voltage on their gate being the switch control signal.

[0057] The FET's are fiarther sized large to have minimal voltage drop during forward and normal operation of the switch. Hence they generally have a capacity to conduct large currents through them.

[0058] The FIGURE. 2 shows the block circuit diagram of a charge pump in phase O of the 2x mode, according to one embodiment of the present invention. With respect to FIG.2, the switches SW1-SW4 are formed by MOSFET's. During the phase O of operation, the top plate of capacitor Cfiy is at voltage Vin. During this phase, the switches SW3 and SW4 are switched off by applying a voltage equal to Vin at their gate terminal. During the 0 phase of operation, the bottom plate of the capacitor Cfiy is charged to Vin through the SW3 (as shown in FIG. 6). During this phase the switch SW2 is turned off.

[0059] The voltage at the top plate of the capacitor (Cfly), V jop is at 2xVin. The switch Sw4 is in conduction mode connecting the capacitor Cout to Cny and charges the output voltage to 2xVin over the subsequent clock cycles. However, this is possible only when the switch SW1 completely isolates the node Vtop from input voltage source Vin.
[0060] The FIGURE. 3 is a cross sectional view of the PMOS switch used in charge pump according to one embodiment of the present invention. With respect to FIG.3, the terminals source (S), drain (D), Gate (G), and Bulk (B), of the PMOS switch are connected to respective voltage as in phase 0 of 2x mode. Although the bias voltage Vgs = 0, the drain of the switch Swl is at 2xVin, leading to a Reverse Bias condition at the input voltage node.

[0061] The reverse bias condition arises when one of the charge storage capacitor is charged to a voltage level higher than input voltage source Vin (2xVin in this exemplary case) and is being isolated from a lower input voltage source (Vin in this exemplary case). The parasitic diodes turn ON and conduct large current into the input voltage source. This conduction of current will happen until the charge pump output Vout reaches Vin + Vbamer where Vban-ier is the forward drop of the parasitic diode existing in the cross section of switch SW1. Hence the output of charge pump will be boosted to just Vin + Vbamer instead of the intended doubling of input voltage.

[0062] There are three parasitic diodes namely the DSB (between source & bulk), DNP (between N-well & P-substrate) and DDB (between drain and bulk). In any practical FET device, the bulk and the source are generally shorted eliminating the diode DSB forming any reverse current path. P-substrate is kept at lowest voltage potential available (Vss), thus reverse biasing the diode DNP irrespective of the voltage level of N-well. However the diode DDB connects the drain and the source of the switch SW1 (as shown in FIG. 5).

[0063] This parasitic diode between the drain and the source would allow current to flow from the Vtop node (which is at a potential 2xVin) to the input voltage source Vin
whenever Vtop>Vin + Vbamer-

[0064] Though the switch SW1 is off during the phase 0, as its Vgs<|Vthp|, the diode DDB conducts large currents from charge pump to input voltage source Vin. This current without any form of reverse current protection can potentially damage the battery, lead to latch up condition and damage metal wires incase of large current. Most importantly, the reverse current flow into the battery will pull down the output voltage of the charge pump to Vjn + Vbamer instead of the intended 2xVin.

[0065] Going from the above discussion, it is clear that the reverse bias condition across the switches of a charge pump will not double the input voltage at the output as the circuit configuration intends to. It instead latches the output voltage at the charge
pump to Vin + Vbamer-

[0066] The necessary and sufficient conditions of avoiding the occurrence of reverse bias condition across a switch of a charge pump are defined below separately for 2 voltage conditions. The first condition is that the Voltage at the drain of a P MOSFET Switch VD is less than the voltage at its source Vs. Under this condition, when the Vgs < 0, the switch is completely turned OFF to perfectly isolate the drain voltage from the source. Hence, it may be stated that the necessary condition for the complete isolation of voltage across the PMOS switch is Vgs < 0, when VD < Vs.

[0067] The second condition is that Voltage at the drain of a P MOSFET Switch VD is greater than the voltage at the source Vs. When the drain voltage is greater than source voltage, then the bulk of the PMOS switch should not be tied to its source. This is concluded so as to avoid a direct path from the drain to source through diode DDB (as shown the FIG. 5).

[0068] Hence it is apparent that the bulk should be tied to the drain voltage which is the higher of the two voltages (VD and VS). In such a case, drain and source swap each other's role. It is just not sufficient to keep Vso <= 0. It is also essential to keep voltage between drain and gate of a PMOS (VDG) equal to zero as well.

[0069] Therefore the necessary and sufficient condition for the PMOS switch to perfectly isolate drain and source voltages during its switched OFF condition is that VDG < 0 and VGS < 0 along with the bulk being tied to potential at the drain, when VD > Vs (called Equation A).

[0070] Hence an intelligent logic switch circuit is formed to provide the necessary gate and bulk drive voltages to the switches of a charge pump to prevent the reverse bias condition to ensure the proper operation of the charge pump. The intelligent logic switch circuit is formed to provide the necessary and sufficient gate and bulk voltages as required by the Equation A.

[0071] There could be several embodiments which confine to the above mentioned equations for driving gate and bulk of the switches of a charge pump which are well within the scope of art or invention.

[0072] The FIGURE. 4 shows the parasitic diodes of the PMOS switch with its bulk tied to the potential at source, in a charge pump according to one embodiment of the present invention. With respect to the FIG.4, the bulk and the source are generally shorted eliminating the diode DSB forming any reverse current path, in any practical FET device. P-substrate is kept at lowest voltage potential available (Vss), thus reverse biasing the diode DNP irrespective of the voltage level of N-well. However the diode DDB connects the drain and the source of the switch SW1.

[0073] The FIGURE. 5 is a simplified block diagram of PMOS switch of FIG. 4 showing the parasitic diode between drain and source which causes the reverse current to flow into the battery. With respect to the FIG.5, the diode DDB connects the drain and the source of the switch SW1. This parasitic diode between the drain and the source would allow current to flow from the Vtop node (which is at a potential 2xVin) to the input voltage source Vin whenever Vtop>Vin + Vban-ier.

[0074] Though the switch is off as its Vgs<|Vthp|, the diode DDB conducts large currents from charge pump to input voltage source Vin. This current without any form of reverse current protection can potentially damage the battery, lead to latch up condition and damage metal wires incase of large current. Most importantly, the reverse current flow into the battery will pull down the output voltage of the charge pump to Vin + Vbarrier iustcad of thc intended 2xVin.

[0075] Thus it is clear that the reverse bias condition across the switches of a charge pump will not double the input voltage at the output as the circuit configuration intends to. It instead latches the output voltage at the charge pump to Vjn + Vbamer-
[0076] The necessary and sufficient conditions of avoiding the occurrence of reverse bias condition across a switch of a charge pump are defined below separately for 2 voltage conditions. The first condition is that the Voltage at the drain of a P MOSFET Switch VD is less than the voltage at its source Vs. Under this condition, when the Vgs < 0, the switch is completely turned OFF to perfectly isolate the drain voltage from the source. Hence, it may be stated that the necessary condition for the complete isolation of voltage across the PMOS switch is Vgs < 0, when VD < Vs.

[0077] The second condition is that Voltage at the drain of a P MOSFET Switch VD is greater than the voltage at the source Vs. When the drain voltage is greater than source voltage, then the bulk of the PMOS switch should not be tied to its source. This is concluded so as to avoid a direct path from the drain to source through diode DDB (as shown the FIG. 5).

[0078] Hence it is apparent that the bulk should be tied to the drain voltage which is the higher of the two voltages (VD and VS). In such a case, drain and source swap each other's role. It is just not sufficient to keep VSG <= 0. It is also essential to keep voltage between drain and gate of a PMOS (VDG) equal to zero as well.

[0079] Therefore the necessary and sufficient condition for the PMOS switch to perfectly isolate drain and source voltages during its switched OFF condition is that VDG < 0 and VGS < 0 along with the bulk being tied to potential at the drain, when VD > Vs (called Equation A).

[0080] Hence an intelligent logic switch circuit is formed to provide the necessary gate and bulk drive voltages to the switches of a charge pump to prevent the reverse bias condition to ensure the proper operation of the charge pump. The intelligent logic switch circuit is formed to provide the necessary and sufficient gate and bulk voltages as required by the Equation A.

[0081] FIG. 6 shows the block circuit diagram of a charge pump in phase 0 of the 2x mode, according to one embodiment of this present invention, with respect to FIG.6, the bottom plate of the capacitor is charged to Vin through SW3 during the 0 phase of operation. During this phase SW2 is switched off The voltage at the top plate of the capacitor (Cfiy), Vtop is at 2xVin. The switch Sw4 is in conduction mode to connect Com to Cfiy and charges the output voltage to 2xVin over the subsequent clock cycles. However, this is possible only when the switch SW1 completely isolates the node Vtop from the input voltage source Vin.

[0082] The FIGURE. 7 shows the PMOS switch with appropriate potential on gate and bulk terminals, used in a charge pump according to one embodiment of the present invention, to avoid the reverse current flow to the current source. With respect to FIG.7, the gate VG should be at potential VD and the bulk is tied to drain to keep the Vdg <= 0, Since VD > Vs, during 0 phase in the charge pump of 2X mode. One of the logical solutions to drive the gate and bulk is as shown in the FIG. 8.

[0083] FIGURE. 8 shows a block circuit diagram of switch logic for a PMOS switch in a charge pump according to one embodiment of the present invention, to achieve the required gate and bulk drive voltages on a PMOS switch in a 2x mode of the charge pump to avoid reverse current. With respect to FIG.8, a switch SW 11 is connected between the gate of the switch SW1 and Vss, while a switch SW 12 is connected between the gate and the drain of the SW1. a switch SW 13 is connected between the source and the bulk of the switch SW13, while another switch SW 14 is connected between the bulk and the drain of the switch SW1.

[0084] During phase , the switch SW1l drives the gate of the switch SW1 to Vss and thereby completely turning it ON. The bulk of SW1 is kept at Vin through the switch SW13 during this phase.

[0085] During phase 0, the switches SW12 and SW14 tie the gate and bulk of switch SW1 respectively to its own drain, thereby meeting the necessary condition required to avoid reverse bias condition between drain and source of SW1 and thus avoiding the clamping of the output voltage node to Vin + Vbarrier.

[0086] Now, consider the bulk switches SW13 and SW14 connected between source and drain of SW1. One of the practical implementation for switches SW1 3 and SW14 is as shown in the FIG. 9.

[0087] The FIG. 9 shows a block circuit diagram of a logic switch circuit for one PMOS switch in a charge pump according to one embodiment of the present invention, used to drive the bulk terminal to the highest potential in the circuit during both phases of the clock in a 2x exemplary mode. With respect to FIG.9, the bulk and the source of the switch SW 13 are connected respectively to the bulk and the source of the switch SW 14 to drive the bulk terminal to the highest potential. The bulk of the switch SW1 is connected in common to the bulks and the sources of the switches SW 13 and switch SW 14.

[0088] The switch SW13 could again face the problem of Reverse bias condition during phase 0 of the 2X mode. This is because, during the phase 0, the switch SW14 connects both VD and Vbulk to 2xVin. In such a case, SW13 has its gate potential at Vin and source at 2xVin leading to Vsg > |Vthp| thereby leading to a path for reverse current from the output voltage node into the battery.

[0089] Hence to avoid this Vsg and Vdg voltages of switch SW13 should be equal to zero during phase 0. Also, on the other hand, it is required that switch SW13 is completely turned on during phase O.

[0090] One of the logical switch circuit used to achieve this in a charge pump is shown in FIG. 10. The FIG. 10 shows the block circuit diagram of an additional circuit for a PMOS switch in a charge pump according to one embodiment of the present invention, to drive the bulk terminal to the highest potential in the circuit during both phases of the clock in a 2x exemplary mode.

[0091] With respect to the FIG. 10, a switch 15 is connected between the bulk of the switch SW1 and the gate of the switch SW1 3 so that the source of the switch SW 15 is connected to the gate of the switch SW13, while the bulk and the drain of the switch SW15 are connected to the source of the switches SW 13 and SW 14. An additional switch SW 16 is connected to the gate of the switch SW 13 so that the drain of the switch SW 16 is connected to the gate of the switch SW 13.

[0092] During phase Vs). It experiences again a similar condition in that the drain voltage when switch is OFF is higher than the source voltage creating large leakage current paths through the parasitic diode DDB

[0100] Hence applying another exemplary embodiment of the invented logic to switch SW4', reverse current can be avoided from its drain to source. Thus to completely isolate the drain and source the switch SW4' along with it bulk and gate logic is as shown in the following FIG. 15.

[0101] FIG. 16 shows the complete 2x mode charge pump with its reverse bias condition protected switches as per the invention discussion. With respect to FIG. 16, a logic switch circuit respectively is connected to the gate and to the bulk of both the switches SW 1 and SW 4 to provide the necessary gate and bulk drive voltages to avoid the reverse bias condition and to prevent the current leakage path in a charge pump circuit.

[0102] The above explained embodiment is intended to be illustrative and not limiting. Many additional embodiments in accordance with this invention will be apparent to those skilled ordinarily in art. All such additional embodiments driving the gate and the bulk of a switch through logic in accordance with this invention are intended to be within the broad principles of this invention.

[0103] To achieve complete isolation and avoid reverse current to the battery and subsequently avoid damage to the MOSFET or latch up occurrence, an intelligent logic of switch configurations is presented.

[0104] Thus the various embodiments of the present invention provides logic to configure gate and bulk drive voltages of a switch in a way so as to avoid reverse bias conditions. The scope of invention involving power switches of the charge pump could individually be also defined for MOS IC reverse battery protection in several automotives and high voltage IC drivers. The present invention provides the proper bias voltages on the gate and bulk terminals of a MOSFET switch so as to allow the output voltage at the charge pump to reach the value which the switch configuration of a given boost mode intends to.

G) ADVANTAGES OF THE INVENTION

[0105] The present invention doesn't use any pre-processing but instead provides logic to configure gate and bulk drive voltages of a switch in a way so as to avoid reverse bias conditions. A switch logic circuit is connected to the gate and to the bulk of the switch in the charge pump to provide necessary gate and bulk drive voltages to prevent the reverse bias condition to avoid the damage to the battery and to prevent the latch up condition thereby ensuring the proper operation of the charge pump. To achieve complete isolation and avoid reverse current to the battery and subsequently avoid damage to the MOSFET or latch up occurrence, an intelligent logic of switch configurations is presented.

[0106] Instead of using a pre-processing block to generate bulk and gate drive voltages, a simple logic is used to systematically control the switches of a charge pump. The idea of using simple structures such as switch logic is unique to this invention. Unlike the usage of pre-processing blocks to drive gate and bulk voltages, the design of switch logic is easy to understand, debug and control. To add to it, switch logic need not be accurate unlike usage of pre-processing blocks like comparator where significant effort is required to design the preprocessing block itself The invention is applicable to avoid the reverse current through the switches used in inductive DC-DC converter also.

[0107] Although the invention is described with various specific embodiments, it will be obvious for a person skilled in the art to practice the invention with modifications. However, all such modifications are deemed to be within the scope of the claims.
[0108] It is also to be understood that the following claims are intended to cover all of the generic and specific features of the present invention described herein and all the statements of the scope of the invention which as a matter of language might be said to fall there between.

CLAIMS

What is claimed is:

1. A charge pump circuit with reverse battery protection comprising:

a first switch and a second switch connected through a flying capacitor;

a third switch connecting the input power supply to both the flying capacitor
and the second switch;

a fourth switch connecting the flying capacitor to the boosted output voltage;
an output capacitor connected to the fourth switch; and

a logic switch circuit connected to both the first switch and the fourth switch;
wherein each switch is a MOSFET switch and the logic switch circuit is connected to both the first switch and the fourth switch to provide necessary gate and bulk drive voltages to prevent reverse bias condition.

2. The charge pump according to claim 1, wherein each switch is a MOSFET and the logic switch circuit is connected to both the first switch and the fourth switch to provide necessary gate and bulk drive voltages to prevent reverse bias condition thereby allowing the output voltage to reach the value which the switch configuration of a given boost mode intends to.

3. The charge pump according to claim 1, wherein a logic switch circuit drives the gate of the first switch to provide the necessary gate drive voltages to prevent the reverse bias condition thereby avoiding the reverse current flow into the power supply.

4. The charge pump according to claim 1, wherein the logic switch circuit is connected to the bulk of the first switch to provide the necessary bulk drive voltage to avoid the reverse bias condition thereby avoiding the reverse current flow through the parasitic diodes of MOSFET switches.

5. The charge pump according to claim 1, wherein the logic switch circuit is connected to the bulk and coupled to the drain and the source of the first switch to provide the necessary bulk drive voltage to avoid the reverse bias condition thereby avoiding the reverse current flow through the parasitic diodes of MOSFET switches.

6. The charge pump according to claim 1, wherein the logic switch circuit connects the gate and the drain of the first switch together, when the first switch is in 'OFF' phase, to avoid the reverse bias condition thereby avoiding the reverse current flow into the power supply.

7. The charge pump according to claim 1, wherein a logic switch circuit is connected to the gate of the fourth switch to provide the necessary gate drive voltages to prevent the reverse bias condition thereby avoiding the reverse current flow from the output capacitor into the flying capacitor.

8. The charge pump according to claim 1, wherein the logic switch circuit is connected to the bulk of the fourth switch to provide the necessary bulk drive voltage to avoid the reverse bias condition thereby avoiding the reverse current flow through the parasitic diodes of MOSFET switches.

9. The charge pump according to claim 1, wherein the logic switch circuit is
connected to the bulk and coupled to the drain and the source of the fourth
switch to provide the necessary bulk drive voltage to avoid the reverse bas
condition.

10. The charge pump according to claim 1, wherein the logic switch circuit
connects the gate and the drain of the fourth switch together, when the fourth
switch is in 'OFF' phase, to avoid the reverse bias condition thereby avoiding
the reverse current flow into the power supply.