TECHNICAL FIELD
[0001] The present disclosure generally relates to transistors. More specifically, the present disclosure relates to a circuit and a method for operating quasi-floating bulk direct gate driven MOSFET.

BACKGROUND
[0002] Background description includes information that can be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] A transistor is a semiconductor device used to amplify or switch electrical signals and power. Since transistor acts as a basic building block in the field of modern electronics, it has application in various fields. One such application area is in the biomedical devices and applications. In one approach, the biomedical applications such as Electro-encephalography (EEG), Electrocorticography (ECoG) and in-vivo multi-electrode recordings require high-gain and low-noise CMOS Operational Transconductance Amplifier with low power consumption. However, in such approaches, achieving high-gain and low-noise amplification with low-power consumption at low-voltage and low-current levels is challenging issue in CMOS devices. Also, along with high-gain and low-noise performance of the amplifier, it should show negligible dependency on process voltage and temperature variations.
[0004] In another approach, the system or device may include Bulk Driven, Floating Bulk, Quasi-Floating Gate, Bulk Driven Quasi-Floating Gate for Operational Transconductance Amplifier. In such approach, the said device may show low-power consumption but have low-gain and high-noise. However, as biomedical applications indispensably require low-noise operation for high quality recording of associated biomedical signals these techniques are unsuitable. Due to these limitations, these approaches are less reliable and less efficient.
[0005] Therefore, there is a need in the art to provide an improved circuit and method for operating quasi-floating bulk direct gate driven MOSFET.
OBJECTS OF THE PRESENT DISCLOSURE
[0006] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below:
[0007] It is an object of the present disclosure to provide high-gain MOS operational transconductance amplifier;
[0008] It is another object of the present disclosure to provide low-noise MOS operational transconductance amplifier;
[0009] It is yet another object of the present disclosure to provide very small impact of process voltage and temperature variations;
[00010] It is yet another object of the present disclosure to provide Low-voltage and low-current operation.

SUMMARY
[00011] The present disclosure relates to transistors. More specifically, the present disclosure relates to a circuit and a method for operating quasi-floating bulk direct gate driven MOSFET.
[00012] This summary is provided to introduce simplified concepts of a system for time bound availability check of an entity, which are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended for use in determining/limiting the scope of the claimed subject matter.
[00013] An aspect of this present disclosure pertains to a circuit to operate a metal oxide semiconductor field effect transistor. The circuit includes a first sub-circuit corresponding to operate as a first resistor including a first direct current (DC) bias voltage source, a second direct current (DC) bias voltage source, a first metal oxide semiconductor (MOS) device, a second metal oxide semiconductor (MOS) device, a third metal oxide semiconductor (MOS) device, a first capacitor and a second capacitor. The circuit also includes a second sub-circuit corresponding to operate as a second resistor including a third direct current (DC) bias voltage source, a fourth direct current (DC) bias voltage source, a fourth metal oxide semiconductor (MOS) device, a fifth metal oxide semiconductor (MOS) device, a sixth metal oxide semiconductor (MOS) device, a third capacitor and a fourth capacitor. The circuit further includes a third sub circuit including a seventh primary MOS device, a seventh secondary MOS device, an eighth primary MOS device, an eighth secondary MOS device, a ninth first-primary MOS device, a ninth second-primary MOS device, a ninth first-secondary MOS device, a ninth second-secondary MOS device, a tenth primary MOS device and a tenth secondary MOS device.
[00014] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[00015] The diagrams are for illustration only, which thus is not a limitation of the present disclosure, and wherein:
[00016] FIG. 1 illustrates a schematic representation of a circuit to operate a metal oxide semiconductor field effect transistor (MOSFET) in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[00017] In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
[00018] If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[00019] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[00020] Embodiments of the present invention may be provided as a computer program product, which may include a machine-readable storage medium tangibly embodying thereon instructions, which may be used to program a computer (or other electronic devices) to perform a process.
[00021] The present disclosure relates to transistors. More specifically, the present disclosure relates to a circuit and a method for operating quasi-floating bulk direct gate driven MOSFET.
[00022] FIG. 1 illustrates a schematic representation of a circuit to operate a metal oxide semiconductor field effect transistor (MOSFET) in accordance with an embodiment of the present disclosure. The circuit 100 includes a first sub-circuit 102 corresponding to operate as a first resistor 102. The first resistor 102 includes a first direct current (DC) bias voltage source 104. As used herein, the term ‘DC bias voltage source’ is defined as a voltage source supplying a fixed DC voltage to the circuit.
[00023] The first resistor 102 also includes a second direct current (DC) bias voltage source 106. The first resistor 102 also includes a first metal oxide semiconductor (MOS) device 108. As used herein, the term ‘MOS device also referred as metal oxide semiconductor field effect transistor (MOSFET)’ is defined as of insulated-gate field-effect transistor that is fabricated by the controlled oxidation of a semiconductor, typically silicon. The MOSFET devices are used for amplifying or switching electronic signals.
[00024] Furthermore, the first resistor 102 includes a second metal oxide semiconductor (MOS) device 110. The first resistor 102 includes further includes a third metal oxide semiconductor (MOS) device 112. The first resistor 102 includes also includes a first capacitor 114 and a second capacitor 116.
[00025] A first end of the first direct current (DC) bias voltage source 104 is coupled to the first MOS device 108, and a second end of the first direct current (DC) bias voltage source 104 is coupled to the second MOS device 110.
[00026] A first end of the second direct current (DC) bias voltage source 106 is coupled to a drain of the third MOS device 112, wherein a first end of the first capacitor 114 is coupled to a source end of the third MOS device 112, wherein a second end of the first capacitor 114 is coupled to a drain of the second MOS device 110, a gate of the third MOS 112 device and a first end of the second capacitor 116, wherein the gate of the third MOS device 112 is directly driven via the second direct current (DC) bias voltage source 106, wherein a bulk of the third MOS device 112 is quasi floating driven. Further, the first MOS device 108, the second MOS device 110 along with the first capacitor 114 and the second capacitor 116 forms quasi floating bulk of the third MOS device 112.
[00027] Furthermore, the circuit includes a second sub-circuit 118 corresponding to operate as a second resistor 118. The second resistor 118 includes a third direct current (DC) bias voltage source 120. The second resistor 118 also includes a fourth direct current (DC) bias voltage source 122.
[00028] The second resistor 118 also includes a fourth metal oxide semiconductor (MOS) device 124. The second resistor 118 further includes a fifth metal oxide semiconductor (MOS) device 126. The second resistor 118 also includes a sixth metal oxide semiconductor (MOS) device 128. The second resistor 118 also includes a third capacitor 130 and a fourth capacitor 132.
[00029] A first end of the third direct current (DC) bias voltage source 120 is coupled to the first MOS device 108, and a second end of the third direct current (DC) bias voltage source 120 is coupled to the fifth MOS device 126.
[00030] A first end of the fourth direct current (DC) bias voltage source 122 is coupled to a drain of the sixth MOS device 128, wherein a first end of the third capacitor 130 is coupled to a source end of the sixth MOS device 128, wherein a second end of the third capacitor 130 is coupled to a drain of the fifth MOS device 126, a gate of the sixth MOS device 128 and a first end of the fourth capacitor 132, wherein the gate of the sixth MOS device 128 is directly driven via the fourth direct current (DC) bias voltage source 122, wherein a bulk of the sixth MOS device 122 is quasi floating driven. Further the fourth MOS device 124, the fifth MOS device 126 along with the third capacitor 130 and the fourth capacitor 132 forms quasi floating bulk of the sixth MOS device 128.
[00031] Furthermore, the circuit includes a third sub circuit 134 which includes: a seventh primary MOS device 136, a seventh secondary MOS device 138, an eighth primary MOS device 140, an eighth secondary MOS device 142, a ninth first-primary MOS device 144, a ninth second-primary MOS device 146, a ninth first-secondary MOS device 148, a ninth second-secondary MOS device 150, a tenth primary MOS device 152 and a tenth secondary MOS device 154.
[00032] In one embodiment, the circuit includes a plurality of MOS mirror pairs, wherein the MOS mirror pairs includes the seventh primary MOS device 136 with the seventh secondary MOS device 138, the eighth primary MOS device 140 with the eighth secondary MOS device 142, the ninth first-primary MOS device 144 with the ninth first-secondary MOS device 148, the tenth primary MOS device 152 with the tenth secondary MOS device 154.
[00033] The drain of the third MOS device 112 of the first sub-circuit 102 is coupled to a first end of a third voltage source 120, wherein the first end of the third voltage source 120 is coupled to a source of the tenth primary MOS device 152, wherein the drain of the third MOS device 112 of the second sub-circuit 118 is coupled to a second end of the third voltage source 120.
[00034] Further, a gate of the tenth primary MOS device 152 and a gate of the tenth secondary MOS device 154 are operatively coupled to a source of the seventh primary MOS device 136 and a source of the seventh secondary MOS device 138. A gate of the seventh primary MOS device 136 is coupled to a first end of a current source 156. Further, a drain of the seventh secondary MOS device 138 is operatively coupled to a source of the eighth primary MOS device 140 and a source of the eighth secondary MOS device 142.
[00035] A drain of the eighth primary MOS device 140 is coupled to a drain of the ninth first-primary MOS device 144, a gate of the ninth first-primary MOS device 144 and a gate of the ninth first-secondary MOS device 148. A drain of the eighth secondary MOS device 142 is coupled to a drain of the ninth second-primary MOS device 146, a gate of the ninth second-primary MOS device 146 and a gate of the ninth second-secondary MOS device 150.
[00036] Furthermore, a gate of the eighth primary MOS device 140 is operatively coupled to a second end of an input voltage source 158 via a fifth capacitor 160, wherein a gate of the eighth secondary MOS device 142 is operatively coupled to a first end of the input voltage source 158 via a sixth capacitor 162. Subsequently, the eighth primary MOS device 140, the eighth secondary MOS device 142, the fifth capacitor 160, the sixth capacitor 162, the first sub-circuit 102 and the second sub-circuit 118 forms a quasi-floating bulk direct gate driven MOSFET technique. The quasi-floating bulk direct gate driven MOSFET technique is applied to a pair of eighth primary MOS device 140 and the eighth secondary MOS device 142 to operate the MOSFET.
[00037] In one exemplary embodiment, output voltage is measured across a drain of the tenth secondary MOS device 154 and a drain of the ninth second-secondary MOS device 150.
[00038] In one embodiment, a source of the tenth primary MOS device 152 and a source of the tenth secondary MOS device 154 is operatively coupled to a drain power voltage 164. In such embodiment, a source of the ninth first-secondary MOS device and a source of the ninth second-secondary MOS device is operatively coupled to a voltage source supply 166.
[00039] In one specific embodiment, the circuit is implemented in at least one of Electro-encephalography (EEG), Electrocorticography (ECoG), in-vivo multi-electrode recordings, or a combination thereof.

ADVANTAGES OF THE PRESENT DISCLOSURE
[00040] The present disclosure provides a circuit and a method for operating quasi-floating bulk direct gate driven MOSFET.
[00041] The present disclosure provides high-gain MOS operational transconductance amplifier.
[00042] The present disclosure also provides low-noise MOS operational transconductance amplifier.
[00043] The present disclosure further provides very small impact of process voltage and temperature variations.
[00044] The present disclosure further provides Low-voltage and low-current operation.

We Claims:

1. A circuit to operate a metal oxide semiconductor field effect transistor (MOSFET) comprising:
a first sub-circuit corresponding to operate as a first resistor comprising:
a first direct current (DC) bias voltage source;
a second direct current (DC) bias voltage source;
a first metal oxide semiconductor (MOS) device;
a second metal oxide semiconductor (MOS) device;
a third metal oxide semiconductor (MOS) device;
a first capacitor;
a second capacitor,
wherein a first end of the first direct current (DC) bias voltage source is coupled to the first MOS device, and a second end of the first direct current (DC) bias voltage source is coupled to the second MOS device,
wherein a first end of the second direct current (DC) bias voltage source is coupled to a drain of the third MOS device, wherein a first end of the first capacitor is coupled to a source end of the third MOS device, wherein a second end of the first capacitor is coupled to a drain of the second MOS device, a gate of the third MOS device and a first end of the second capacitor, wherein the gate of the third MOS device is directly driven via the second direct current (DC) bias voltage source, wherein a bulk of the third MOS device is quasi floating driven,
wherein the first MOS device, the second MOS device along with the first capacitor and the second capacitor forms quasi floating bulk of the third MOS device;
a second sub-circuit corresponding to operate as a second resistor comprising:
a third direct current (DC) bias voltage source;
a fourth direct current (DC) bias voltage source;
a fourth metal oxide semiconductor (MOS) device;
a fifth metal oxide semiconductor (MOS) device;
a sixth metal oxide semiconductor (MOS) device;
a third capacitor;
a fourth capacitor,
wherein a first end of the third direct current (DC) bias voltage source is coupled to the first MOS device, and a second end of the third direct current (DC) bias voltage source is coupled to the fifth MOS device,
wherein a first end of the fourth direct current (DC) bias voltage source is coupled to a drain of the sixth MOS device, wherein a first end of the third capacitor is coupled to a source end of the sixth MOS device, wherein a second end of the third capacitor is coupled to a drain of the fifth MOS device, a gate of the sixth MOS device and a first end of the fourth capacitor, wherein the gate of the sixth MOS device is directly driven via the fourth direct current (DC) bias voltage source, wherein a bulk of the sixth MOS device is quasi floating driven,
wherein the fourth MOS device, the fifth MOS device along with the third capacitor and the fourth capacitor forms quasi floating bulk of the sixth MOS device;
a third sub circuit comprising:
a seventh primary MOS device;
a seventh secondary MOS device;
an eighth primary MOS device;
an eighth secondary MOS device;
a ninth first-primary MOS device;
a ninth second-primary MOS device;
a ninth first-secondary MOS device;
a ninth second-secondary MOS device;
a tenth primary MOS device; and
a tenth secondary MOS device,
wherein the drain of the third MOS device of the first sub-circuit is coupled to a first end of a third voltage source, wherein the first end of the third voltage source is coupled to a source of the tenth primary MOS device, wherein the drain of the third MOS device of the second sub-circuit is coupled to a second end of the third voltage source,
wherein a gate of the tenth primary MOS device and a gate of the tenth secondary MOS device are operatively coupled to a source of the seventh primary MOS device and a source of the seventh secondary MOS device,
wherein a gate of the seventh primary MOS device is coupled to a first end of a current source,
wherein a drain of the seventh secondary MOS device is operatively coupled to a source of the eighth primary MOS device and a source of the eighth secondary MOS device,
wherein a drain of the eighth primary MOS device is coupled to a drain of the ninth first-primary MOS device, a gate of the ninth first-primary MOS device and a gate of the ninth first-secondary MOS device,
wherein a drain of the eighth secondary MOS device is coupled to a drain of the ninth second-primary MOS device, a gate of the ninth second-primary MOS device and a gate of the ninth second-secondary MOS device,
wherein a gate of the eighth primary MOS device is operatively coupled to a second end of an input voltage source via a fifth capacitor, wherein a gate of the eighth secondary MOS device is operatively coupled to a first end of the input voltage source via a sixth capacitor,
wherein the eighth primary MOS device, the eighth secondary MOS device, the fifth capacitor, the sixth capacitor, the first sub-circuit and the second sub-circuit forms a quasi-floating bulk direct gate driven MOSFET technique,
wherein the quasi-floating bulk direct gate driven MOSFET technique is applied to a pair of eighth primary MOS device and the eighth secondary MOS device to operate the MOSFET.
2. The circuit as claimed in claim 1, wherein the circuit comprises a plurality of MOS mirror pairs, wherein the MOS mirror pairs comprises the seventh primary MOS device with the seventh secondary MOS device, the eighth primary MOS device with the eighth secondary MOS device, the ninth first-primary MOS device with the ninth first-secondary MOS device, the tenth primary MOS device with the tenth secondary MOS device.
3. The circuit as claimed in claim 1, wherein output voltage is measured across a drain of the tenth secondary MOS device and a drain of the ninth second-secondary MOS device.
4. The circuit as claimed in claim 1, wherein the circuit is implemented in at least one of Electro-encephalography (EEG), Electrocorticography (ECoG), in-vivo multi-electrode recordings, or a combination thereof.