[0001]The present disclosure relates to computing systems. In particular it pertains to
memory arrays used in computing systems.
BACKGROUND OF THE DISCLOSURE
[0002] The background description includes information that may be useful in
understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] A computer system throughput is limited due to the relative ability of its
processors compared to top rates of data transfer. A processor is idle for a certain amount of time while memory is accessed. This is known as the von Neumann bottleneck after John von Neumann, a 20th century mathematician, scientist and computer science pioneer who was also involved in the Manhattan Project
[0004] Solutions to the bottleneck aim at achieving a higher memory access to serve a
faster processor such as a CPU. In a von Neumann architecture, a computer stores programming instructions along with actual data. This is in contrast to a Harvard architecture where these two kinds of memory are stored separately. Computer scientists have attempted to address the von Neumann bottleneck in various ways. One is to place critical memory in an easily accessible cache. There is also the idea of multithreading, or managing multiple processes in a triaged system. Other potential tools, like parallel processing, or changing the memory bus design, also work on the idea of decreasing this "bottleneck" or, in a phrase commonly used with this issue, increase the bandwidth for memory coming in and out of the processor.
[0005] Present solutions so far proposed mainly emphasis on near-memory computing.
However, near memory computing solutions are not optimum solutions as memory and logic operations are performed on different memory blocks and to and fro movement of data is required between the two blocks.

[0006] Hence there is a need in the art for a method and a device that enables removal of
this bottleneck as much as possible so as to cater to ever faster and more parallel processing needs demanded by present computer applications.
[0007] All publications herein are incorporated by reference to the same extent as if each
individual publication or patent application were specifically and individually indicated to be
incorporated by reference. Where a definition or use of a term in an incorporated reference is
inconsistent or contrary to the definition of that term provided herein, the definition of that term
provided herein applies and the definition of that term in the reference does not apply.
[0008] In some embodiments, the numbers expressing quantities or dimensions of items,
and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term "about." Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[0009] As used in the description herein and throughout the claims that follow, the
meaning of "a," "an," and "the" includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of "in" includes "in" and "on" unless the context clearly dictates otherwise.
[00010] The recitation of ranges of values herein is merely intended to serve as a
shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. "such as") provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not

pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[00011] Groupings of alternative elements or embodiments of the invention disclosed
herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.
OBJECTS OF THE INVENTION
[00012] Some of the objects of the present disclosure, which at least one embodiment
herein satisfies are as listed herein below.
[00013] It is an object of the present disclosure to provide for a circuit that eliminates
problem of "memory wall" being faced in von Neumann architecture that limits data transfer
between a processor and associated memory due to inherent data access limitations in existing
memory circuits.
[00014] It is another object of the present disclosure to provide for a circuit that can
perform both memory and logic operations, and can store both memory and logic state
simultaneously in time (clock cycle) and space (silicon area).
[00015] It is yet another object of the present disclosure to provide for a circuit that can
shift some level of intelligence directly into the memory array realized using same memory
bitcells and not a nearby logic array.
[00016] It is another object of the present disclosure to provide for a circuit that can use
bitcells from memory array itself, perform one step logic realization, and store the result in-situ
in the same bitcell without interfering with the memory state stored prior logic operation.
[00017] It is yet another object of the present disclosure to provide for a circuit that can
eliminate need for extra memory bitcell required to store the logic output and using which a
single read operation can provide both memory and logic state outputs, thereby saving one read
step and one extra memory access.

[00018] It is yet another object of the present disclosure to provide for a circuit that can
eliminate the need for extra processing or computational blocks used to realize logic operations, as the memory array itself can be utilized to perform logic operations.
SUMMARY
[00019] The present disclosure mainly relates to memory arrays in computing systems, in
particular it pertains to a circuit for implementing a memory that assists in improving processing
bandwidth of a computing system by mitigating von Neumann bottleneck.
[00020] This summary is provided to introduce simplified concepts of circuit for in
memory computing operations, which are further described below in the Detailed Description.
This summary is not intended to identify key or essential features of the claimed subject matter,
nor is it intended for use in determining/limiting the scope of the claimed subject matter.
[00021] In an aspect, proposed invention discloses a circuit that can include a non-volatile
memory (NVM) device based bitcell, the bitcell including two transistors and a multilevel NVM
device that is capable of simultaneously storing memory and logic state such that both logic and
Memory states can be readable at the same time in a single clock cycle.
[00022] In another aspect, the bitcell can perform both Memory and Logic operations
simultaneously on the same bitcell so as to eliminate extra data movement required between
memory and logic arrays.
[00023] In yet another aspect, the NVM device based bitcell can be configured as or can
be used to build a cache memory array that can act as a high speed buffer between conventional
memory and CPU with computing capability.
[00024] In an aspect, the bitcell can enable realization of logic and memory functions
simultaneously in space/silicon area and time/clock cycles.
[00025] In yet another aspect, the NVM device can have four or more distinct resistive
states, the states being Memory Low Resistance States (LRS states) and Memory High
Resistance States (HRS states), and memory region can include the LRS and HRS states that can
be sub-categorized as Logic ' 1' and Logic '0'.
[00026] In an aspect, during a Memory Write operation, initially a read operation can be
performed.

[00027] In another aspect, in case the NVM device is in the same state as it needs to be
programmed, no programming signal is applied, and if initial state of NVM device is different, at least one programming signal can be applied.
[00028] In yet another aspect, for Memory Write ‗1‘, the NVM device can be
programmed to state ‗11‘, and for Memory Write ‗0‘, the device can be programmed to state ‗01‘.
[00029] In an aspect, during memory write operation, the two transistors (M1 and M2) can
be kept ON, and during logic operation, at least one predefined programming signal can be applied at terminals (V1 and V2) of the bitcell and input variables can act as gate control signals for the two transistors, and the NVM device can be programmed to a corresponding logic state depending on different combinations of the input variables.
[00030] In another aspect, multiple logic operations can be realized if refresh operation is
performed on the bitcell for which previous logic output is no longer required.
[00031] The technical problem solved by proposed invention is the ―memory wall‖ being
faced in von Neumann architecture that limits data transfer between a processor and associated
memory due to inherent data access limitations in existing memory circuits.
[00032] Proposed invention aims to solve this problem by processing data right at the
memory bitcell itself thereby eliminating bandwidth-limiting and energy consuming transfers between the processor and memory and so, completely diminishing the data movement problem of data-intensive applications. Present disclosure elaborates upon a simultaneous logic in memory (SLIM) methodology that makes memory capable of performing at least some part of logic operations as well. A NVM device based bitcell that is capable of performing both memory and logic operations and storing results of both the operations in the same bitcell ―simultaneously‖ is disclosed, thereby eliminating need for extra memory bitcell required to store the logic output and enabling a single read operation to provide both memory and logic state outputs.
[00033] Within the scope of this application it is expressly envisaged that the various
aspects, embodiments, examples and alternatives set out in the preceding paragraphs, in the claims and/or in the following description and drawings, and in particular the individual features thereof, may be taken independently or in any combination. Features described in connection with one embodiment are applicable to all embodiments, unless such features are incompatible.
6

[00034] Various objects, features, aspects and advantages of the present disclosure will
become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like features.
BRIEFDESCRIPTIONOFDRAWINGS
[00035] The accompanying drawings are included to provide a further understanding of
the present disclosure, and are incorporated in and constitute a part of this specification. The
drawings illustrate exemplary embodiments of the present disclosure and, together with the
description, serve to explain the principles of the present disclosure. The diagrams are for
illustration only, which thus is not a limitation of the present disclosure, and wherein:
[00036] FIG. 1(a) illustrates a von Neumann based computer architecture while FIG. 1(b)
illustrates existing state of art LIM solutions.( Prior Arts)
[00037] FIG. 1 (c) illustrate s an exemplary SLIM solution for true logic-in-memory
realization in accordance with an exemplary embodiment of the present disclosure.
[00038] FIG. 2 illustrates four distinct NVM device states that can be used to implement
proposed invention in accordance with exemplary embodiments of the present disclosure.
[00039] FIG. 3 illustrates circuit schematic for 2T-1R NVM device based bitcell for
implementing SLIM functionality proposed in this invention, in accordance with an exemplary
embodiment of the present disclosure. .
[00040] FIG. 4(a) illustrates a flowchart summarizing memory operations in proposed
SLIM bitcell, while FIG. 4(b) illustrates a flowchart summarizing logic operations in the
proposed SLIM bitcell, in accordance with an exemplary embodiment of the present disclosure.
[00041] FIG. 5 summarizes exemplary programming signals that can be used in proposed
invention in accordance with an exemplary embodiment of the present disclosure.
[00042] Table 1 summarizes the logical truth table results for NOR gate implementation in
accordance with an exemplary embodiment of the present disclosure.
[00043] FIGs.6(a) to 6(f) illustrate Memory Write '1' and Memory Write '0' from different
initial conditions for an exemplary device configured with proposed NVM device based bitcell in
accordance with an exemplary embodiment of the present disclosure.
7

[00044] FIG. 7 shows experimental result for four possible cases of variables ‗k‘ and ‗l '
(i.e., k=l='0'; k='0',l='1' ; k='1',l='0 '; k=l='1') in accordance with an exemplary embodiment of
the present disclosure.
[00045] FIG.8 illustrates architecture of a refresh scheme used in order to carry out
multiple consecutive logic operations in accordance with an exemplary embodiment of the
present disclosure.
[00046] FIGs. 9(a) and 9(b) illustrate exemplary alternate block architectures for proposed
SLIM implementation in accordance with exemplary embodiments of the present disclosure.
[00047] Table 2 illustrates variable assignment for other Boolean logic operations in
accordance with an exemplary embodiment of the present disclosure
[00048] Table 3 illustrates a comparison of SLIM architecture proposed with existing
different schemes proposed in literature.
DETAILED DESCRIPTION
[00049] The following is a detailed description of embodiments of the disclosure depicted
in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[00050] In the following description, numerous specific details are set forth in order to
provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
[00051] If the specification states a component or feature ―may‖, ―can‖, ―could‖, or
―might‖ be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[00052] As used in the description herein and throughout the claims that follow, the
meaning of ―a,‖ ―an,‖ and ―the‖ includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of ―in‖ includes ―in‖ and ―on‖ unless the context clearly dictates otherwise.
8

[00053] Exemplary embodiments will now be described more fully hereinafter with
reference to the accompanying drawings, in which exemplary embodiments are shown. These exemplary embodiments are provided only for illustrative purposes and so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. The invention disclosed may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Various modifications will be readily apparent to persons skilled in the art. The general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Moreover, all statements herein reciting embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure). Also, the terminology and phraseology used is for the purpose of describing exemplary embodiments and should not be considered limiting. Thus, the present invention is to be accorded the widest scope encompassing numerous alternatives, modifications and equivalents consistent with the principles and features disclosed. For purpose of clarity, details relating to technical material that is known in the technical fields related to the invention have not been described in detail so as not to unnecessarily obscure the present invention.
[00054] Thus, for example, it will be appreciated by those of ordinary skill in the art that
the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this invention. The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches if shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named element.
9

[00055] The ensuing description provides exemplary embodiments only, and is not
intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing an exemplary embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the disclosure as set forth in the appended claims.
[00056] Specific details are given in the following description to provide a thorough
understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments.
[00057] Embodiments of the present invention may be provided as or associated with a
computer program product, which may include a machine-readable storage medium tangibly embodying thereon instructions, which may be used to program a computer (or other electronic devices) to perform a process. The term ―machine-readable storage medium‖ or ―computer-readable storage medium‖ includes, but is not limited to, fixed (hard) drives, magnetic tape, floppy diskettes, optical disks, compact disc read-only memories (CD-ROMs), and magneto-optical disks, semiconductor memories, such as ROMs, PROMs, random access memories (RAMs), programmable read-only memories (PROMs), erasable PROMs (EPROMs), electrically erasable PROMs (EEPROMs), solid-state drives (SSDs), flash memory, magnetic, resistive memory (RRAM/ReRAM), phase-change memory, conductive bridge memory (CBRAM), spintronics based memory, organic device based memory (PCM), ferroelectric memory (FRAM, FeRAM), memristor, atomic memory or optical cards, or other type of media/machine-readable medium suitable for storing electronic instructions (e.g., computer programming code, such as software or firmware). A machine-readable medium may include a non-transitory medium in which data can be stored and that does not include carrier waves and/or transitory electronic signals propagating wirelessly or over wired connections. Examples of a non-transitory medium may include, but are not limited to, a magnetic disk or tape, optical storage media such as compact disk (CD) or digital versatile disk (DVD), flash memory, memory
10

or memory devices. A computer-program product may include code and/or machine-executable instructions that may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and/or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.
[00058] Furthermore, embodiments may be implemented by hardware, software,
firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks (e.g., a computer-program product) may be stored in a machine-readable medium. A processor(s) may perform the necessary tasks.
[00059] Each of the appended claims defines a separate invention, which for infringement
purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the "invention" may in some cases refer to certain specific embodiments only. In other cases it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.
[00060] Various terms as used herein are shown below. To the extent a term used in a
claim is not defined below, it should be given the broadest definition persons in the pertinent art
have given that term as reflected in printed publications and issued patents at the time of filing.
[00061] In an aspect, proposed invention discloses a circuit that can include a non-volatile
memory (NVM) device based bitcell, the bitcell including two transistors and a multilevel NVM device that is capable of simultaneously storing memory and logic state such that both logic and Memory states can be readable at the same time in a single clock cycle.
[00062] In another aspect, the bitcell can perform both Memory and Logic operations
simultaneously on the same bitcell so as to eliminate extra data movement required between memory and logic arrays.
11

[00063] In yet another aspect, the NVM device based bitcell can be configured as or can
include a cache memory array that can act as a high speed buffer between conventional memory and CPU.
[00064] In an aspect, the bitcell can enable realization of logic and memory functions
simultaneously in space/silicon area and time/clock cycles.
[00065] In yet another aspect, the NVM device can have four or more distinct resistive
states, the states being Memory Low Resistance States (LRS states) and Memory High Resistance States (HRS states), and memory region can include the LRS and HRS states that can be sub-categorized as Logic ‗ 1‘ and Logic ‗0‘.
[00066] In an aspect, during a Memory Write operation, initially a read operation can be
performed.
[00067] In another aspect, in case the NVM device is in the same state as it needs to be
programmed, no programming signal is applied, and if initial state of NVM device is different, at least one programming signal can be applied.
[00068] In yet another aspect, for Memory Write ‗1‘, the NVM device can be
programmed to state ‗11‘, and for Memory Write ‗0‘, the device can be programmed to state ‗01‘.
[00069] In an aspect, during memory write operation, the two transistors (M1 and M2) can
be kept ON, and during logic operation, at least one predefined programming signal can be applied at terminals (V1 and V2) of the bitcell and input variables can act as gate control signals for the two transistors, and the NVM device can be programmed to a corresponding logic state depending on different combinations of the input variables.
[00070] In another aspect, multiple logic operations can be realized if refresh operation is
performed on the bitcell for which previous logic output is no longer required.
[00071] In an aspect, invention disclosed assists in overcoming limitations of von
Neumann bottleneck and its existing solutions. Existing solutions so far proposed in literature
mainly emphasis on near-memory computing. However, near memory computing solutions are
not optimum solutions as memory and logic operations are performed on different memory
blocks and to and fro movement of data is required between the two blocks.
[00072] Proposed simultaneous logic in memory (SLIM) methodology elaborated herein
develops on the concept of making memory capable of doing some part of logic realization.
12

Invention disclosed delivers a NVM device based bitcell that is capable of performing both
memory and logic operations and is capable of storing results of both the operations in the same
bitcell ―simultaneously‖. This eliminates need for extra memory bitcell required to store the
logic output and a single read operation can provide both memory and logic state outputs.
Consequently, memory density can be enhanced and data movement between memory arrays for
computation can be lowered.
[00073] Proposed invention uses NOR gate realization as universal logic gate. That is, all
basic logic operations and add operation can be performed using multiple NOR gates. Building
NOR gate will boost the logic computation capabilities of the memory formed using proposed
methodology. Further, SLIM capabilities proposed can be expanded to different Boolean logics
such as NOT, AND, OR and NAND gates using different schemes as further elaborated.
[00074] In an aspect, proposed invention helps in eliminating the major issue of ―memory
wall‖ being faced in von Neumann architecture by eliminating bandwidth-limiting and energy
consuming transfers between the processor and memory. Processing right at the memory bitcell
can completely diminish the data movement problem of data-intensive applications.
[00075] In another aspect, 2T-1R (2 Transistor 1 Resistive Random Access Memory)
SLIM array described herein can be essentially a microelectronic memory with some
combination logic associated with each 2T-1R bitcell. 2T-1R SLIM logic-enhanced ―cache‖
memory array can act as a high speed buffer between conventional memory and CPU.
[00076] In yet another aspect, multilevel non-volatile memories can be used for SLIM
bitcell that can store both Memory and Logic state even after a system using such memories is
shut down.
[00077] In this manner, invention proposed helps in reading both logic and Memory states
at the same time, thereby saving on read step and so, saving one extra memory access. It needs
only one step (one clock cycle) for logic execution, unlike existing solutions that need two or
three steps for realizing a logic.
[00078] In an aspect, by using refresh operation on 2T-1R NVM device based bitcells, for
which logic output is no longer required, multiple logic operations can be performed on the same
2T-1R bitcell with Memory state always preserved.
[00079] The proposed methodology and invention can save considerable amount of silicon
area in computing systems
13

[00080] The proposed methodology can enable latent storage devices like SSDs, USBs,
SD cards to also be used for computing without the loss of data that they are already storing.
[00081] In an exemplary embodiment, invention proposed can include a SLIM bitcell with
two transistors and one multilevel NVM (non-volatile memory) device (with four discrete well
separated resistive levels) capable of storing Memory and Logic state simultaneously. The key
concept of SLIM implementation is illustrated in FIG. 1(c).
[00082] FIG. 1(a) shows a typical von Neumann based computer architecture where logic
and memory implementations are carried out in two separate units and there is data movement
between these two for realizing logic/ arithmetic functionalities. Logic operation is carried out at
Arithmetic Logic Unit (ALU) shown as 102 that interacts with memory blocks shown as 104.
FIG. 1(b) illustrates the LIM (Logic-in-memory) solutions proposed so far. In these
implementations, different LIM bitcell arrays (memory and logic bitcell arrays) shown as 122
and 124 are exploited and data transfer takes place between these two and hence latency for
executing a logic operation and storing its output is lowered when compared with traditional von
Neumann architecture.
[00083] FIG. 1 (c) illustrates proposed invention concept. Here the same bitcell (SLIM
bitcell) illustrated as 142 performs both Memory and Logic operations simultaneously on the
same bitcell and hence eliminates extra data movement required between memory and logic
arrays.
[00084] In proposed invention, the same NVM device based bitcell is capable of
performing both memory and logic operation and furthermore it can preserve memory and logic
states simultaneously. Both logic and memory states can be read simultaneously. Hence it can be
termed as a SLIM (simultaneous logic in memory) bitcell. Thus, it can realize logic- and
memory functions simultaneously in space (silicon area) and time (clock cycles).
[00085] FIG. 2 illustrates four distinct NVM device states that can be used to implement
proposed invention in accordance with exemplary embodiments of the present disclosure.
[00086] In an exemplary embodiment, a multilevel bilayer OxRAM ( oxide based resistive
memory) device can be used as an NVM device. The resistance range choice is a function of
NVM device and programming conditions.
[00087] Four distinct resistive states can be selected for the NVM device. As shown in
FIG. 2, these states can be categorized as Memory LRS (low resistance state) states (shown as
14

state ‗11‘ and state ‗10‘) and Memory HRS (high resistance state) states (shown as state ‗01‘ and state ‗00‘). Within each memory region, the two states can be sub- categorized as Logic ‗1‘ and Logic ‗0‘ as illustrated.
[00088] FIG. 3 illustrates circuit schematic for a 2T-1R NVM device based bitcell for
implementing SLIM functionality proposed in this invention, in accordance with an exemplary embodiment of the present disclosure.
[00089] M1 and M2 illustrated can be two NMOS (N-type metal-oxide-semiconductor)
transistors of the 2T-1R NVM device based bitcell disclosed. Pulses P1/P2 can be applied at
node V1 and P3 at node V2 (pulses P1, P2 and P3 as shown in FIG. 5 and Table 2). Gate
voltages VG1 and VG2 can be applied at transistors M1 and M2 respectively in line with operands
as shown in Table 2. Table 2 illustrates variable assignment for other Boolean logic operations.
[00090] FIG. 4(a) illustrates a flowchart summarizing memory operations in proposed
SLIM bitcell, while FIG. 4(b) illustrates a flowchart summarizing logic operations in the
proposed SLIM bitcell, in accordance with an exemplary embodiment of the present disclosure.
[00091] FIG. 4 (a) illustrates working methodology of SLIM bitcell (NVM device based
bitcell) proposed. During Memory Write operation, initially a read operation can be performed as
shown at 402 and initial device (that is, the NVM device in which the proposed bitcell is being
implemented) state Sint can be read. In prior art/ published literature, read before write has been
considered as an effective endurance enhancement algorithm. Sint can be compared with state to
be programmed, as shown at 404.If the device is already in the same state as it needs to be
programed ( i.e. Sint is same as state to be programmed), no further programming signal is
applied, as shown at 406. However, if initial state of the NVM device is different (i.e. Sint is not
equal to the state to be programmed), programming signals are applied, as illustrated at 408.
[00092] For Memory Write ‗1‘, the device can be programmed to state ‗11‘ and for
Memory Write ‗0‘, the device can be programmed to state ‗01‘.
[00093] During Memory Write operation, M1 and M2 transistors (as shown in FIG.3)
can be kept ON. During logic operation, predefined programming signals may be applied at V1 and V2 terminals of bitcell (shown in FIG. 4) and input variables (operands) k and l ( as given in table 1) can act as gate control signals for transistor M1 and M2 respectively. The NVM device can be programmed to a corresponding logic state depending upon the different
15

combination of variable k and l. NOR operation can be realized using proposed SLIM bitcell and as summarized in Table 1.
[00094] FIG. 4(b) illustrates a flowchart summarizing logic operations in the proposed
SLIM bitcell, in accordance with an exemplary embodiment of the present disclosure.
[00095] As already elaborated, prime benefit of SLIM methodology is to perform memory
and logic operation on the same SLIM bitcell. Before executing memory operation, OxRAM device state can be read using sense amplifier circuit. State ‗11‘ (signifying Memory write ‗1‘) and State ‗01‘ (signifying Memory write ‗0‘) can be the absolute memory states. However, during Logic operation, depending upon the value of operands k and l, the possible device states can be State ‗11‘, State ‗10‘, State ‗01‘ and State ‗00‘. In order to perform multiple logic operations, refresh operation needs to be performed to ensure the resistive state of device lies in absolute memory states before each logic operation.
[00096] To implement refresh operation, three SET pulses (of amplitude 2 V each and
pulse width = 7 ms i.e. P2) can be applied after selecting the SLIM bitcells in non-absolute
memory state. This selection can be carried out using row decoder and column selectors in an
array. This can bring back the device to absolute memory states and a new logic operation can be
performed. In this manner, a refresh scheme can be implemented as summarized in FIG. 4(b).
[00097] As illustrated in FIG. 4(b), at 420 a logic operation request can be implemented
consequent which at 422 the SLIM bitcells can be read. At 424 it can be determined if bitcells read are in absolute Memory State (11/01) or not. If yes, logic can be applied on them as shown at 426. If no, bitcells with non-absolute Memory state can be selected as shown at 428. Further refresh: V1=P2, V2=gnd, VG1=VG2=4 V can be applied, as shown at 430,consequent to which logic can be performed as shown at 432.
[00098] FIG. 5 summarizes exemplary programming signals that can be used in proposed
invention in accordance with an exemplary embodiment of the present disclosure.
[00099] FIG. 5 illustrates exemplary proposed programming signals for SLIM memory-
logic transitions in a 2T-1R SLIM bitcell, in accordance with an exemplary embodiment of the present disclosure.
[000100] The programming signals used for state transition can be specific to the device used. Different programming pulses P1, P2 and P3 as shown in FIG. 5 can be used.
16

[000101] Table 1 summarizes the logical truth table results for NOR gate implementation
in accordance with an exemplary embodiment of the present disclosure.
[000102] Table 1 illustrates a Truth table for NOR logic operation realized using SLIM
methodology proposed herein.
[000103] As shown, States 11 and 10 are Memory LRS states, while states 01 and 00 are
memory HRS states. Stored memory state is preserved after all logic operations. Same SLIM
bitcell is capable of performing both Memory and Logic functions.
[000104] FIGs.6(a) to 6(f) illustrate Memory Write ‗1‘ and Memory Write ‗0‘ from
different initial conditions for an exemplary device configured with proposed NVM device based
bitcell in accordance with an exemplary embodiment of the present disclosure.
[000105] In an exemplary embodiment, an MLC (multi-level cell) bilayer OxRAM device
Ni/HfO2 (3 nm)/ TiO2:Al (9 nm)/ TiN can be used for validating functionality of SLIM bitcell
proposed.
[000106] FIG. 6 summarizes Memory Write ‗1‘ and Memory Write ‗0‘ from different
initial conditions for an exemplary device as elaborated above.
[000107] FIG. 6(a) illustrates Memory Write ‗1‘ operation (programming device to state
11) with the device‘s initial condition as state 10. Programming signals in volts are plotted along
Y axis while programming time in milliseconds is plotted along X axis. Curve 602-1 represents
current through the OxRAM device in microamperes.
[000108] Corresponding FIG. 6(a1) illustrates graph of a read operation for the device‘s initial condition as state 10 to final state 11. Resistance in Megaohms is plotted along Y axis while read time in milliseconds is plotted along Y Axis. Curve 604-1 represents initial state resistance while curve 604-2 represents the final state resistance.
[000109] FIG. 6(b) illustrates Memory Write ‗1‘ operation (programming device to state 11) with the device‘s initial condition as state 01. Programming signals in volts are plotted along
Y axis while programming time in milliseconds is plotted along X axis. Curve 602-2 represents
current through the OxRAM device in microamperes.
[000110] Corresponding FIG. 6(b1) illustrates graph of a read operation for the device‘s initial condition as state 01 to final state 11. Resistance in Megaohms is plotted along Y axis while read time in milliseconds is plotted along Y Axis. Curve 606-1 represents initial state resistance while curve 606-2 represents the final state resistance.
17

[000111] FIG. 6(c) illustrates Memory Write ‗1‘ operation (programming device to state
11) with the device‘s initial condition as state 00. Programming signals in volts are plotted along
Y axis while programming time in milliseconds is plotted along X axis. Curve 602-3 represents
current through the OxRAM device in microamperes.
[000112] Corresponding FIG. 6(c1) illustrates graph of a read operation for the device‘s
initial condition as state 00 to final state 11. Resistance in Megaohms is plotted along Y axis while read time in milliseconds is plotted along Y Axis. Curve 608-1 represents initial state resistance while curve 608-2 represents the final state resistance.
[000113] FIG. 6(d) illustrates Memory Write ‗0‘ operation (programming device to state
01) with the device‘s initial condition as state 11. Programming signals in volts are plotted along
Y axis while programming time in milliseconds is plotted along X axis. Curve 622-1 represents
current through the OxRAM device in microamperes.
[000114] Corresponding FIG. 6(d1) illustrates graph of a read operation for the device‘s
initial condition as state 11 to final state 01. Resistance in Megaohms is plotted along Y axis while read time in milliseconds is plotted along Y Axis. Curve 624-1 represents initial state resistance while curve 624-2 represents the final state resistance.
[000115] FIG. 6(e) illustrates Memory Write ‗0‘ operation (programming device to state
01) with the device‘s initial condition as state 10. Programming signals in volts are plotted along
Y axis while programming time in milliseconds is plotted along X axis. Curve 622-2 represents
current through the OxRAM device in microamperes.
[000116] Corresponding FIG. 6(e1) illustrates graph of a read operation for the device‘s
initial condition as state 10 to final state 01. Resistance in Megaohms is plotted along Y axis
while read time in milliseconds is plotted along Y Axis. Curve 626-1 represents initial state
resistance while curve 626-2 represents the final state resistance.
[000117] FIG. 6(f) illustrates Memory Write ‗0‘ operation (programming device to state 01)
with the device‘s initial condition as state 00. Programming signals in volts are plotted along Y
axis while programming time in milliseconds is plotted along X axis. Curve 622-3 represents
current through the OxRAM device in microamperes.
[000118] Corresponding FIG. 6(f1) illustrates graph of a read operation for the device‘s
initial condition as state 11 to final state 01. Resistance in Megaohms is plotted along Y axis
18

while read time in milliseconds is plotted along Y Axis. Curve 628-1 represents initial state resistance while curve 628-2 represents the final state resistance.
[000119] Assuming that Memory operation was performed using SLIM bitcell, the same bitcell can also be used for implementing Logic operation and the bitcell can save both memory and logic results. After Memory operation, the NVM device ( interchangeably termed as device herein) can be either in State ‗11‘ or State ‗01‘.
[000120] For logic realization, at V2 node of SLIM bitcell, two pulses of amplitude 5.5 V can be applied and V1 node can be grounded (i.e. P2). SLIM bitcell is capable of performing NOR operation for two 1-bit binary inputs (k, l). These two binary variables act as gate voltages for NMOS (N-type metal-oxide-semiconductor) transistors M1 and M2. When k and l are ‗1‘ , a signal of 10 V can be applied at the gate terminal and for k and l as ‗0‘, the gate terminal can be grounded.
[000121] FIG. 7 shows experimental result for four possible cases of variables ‗k‘ and ‗ l‘ (i.e, k=l=‘0‘; k=‘0‘,l=‘1‘ ; k=‘1‘,l=‘0 ‗; k=l=‘1‘) in accordance with an exemplary embodiment of the present disclosure.
[000122] FIG. 7(a) illustrates experimental results of NOR logic implemented by 2T-1R SLIM bitcell with the NVM device‘s initial state: 11. Gate voltage operands k and l are set at 0, as shown at FIG.7(p) wherein gate voltage (V) at operands k and l is plotted along Y axis and programming time in milliseconds is plotted along X axis. In FIG. 7(a) voltage applied at V2 is plotted along Y axis while programming time in milliseconds is plotted along X axis. Curve 702-1 illustrates current thorough the OxRAM device in nanoamperes.
[000123] FIG. 7(a1) illustrates corresponding device state change wherein resistance in megaohms is plotted along Y axis and read time in milliseconds is plotted along X axis. Curve704-1 shows initial state resistance while curve 704-2 shows final state resistance. As the two curves are same in FIG. (7a1), it illustrates that there is no state change. [000124] FIG. 7(b) illustrates experimental results of NOR logic implemented by 2T-1R SLIM bitcell with the device‘s initial state: 11.Gate voltage operand k is set at 0 while operand l is set at 10 V, as shown at FIG.7(q) wherein gate voltage (V) at operands k and l is plotted along Y axis and programming time in milliseconds is plotted along X axis. In FIG. 7(b) voltage applied at V2 is plotted along Y axis while programming time in milliseconds is plotted along X axis. Curve 702-2 illustrates current thorough the OxRAM device in microamperes.
19

[000125] FIG. 7(b1) illustrates corresponding device state change wherein resistance in
megaohms is plotted along Y axis and read time in milliseconds is plotted along X axis.
Curve706-1 shows initial state (11) resistance while curve 706-2 shows final state (10)
resistance.
[000126] FIG. 7(c) illustrates experimental results of NOR logic implemented by 2T-1R
SLIM bitcell with the device‘s initial state: 11.Gate voltage operand l is set at 0 while operand k
is set at 10 V, as shown at FIG.7(r) wherein gate voltage (V) at operands k and l is plotted along
Y axis and programming time in milliseconds is plotted along X axis. In FIG. 7(c) voltage
applied at V2 is plotted along Y axis while programming time in milliseconds is plotted along X
axis. Curve 702-3 illustrates current thorough the OxRAM device in microamperes.
[000127] FIG. 7(c1) illustrates corresponding device state change wherein resistance in
megaohms is plotted along Y axis and read time in milliseconds is plotted along X axis.
Curve708-1 shows initial state (11) resistance while curve 708-2 shows final state (10)
resistance.
[000128] FIG. 7(d) illustrates experimental results of NOR logic implemented by 2T-1R
SLIM bitcell with the device‘s initial state: 11. Gate voltage operand k is set at 10 while operand
l is also set at 10 V, as shown at FIG.7(S) wherein gate voltage (V) at operands k and l is plotted
along Y axis and programming time in milliseconds is plotted along X axis. In FIG. 7(D) voltage
applied at V2 is plotted along Y axis while programming time in milliseconds is plotted along X
axis. Curve 702-4 illustrates current thorough the OxRAM device in microamperes.
[000129] FIG. 7(d1) illustrates corresponding device state change wherein resistance in
megaohms is plotted along Y axis and read time in milliseconds is plotted along X axis.
Curve710-1 shows initial state (11) resistance while curve 710-2 shows final state (10)
resistance.
[000130] FIG. 7(e) illustrates experimental results of NOR logic implemented by 2T-1R
SLIM bitcell with the device‘s initial state: 01. Gate voltage operand k is set at 0 V while
operand l is also set at 0 V, as shown at FIG.7(p) wherein gate voltage (V) at operands k and l is
plotted along Y axis and programming time in milliseconds is plotted along X axis. In FIG. 7(e)
voltage applied at V2 is plotted along Y axis while programming time in milliseconds is plotted
along X axis. Curve 722-1 illustrates current thorough the OxRAM device in nanoamperes.
20

[000131] FIG. 7(e1) illustrates corresponding device state change wherein resistance in
megaohms is plotted along Y axis and read time in milliseconds is plotted along X axis.
Curve724-1 shows initial state resistance while curve 724-2 shows final state resistance. As the
two curves are same in FIG. (7E1), it illustrates that there is no state change.
[000132] FIG. 7(f) illustrates experimental results of NOR logic implemented by 2T-1R
SLIM bitcell with the device‘s initial state: 01. Gate voltage operand k is set at 0 while operand l
is set at 10, as shown at FIG.7(q) wherein gate voltage (V) at operands k and l is plotted along Y
axis and programming time in milliseconds is plotted along X axis. In FIG. 7(f) voltage applied
at V2 is plotted along Y axis while programming time in milliseconds is plotted along X axis.
Curve 722-2 illustrates current thorough the OxRAM device in microamperes.
[000133] FIG. 7(f1) illustrates corresponding device state change wherein resistance in
megaohms is plotted along Y axis and read time in milliseconds is plotted along X axis.
Curve726-1 shows initial state (01) resistance while curve 726-2 shows final state (00)
resistance.
[000134] FIG. 7(g) illustrates experimental results of NOR logic implemented by 2T-1R
SLIM bitcell with the device‘s initial state: 01. Gate voltage operand k is set at 10 while operand
l is set at 0, as shown at FIG.7(r) wherein gate voltage (V) at operands k and l is plotted along Y
axis and programming time in milliseconds is plotted along X axis. In FIG. 7(g) voltage applied
at V2 is plotted along Y axis while programming time in milliseconds is plotted along X axis.
Curve 722-4 illustrates current thorough the OxRAM device in microamperes.
[000135] FIG. 7(g1) illustrates corresponding device state change wherein resistance in
megaohms is plotted along Y axis and read time in milliseconds is plotted along X axis.
Curve728-1 shows initial state (01) resistance while curve 728-2 shows final state (00)
resistance.
[000136] FIG. 7(h) illustrates experimental results of NOR logic implemented by 2T-1R
SLIM bitcell with the device‘s initial state: 01. Gate voltage operand k is set at 10 while operand
l is also set at 10, as shown at FIG.7(s) wherein gate voltage (V) at operands k and l is plotted
along Y axis and programming time in milliseconds is plotted along X axis. In FIG. 7(H) voltage
applied at V2 is plotted along Y axis while programming time in milliseconds is plotted along X
axis. Curve 722-6 illustrates current thorough the OxRAM device in microamperes.
21

[000137] FIG. 7(h1) illustrates corresponding device state change wherein resistance in
megaohms is plotted along Y axis and read time in milliseconds is plotted along X axis.
Curve730-1 shows initial state (01) resistance while curve 730-2 shows final state (00)
resistance.
[000138] Among the four variable combinations, the OxRAM device exhibits switching to
logic HRS state for k=‘0‘, l=‘1‘; k=‘1‘, l=‘0‘ and k=l=‘1‘.
[000139] FIG. 8 illustrates architecture of a refresh scheme used in order to carry out
multiple consecutive logic operations in accordance with an exemplary embodiment of the
present disclosure.
[000140] As already elaborated (FIG. 4(b)), in order to perform multiple logic operations,
refresh operation needs to be performed to ensure the resistive state of the device lies in absolute
memory states before each logic operation.
[000141] FIG. 8 illustrates architecture of a scheme to implement refresh operation at block
level. There can be bit (called tag-bit) corresponding to each row in a Mat. Initially, if only
memory operation is performed, the tag bit can be initialized to 0. Once the complete row is
utilized for logic implementation, its corresponding tag bit can be set HIGH. Once all bits in the
byte (called tag-byte) are high, refresh scheme can be applied in the selected mat.
[000142] FIGs. 9(a) and 9(b) illustrate exemplary alternate block architectures for proposed
SLIM implementation in accordance with exemplary embodiments of the present disclosure.
[000143] As illustrated, SLIM control unit close to 2T-1R SLIM bitcell array helps in
execution of Memory-and Logic-functions. The CPU communicates with SLIM control unit.
There are three major operations in SLIM programming: Memory- , Logic- and Read- operation.
A 2x2 2T-1R bitcell arrangement is also shown to signal mapping for different possible
operations.
[000144] Table 2 illustrates variable assignment for other Boolean logic operations in
accordance with an exemplary embodiment of the present disclosure.
[000145] Table 2 shows values of operands ‗k‘ and ‗l‘, and Voltages V1, V2, VG1 and VG2
that can be provided as appropriate to a 2T-1R bitcell (as shown in FIG. 3) for implementing
SLIM functionality proposed in this invention.
[000146] Table 3 illustrates a comparison of SLIM architecture proposed with existing
different schemes proposed in literature.
22

[000147] Reference [1] ( E. Linn, R. Rosezin, S. Tappertzhofen, U. Bottger, R. Waser,
"Beyond von Neumann-logic operations in passive crossbar arrays alongside memory
operations", Nanotechnology, vol. 23, no. 30, Aug. 2012 ) implements a sequential logic method
using a complementary resistive switch (CRS) device with 3 steps. It retains only Logic output
and provides for a Destructive Read operation.
[000148] Reference [2] ( T. G. You, Y. Shuai, W. B. Luo, N. Du, D. Burger, I. Skorupa, R.
Hubner, S. Henker, C. Mayr, R. Schuffny, " Exploiting memristive BiFeO 3 bilayer structures
for compact sequential logics ", Adv. Funct. Mater., vol. 24, no. 22, pp. 3357-3365, Jun. 2014)
implements a sequential logic method with a Bipolar resistive switch device (BRS) with three
steps. It retains only Logic output and needs rectifying behavior.
[000149] Reference [3] (S. Gao, M. J. Wang, G. Y. Wang, C. Song, F. Pan,
"Implementation of complete Boolean logic functions in single complementary resistive switch",
Sci. Rep., pp. 15467, Oct. 2015) implements a sequential logic method with one CRS device and
three steps. It retains only Logic output, and has complex integration.
[000150] Reference [4] (Y. Zhou, Y. Li, L. Xu, S. Zhong, H. Sun, X. Miao, "16 Boolean
logics in three steps with two anti-serially connected memristors", Appl. Phys. Lett., vol. 106,
no. 23, Jun. 2015) implements a sequential logic method with two BRS devices and three steps.
It retains only Logic output, and has complex integration.
[000151] Reference [5] (S. Kvatinsky, D. Belousov, S. Liman, G. Satat, N. Wald, E. G.
Friedman, A. Kolodny, U. C. Weiser, "MAGIC—Memristor-aided logic", IEEE Trans. Circuits
Syst. II Express Briefs, vol. 61, no. 11, pp. 895-899, Nov. 2014) implements a MAGIC method
using three BRS devices and two steps. It retains only Logic output, and lacks signal restoration.
[000152] Reference [6] (Z.R. Wang, Y.T. Su, Y. Li, Y.X. Zhou, T.J. Chu, K.C. Chang,
T.C. Chang, T.M. Tsai, S.M. Sze, and X.S. Miao. "Functionally complete Boolean logic in 1T1R
resistive random access memory." IEEE Electron Device Letters 38, no. 2, 179-182, 2017) uses a
1T1R method with two 1T-1R devices and two steps. It retains only Logic output.
[000153] As can be seen, existing LIM strategies focus on realizing a logic function using
memory cell. However the memory cell cannot be used for its storage property and logic
capability as doing one operations destructs the output of preceding operation.
[000154] In contrast to all above, SLIM method proposed herein uses one 2T-1R device as
elaborated above and one step. It retains Logic output and Initial Memory state ‗simultaneously‘.
23

[000155] As can be appreciated from above, existing solutions help in realizing different
logic operations using NVM devices (with two discrete resistance levels: LRS/ HRS) using a certain bitcell configuration and multiple steps, including initialization step, intermediate step or/and final step. This increases the latency for executing a logic operation near memory and kills the prime advantage of overcoming the memory bottleneck. In true sense, the need is to shift some load of logic/arithmetic operations close to memory or inside memory thereby making intelligent memory that can offload some processing burden from processor side and so helps in saving time by reducing memory-processor data transfer cycles.
[000156] However, proposed invention is oriented towards realizing more and more logic
operations using the different bitcell configurations. The stateful logic implementation using memristors/ NVM devices has been the prime area of research in this direction. In discrete memory and logic arrays, there is further data movement between memory arrays and logic arrays. During any logic operation, opcodes are inputs given by the user and the user is interested in reading/ saving the logic output and to drive further logic /arithmetic operation.
[000157] Proposed invention shifts some level of intelligence directly into the memory
array (realized using same memory bitcells) and not a nearby logic array. It uses 2T-1R bitcells
from memory array itself and performs one step logic realization and the result is stored in-situ in
the same bitcell without interfering with the memory state stored prior logic operation.
[000158] Furthermore, proposed invention implements NOR logic operation using standard
one step methodology whereas other implementations/ inventions in literature needs multiple
steps and thus latency is higher and needs a reconfigurable system for true logic realization.
[000159] In previous implementations/ inventions, a bitcell is capable for storing either
memory states or logic outputs. Proposed invention on the other hand discloses a 2T-1R NVM device based bitcell that effectively stores both the states and a single read operation is capable of reading both the states.
[000160] In this manner, proposed invention enables performance of simultaneous logic
and memory operation on the same memory bitcell while preserving the memory state. It discloses a 2T-1R NVM device based bitcell that has capability of performing both memory and logic operations, and of storing both memory and logic state simultaneously in time (clock cycle) and space (silicon area). One read operation is capable of reading both memory and logic state.
24

The 2T-1R NVM device based bitcell proposed is capable of performing logic operation in a
single step, thereby truly helping in resolving von Neumann bottleneck.
[000161] Bitcell disclosed can be further used for realizing multiple logic operation and
addition operation as the basic unit has the capability of implementing universal NOR gate.
Multiple logic operations can be realized if refresh operation is performed on SLIM bitcells
proposed for which previous logic output is no longer required.
[000162] Existing solutions for logic-in-memory realization have an issue of sneak paths
due to absence of selector devices and complex programming strategies are required to mitigate
this issue. Proposed invention uses transistor devices as selector and so resolves the
programming complexity to prevent the sneak paths.
[000163] SLIM architecture proposed reduces the energy of computation significantly by
performing computation in memory module, rather than moving data through large memory
hierarchies to the processor core.
[000164] Proposed invention holds true for all multilevel NVM devices that have the
capability to switch from LRS to HRS states and vice versa with pre-defined scheme.
[000165] Circuit implementation proposed (using 2T-1R NVM device based bitcell) can be
used for realizing other boolean logic operations such as NOT, OR, AND, NAND etc.
[000166] As used herein, and unless the context dictates otherwise, the term ―coupled to‖ is
intended to include both direct coupling (in which two elements that are coupled to each other or
in contact with each other) and indirect coupling (in which at least one additional element is
located between the two elements). Therefore, the terms ―coupled to‖ and ―coupled with‖ are
used synonymously. Within the context of this document terms ―coupled to‖ and ―coupled with‖
are also used euphemistically to mean ―communicatively coupled with‖ over a network, where
two or more devices are able to exchange data with each other over the network, possibly via
one or more intermediary device.
[000167] Moreover, in interpreting both the specification and the claims, all terms should
be interpreted in the broadest possible manner consistent with the context. In particular, the
terms ―comprises‖ and ―comprising‖ should be interpreted as referring to elements, components,
or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps
may be present, or utilized, or combined with other elements, components, or steps that are not
expressly referenced. Where the specification claims refers to at least one of something selected
25

from the group consisting of A, B, C ….and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc.
[000168] While some embodiments of the present disclosure have been illustrated and
described, those are completely exemplary in nature. The disclosure is not limited to the embodiments as elaborated herein only and it would be apparent to those skilled in the art that numerous modifications besides those already described are possible without departing from the inventive concepts herein. All such modifications, changes, variations, substitutions, and equivalents are completely within the scope of the present disclosure. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims.
ADVANTAGESOFTHEINVENTION
[000169] The present disclosure provides for a circuit that has a bitcell that performs both
memory and logic operations, and stores both memory and logic state simultaneously in time
(clock cycle) and space (silicon area).
[000170] The present disclosure provides for a circuit that shifts some level of intelligence
directly into the memory array realized using same memory bitcells and not a nearby logic array.
[000171] The present disclosure provides for a circuit that uses bitcells from memory array
itself, performs one step logic realization, and stores the result in-situ in the same bitcell without
interfering with the memory state stored prior logic operation.
[000172] The present disclosure provides for a circuit that eliminates need for extra
memory bitcell required to store the logic output and using which a single read operation can
provide both memory and logic state outputs, thereby saving one read step and one extra memory
access.
[000173] The present disclosure provides for a circuit that eliminates the need for extra
processing or computational blocks used to realize logic operations, as the memory array itself
can be utilized to perform logic operations.
[000174] The present disclosure provides for a circuit that provides a "cache" memory array
to act as a high speed buffer between conventional memory and CPU.
[000175] The present disclosure provides for a bitcell that stores both Memory and Logic
states even after a system using such a bitcell is shut down.
26

[000176] The present disclosure provides for a circuit that needs only one step (one clock cycle) for logic execution, unlike existing solutions that need two or three steps for realizing a logic
[000177] The present disclosure provides for a circuit that saves considerable amount of silicon area in computing systems
[000178] The present disclosure provides for a circuit that enables latent storage devices like SSDs, USBs, SD cards to also be used for computing without the loss of data that they are already storing.
[000179] The present disclosure provides for a circuit that implements NOR logic operation using standard one step methodology thereby reducing latency.
[000180] The present disclosure provides for a circuit that uses transistor devices as selector thereby resolving programming complexity to prevent sneak paths.
[000181] The present disclosure provides for a circuit with an architecture that reduces the energy of computation significantly by performing computation in memory module, rather than moving data through large memory hierarchies to the processor core.
[000182] The present disclosure provides for a circuit that can be used for all multilevel NVM devices that have the capability to switch from LRS to HRS states and vice versa with pre-defined scheme.
[000183] The present disclosure provides for a circuit that can be used for realizing other boolean logic operations such as NOT, OR, AND, NAND etc.

We Claim:

A circuit comprising a non-volatile memory (NVM) device based bitcell, said bitcell comprising two transistors and a multilevel NVM device that is capable of simultaneously storing memory and logic state such that both logic and Memory states are readable at the same time in a single clock cycle.
2. The circuit of claim 1, wherein said bitcell performs both Memory and Logic operations simultaneously on the same bitcell so as to eliminate extra data movement required between memory and logic arrays.
3. The circuit of claim 1, wherein said NVM device based bitcell is configured as or comprises a cache memory array that acts as a high speed buffer between conventional memory and CPU.
4. The circuit of claim 1, wherein said bitcell enables realization of logic and memory functions simultaneously in space/silicon area and time/clock cycles.
5. The circuit of claim 1, wherein said NVM device has four or more distinct resistive states, said states being Memory Low Resistance States (LRS states) and Memory High Resistance States (HRS states), and wherein memory region comprises the LRS and HRS states that are sub-categorized as Logic '1' and Logic '0'.
6. The circuit of claim 1, wherein during a Memory Write operation, initially a read operation is performed.
7. The circuit of claim 1, wherein in case the NVM device is in the same state as it needs to be programmed, no programming signal is applied, and wherein if initial state of NVM device is different, at least one programming signal is applied.
8. The circuit of claim 1, wherein for Memory Write '1', said NVM device is programmed to state ' 11', and for Memory Write '0', said device is programmed to state '01'.
9. The circuit of claim 1, wherein during memory write operation, said two transistors (Ml and M2) are kept ON, and wherein during logic operation, at least one predefined programming signal is applied at terminals (VI and V2) of said bitcell and input variables act as gate control signals for said two transistors, and wherein said NVM device is programmed to a corresponding logic state depending on different combinations of said input variables.

10. The circuit of claim 1, wherein multiple logic operations are realizable if refresh operation is performed on said bitcell for which previous logic output is no longer required.