0001] The present disclosure relates to the field of semiconductor devices. In particular,
the present disclosure provides a circuit for noise mitigation.
BACKGROUND
[0002] The background description includes information that may be useful in
understanding the present invention. It is not an admission that any of the information provided
herein is prior art or relevant to the presently claimed invention, or that any publication specifically
or implicitly referenced is prior art.
[0003] In various biomedical applications, such as, neural signal recording, on-chip bioimpedance spectroscopy, bio-signal recording, cardiac electrical impedance tomography (CEIT)
and scanning ion-conductance microscopy (SICM), and other similar applications precise
electrical signals comprising minimal noise are required for delivering optimal performance and
acquiring accurate results.
[0004] In most of the biomedical equipment, analog circuits, such as, voltage amplifiers,
trans-conductance amplifiers, trans-impedance amplifiers, filters, and other similar circuits are
incorporated within the equipment. But, the noise generated from the analog circuits, while
operating the biomedical equipment, gets mixed with the original signal, which may result in
reduced efficiency of the equipment and an erroneous signal as output, and, moreover, rendering
such equipment unfit for biomedical purposes, where a high accuracy is required.
[0005] Hence, a low noise operation is required to prevent the signal conditioned by the
analog circuits, incorporated within the equipment, from being corrupted. A technique of operating
metal–oxide–semiconductor (MOS) devices in subthreshold region and sizing them with larger
area is found to be useful for mitigation of the noise, as fortunately, during such operations, high
trans-conductance can be achieved, which aids in mitigation of the noise present in the original
signal. However, the technique can reduce noise only to a limited extent, owing to various
limitations in increasing gate trans-conductance (gm) and, further, a (trans-conductance (gm)/
current (Id)) ratio of the MOS devices.
3
[0006] There is, therefore, a need in the art to provide an effective and accurate circuit to
overcome the above mentioned problems, and provide a means for mitigating noise from the
conditioned signal.
OBJECTS OF THE PRESENT DISCLOSURE
[0007] Some of the objects of the present disclosure, which at least one embodiment herein
satisfies are as listed herein below.
[0008] It is an object of the present disclosure to provide a circuit for reducing noise from
an input signal.
[0009] It is another object of the present disclosure to provide a circuit with high transconductance.
[0010] It is another object of the present disclosure to provide a circuit for reducing noise
power spectral density.
[0011] It is another object of the present disclosure to provide a circuit with reduced
thermal noise.
[0012] It is another object of the present disclosure to provide a circuit for conserving
electrical power, by avoiding its wastage.
[0013] It is another object of the present disclosure to provide a cost-effective, efficient,
and accurate circuit.
[0014] These and other objects of the present invention will become readily apparent from
the following detailed description taken in conjunction with the accompanying drawings.
SUMMARY
[0015] The present disclosure relates to the field of semiconductor devices. In particular,
the present disclosure provides a circuit for noise mitigation.
[0016] An aspect of the present disclosure pertains to a circuit for noise control, the circuit
comprising: a noise control unit comprising: a Metal Oxide Semiconductor (MOS) transistor
comprising a body terminal, a gate terminal, a source terminal, and a drain terminal, wherein the
source terminal is supplied with a biasing voltage, and the drain terminal is grounded; and a
capacitor electrically coupled to the transistor, wherein the capacitor configured between the body
terminal and the gate terminal of the transistor; an input terminal electrically coupled to a front
4
end of the noise control unit, and configured to receive an input signal from an electric power
source or real time biological signal received via sensors; an output terminal electrically coupled
to a second end of the noise control unit to facilitate transmission of a filtered signal, wherein the
output terminal is configured at the drain terminal of the transistor, wherein, the circuit is
configured to control noise associated with the input signal, based on an increase in transconductance due to the capacitor, and correspondingly provide the filtered signal.
[0017] In an aspect, the input signal may be applied to the gate terminal of the transistor
and, through the capacitor, to the bulk terminal of the transistor, in the circuit.
[0018] In an aspect, the capacitor may be having a pre-defined capacitance value.
[0019] In an aspect, the circuit may comprise a resistor having a pre-defined resistance or
can be load or tail transistors, wherein one terminal of the resistor being attached to the drain
terminal of the transistor, and other terminal of the resistor being grounded.
[0020] In an aspect, the transistor may be any or a combination of N-type transistor and Ptype transistor.
[0021] In an aspect, the circuit may be configured to reduce noise power density of the
input signal.
[0022] In an aspect, the circuit may be configured to control signal-to-noise ratio
associated with the input signal.
[0023] In an aspect, the input signal may comprise any or a combination of analog signal
and digital signal.
[0024] In an aspect, the electric power source may comprise any or a combination of
voltage source, current source, dependent source, and independent source.
[0025] In an aspect, the circuit may provide a fast response time.
BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The accompanying drawings are included to provide a further understanding of the
present disclosure, and are incorporated in and constitute a part of this specification. The drawings
illustrate exemplary embodiments of the present disclosure and, together with the description,
serve to explain the principles of the present disclosure.
[0027] The diagrams are for illustration only, which thus is not a limitation of the present
disclosure, and wherein:
5
[0028] FIGs. 1A and 1B illustrate exemplary diagram of the proposed circuit to illustrate
its overall working in accordance with an embodiment of the present disclosure.
[0029] FIG. 2 illustrates exemplary capacitance equivalent of the proposed circuit in
accordance with an exemplary embodiment of the present disclosure.
[0030] FIG. 3 illustrates exemplary small signal model equivalent of the proposed circuit
in accordance with an exemplary embodiment of the present disclosure.
DETAILED DESCRIPTION
[0031] In the following description, numerous specific details are set forth in order to
provide a thorough understanding of embodiments of the present invention. It will be apparent to
one skilled in the art that embodiments of the present invention may be practiced without some of
these specific details.
[0032] If the specification states a component or feature “may”, “can”, “could”, or “might”
be included or have a characteristic, that particular component or feature is not required to be
included or have the characteristic.
[0033] As used in the description herein and throughout the claims that follow, the
meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates
otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on”
unless the context clearly dictates otherwise.
[0034] The recitation of ranges of values herein is merely intended to serve as a shorthand
method of referring individually to each separate value falling within the range. Unless otherwise
indicated herein, each individual value is incorporated into the specification as if it were
individually recited herein. All methods described herein can be performed in any suitable order
unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and
all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments
herein is intended merely to better illuminate the invention and does not pose a limitation on the
scope of the invention otherwise claimed. No language in the specification should be construed as
indicating any non-claimed element essential to the practice of the invention.
[0035] Groupings of alternative elements or embodiments of the invention disclosed herein
are not to be construed as limitations. Each group member can be referred to and claimed
individually or in any combination with other members of the group or other elements found
6
herein. One or more members of a group can be included in, or deleted from, a group for reasons
of convenience and/or patentability. When any such inclusion or deletion occurs, the specification
is herein deemed to contain the group as modified thus fulfilling the written description of all
groups used in the appended claims.
[0036] Exemplary embodiments will now be described more fully hereinafter with
reference to the accompanying drawings, in which exemplary embodiments are shown. This
invention may, however, be embodied in many different forms and should not be construed as
limited to the embodiments set forth herein. These embodiments are provided so that this
disclosure will be thorough and complete and will fully convey the scope of the invention to those
of ordinary skill in the art. Moreover, all statements herein reciting embodiments of the invention,
as well as specific examples thereof, are intended to encompass both structural and functional
equivalents thereof. Additionally, it is intended that such equivalents include both currently known
equivalents as well as equivalents developed in the future (i.e., any elements developed that
perform the same function, regardless of structure).
[0037] The present disclosure relates to the field of semiconductor devices. In particular,
the present disclosure provides a circuit for noise mitigation.
[0038] According to an aspect the present disclosure pertains to a circuit for noise control,
the circuit comprising: a noise control unit comprising: a Metal Oxide Semiconductor (MOS)
transistor comprising a body terminal, a gate terminal, a source terminal, and a drain terminal,
wherein the source terminal is supplied with a biasing voltage, and the drain terminal is grounded;
and a capacitor electrically coupled to the transistor, wherein the capacitor configured between the
body terminal and the gate terminal of the transistor; an input terminal electrically coupled to a
front end of the noise control unit, and configured to receive an input signal from an electric power
source; an output terminal electrically coupled to a second end of the noise control unit to facilitate
transmission of a filtered signal, wherein the output terminal is configured at the drain terminal of
the transistor, wherein, the circuit is configured to control noise associated with the input signal,
based on an increase in trans-conductance due to the capacitor, and correspondingly provide the
filtered signal.
[0039] In an embodiment, the input signal can be applied to the gate terminal of the
transistor and, through the capacitor, to the bulk terminal of the transistor, in the circuit.
[0040] In an embodiment, the capacitor can be having a pre-defined capacitance value.
7
[0041] In an embodiment, the circuit can include a resistor having a pre-defined resistance
or can be load or tail transistors, wherein one terminal of the resistor being attached to the drain
terminal of the transistor, and other terminal of the resistor being grounded.
[0042] In an embodiment, the transistor can be any or a combination can be load or tail
transistors.
[0043] In an embodiment, the circuit can be configured to reduce noise power density of
the input signal.
[0044] In an embodiment, the circuit can be configured to control signal-to-noise ratio
associated with the input signal.
[0045] In an embodiment, the input signal can include any or a combination of analog
signal and digital signal.
[0046] In an embodiment, the electric power source can include any or a combination of
voltage source, current source, dependent source, and independent source.
[0047] In an embodiment, the circuit can provide a fast response time.
[0048] FIGs. 1A and 1B illustrate exemplary diagram of the proposed circuit to illustrate
its overall working in accordance with an embodiment of the present disclosure.
[0049] As illustrated, in an embodiment, FIG. 1A illustrates an exemplary block diagram
of the proposed circuit 100, and FIG. 1B illustrates an exemplary circuit diagram of the proposed
circuit 100.
[0050] In an embodiment, the block diagram of the proposed circuit 100 for controlling
noise, can include an input terminal 110, a noise control unit 120, and an output terminal 130. In
another embodiment, the noise control unit 120 can include a Metal Oxide Semiconductor (MOS)
transistor 122 comprising a body terminal B, a gate terminal G, a source terminal S, and a drain
terminal D, a capacitor 124 having pre-defined capacitance value (C), and a resistor 126 having
pre-defined resistance (R). The transistor 122 can be any or a combination of N-type transistor and
P-type transistor, and the capacitor 124 and the resistor 126 can be electrically coupled to the
transistor 122, such that one end of the capacitor 124 can be attached to the body terminal B of the
transistor 122 and other end of the capacitor 124 can be attached to the gate terminal G of the
transistor 122, and, simultaneously, one terminal of the resistor 126 can be attached to the drain
terminal D of the transistor 122, and other terminal of the resistor 126 can be grounded.
8
[0051] In an illustrative implementation, a biasing voltage (VDD) can be applied at the
source terminal S of the transistor 122, where the biasing voltage (VDD) can be supplied through
any or a combination of an independent voltage source and a dependent voltage source.
[0052] . In an embodiment, such configuration of the transistor 122 and the capacitor 124
can enable reduction of thermal noise associated with the proposed circuit 100.
[0053] In an embodiment, an input signal can be fed from an electric power source (not
shown) to the proposed circuit 100 through the input terminal 110 of the proposed circuit 100,
where the input terminal 110 can be configured with the gate terminal G of the transistor 122, and
can be attached to the body terminal B of the transistor 122 through the capacitor 124. In an
illustrative embodiment, the input signal can include any or a combination of analog signal and
digital signal, and the electric power source can include, but not limited to, any or a combination
of voltage source, current source, dependent source, and independent source.
[0054] In an illustrative implementation, the input signal (Vi) can be transmitted from the
input terminal 110 to the noise control unit 120, where the input signal (Vi) can be branched, and
further, a part of the input signal (Vi) can be fed to the transistor 122 through the gate terminal G
of the transistor 122, and other part of input signal (Vi) can be fed to the capacitor 124, which
further, can be transmitted to the body terminal B of the transistor 122. In an embodiment, noise
associated with the input signal (Vi), can be mitigated through the proposed circuit 100. The
proposed circuit 100 can operate, resulting in an increase in trans-conductance due to the presence
of the capacitor 124, which can result in mitigation of the noise associated with the input signal
(Vi) more efficiently, and correspondingly facilitating a filtered signal (Vout), which can have
minimal noise.
[0055] In an embodiment, devices and techniques present in the market can provide some
trans-conductance, which can aid in mitigation of the noise present in the input signal. However,
the said devices and techniques can reduce noise only to a limited extent, owing to various
limitations in increasing gate trans-conductance (gm).
[0056] In an embodiment, noise power spectral density can be defined as the power spectral
density of noise, or the noise power per unit of bandwidth, and can have dimensions of power over
frequency, whose SI unit can be given as watts per hertz, or, watt-seconds. In an embodiment,
noise power spectral density (𝑉𝑛
2
) resulting from the said devices can be given by the formula –
9
𝑉𝑛
2 =
𝑖𝑛
2
𝑔𝑚
2
-where, 𝑖𝑛 can represent an input current.
Here, it can be observed that the noise power spectral density (𝑉𝑛
2
) is inversely proportional to square of
the trans-conductance (𝑔𝑚) offered by the devices.
[0057] In an embodiment, the proposed circuit 100 can offer an effective trans-conductance
of (𝑔𝑚 + 𝑘1𝑔𝑚𝑏), which can be due to presence of the capacitor 124 in the proposed circuit 100,
where 𝑘1can be a scale-factor, and can be expressed as 𝐶𝐵
𝐶𝑇
, such that 𝐶𝐵 can be capacitance value
of the capacitor 124, 𝐶𝑇 can be total capacitance associated the body terminal of the transistor 122,
𝑔𝑚 can be gate transconductance of transistor 122 and 𝑔𝑚𝑏 is the bulk transconductance of
transistor 122. So, noise power spectral density (𝑉𝑛
2
) resulting from the proposed circuit 100 can be
given by the formula –
𝑉𝑛
2 =
𝑖𝑛
2
(𝑔𝑚+𝑘1𝑔𝑚𝑏)
2
Here, it can be observed that the noise power spectral density (𝑉𝑛
2
) is inversely proportional to square of
the trans-conductance (𝑔𝑚 + 𝑘1𝑔𝑚𝑏). In an embodiment, it can be appreciated that the trans −
conductance (𝑔𝑚 + 𝑘1𝑔𝑚𝑏) > 𝑔𝑚 > 𝑔𝑚𝑏, hence, the noise power spectral density (𝑉𝑛
2
) of the
proposed circuit 100 can be far less than the said devices and the said techniques. Hence, it can be said
that the proposed circuit 100 can facilitate improved noise reduction, and further, provide the
filtered signal with improved signal-to-noise (SNR) ratio.
[0058] In an embodiment, the output terminal 130 of the proposed circuit 100 can be
electrically coupled to a second end of the noise control unit 120, such that the output terminal 130
can be configured at the drain terminal D of the transistor 122. In output terminal 130 can be
configured to transmit the filtered signal (Vout) to other devices.
[0059] FIG. 2 illustrates exemplary capacitance equivalent of the proposed circuit 100 in
accordance with an exemplary embodiment of the present disclosure.
[0060] As illustrated, in an embodiment, FIG. 2 illustrates exemplary capacitance
equivalent of the proposed circuit 100. The exemplary capacitance equivalent can include a
capacitor CBS between a first node N1and a source terminal S of a transistor 122, and a capacitor
CBD between the first node N1and a drain terminal D of the transistor 122. A capacitor CBG
connected in parallel a capacitor CB can be there between a gate terminal G of the transistor 122
10
and the first node N1. The exemplary capacitance equivalent can also include a capacitor CBSub
between the first node N1 and a body terminal B (also, represented as Substrate Sub) of the
transistor 122. In an embodiment, a biasing voltage (VDD) can be applied at the source terminal S
of the transistor 122 to drive the transistor 122 in an operating region like sub-threshold region.
[0061] In an embodiment, due to said capacitance equivalent, the proposed circuit 100 can
provide a large value of trans-conductance (𝑔𝑚 + 𝑘1𝑔𝑚𝑏), which can act as a means to reduce
noise from an input signal that can be applied at the gate terminal G, and at the body terminal B/
Sub, through the capacitor 124 having a capacitance value of CB.
[0062] FIG. 3 illustrates exemplary small signal model equivalent of the proposed circuit
in accordance with an exemplary embodiment of the present disclosure.
[0063] As illustrated, in an embodiment, FIG. 3 illustrates exemplary small signal model
equivalent of the proposed circuit 100. In an embodiment, when an input voltage signal (Vin) is
applied, through an input terminal 110, between a gate terminal G and a source terminal S of a
transistor 122, which is incorporated in the proposed circuit 100, then after removing noise from
the signal (Vin), the proposed circuit 100 can provide a filtered signal (Vout). In an illustrative
implementation, the filtered signal (Vout) can be received from an output terminal 130, which can
be located between the source terminal S and a drain terminal D of the transistor 122.
[0064] In an illustrative embodiment, in case of minor fluctuations in the input voltage
signal (Vin), the fully charged capacitor 124 can provide an additional voltage, and hence,
removing the fluctuations, and, further, providing corresponding filtered voltage signal. In another
illustrative embodiment, in case of minor fluctuations in the input voltage signal (Vin), the
capacitor 124 can enable shunting of spikes, or transient noise present in the input voltage signal
(Vin), and hence, removing the fluctuations, and, further, providing corresponding filtered voltage
signal.
[0065] Thus, it will be appreciated by those of ordinary skill in the art that the diagrams,
schematics, illustrations, and the like represent conceptual views or processes illustrating systems
and methods embodying this invention. Those of ordinary skill in the art further understand that
the exemplary circuit, module, processes, methods, and/or operating systems described herein are
for illustrative purposes and, thus, are not intended to be limited to any particular named.
[0066] As used herein, and unless the context dictates otherwise, the term "coupled to" is
intended to include both direct coupling (in which two elements that are coupled to each other
11
contact each other) and indirect coupling (in which at least one additional element is located
between the two elements). Therefore, the terms "coupled to" and "coupled with" are used
synonymously. Within the context of this document terms "coupled to" and "coupled with" are
also used euphemistically to mean “communicatively coupled with” over a network, where two or
more devices are able to exchange data with each other over the network, possibly via one or more
intermediary device.
[0067] It should be apparent to those skilled in the art that many more modifications
besides those already described are possible without departing from the inventive concepts herein.
The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended
claims. Moreover, in interpreting both the specification and the claims, all terms should be
interpreted in the broadest possible manner consistent with the context. In particular, the terms
“comprises” and “comprising” should be interpreted as referring to elements, components, or steps
in a non-exclusive manner, indicating that the referenced elements, components, or steps may be
present, or utilized, or combined with other elements, components, or steps that are not expressly
referenced. Where the specification claims refers to at least one of something selected from the
group consisting of A, B, C …. and N, the text should be interpreted as requiring only one element
from the group, not A plus N, or B plus N, etc.
[0068] While the foregoing describes various embodiments of the invention, other and
further embodiments of the invention may be devised without departing from the basic scope
thereof. The scope of the invention is determined by the claims that follow. The invention is not
limited to the described embodiments, versions or examples, which are included to enable a person
having ordinary skill in the art to make and use the invention when combined with information
and knowledge available to the person having ordinary skill in the art.
ADVANTAGES OF THE INVENTION
[0069] The present disclosure provides a circuit for removing noise from an input signal.
[0070] The present disclosure provides a circuit with high trans-conductance.
[0071] The present disclosure provides a circuit for reducing noise power spectral density.
[0072] The present disclosure provides a circuit with reduced thermal noise.
[0073] The present disclosure provides a circuit for conserving electrical power, by
avoiding its wastage.
12
[0074] The present disclosure provides a circuit that is efficient, reliable, and costeffective.

We Claim:

1. A circuit for noise control, the circuit comprising:
a noise control unit comprising:
a Metal Oxide Semiconductor (MOS) transistor comprising a body
terminal, a gate terminal, a source terminal, and a drain terminal, wherein the source
terminal is supplied with a biasing voltage, and the drain terminal is grounded; and
a capacitor electrically coupled to the transistor, wherein the capacitor
configured between the body terminal and the gate terminal of the transistor;
an input terminal electrically coupled to a front end of the noise control unit, and
configured to receive an input signal from an electric power source;
an output terminal electrically coupled to a second end of the noise control unit to
facilitate transmission of a filtered signal, wherein the output terminal is configured
between the source terminal and the drain terminal of the transistor,
wherein, the circuit is configured to control noise associated with the input
signal, based on an increase in trans-conductance due to the capacitor, and correspondingly
provide the filtered signal.
2. The circuit as claimed in claim 1, wherein the input signal is applied to the gate terminal
of the transistor and, through the capacitor, to the bulk terminal of the transistor, in the
circuit.
3. The circuit as claimed in claim 1, wherein the capacitor is having a pre-defined capacitance
value.
4. The circuit as claimed in claim 1, wherein the circuit comprises a resistor or transistor or
load having a pre-defined resistance, wherein one terminal of the resistor being attached to
the drain terminal of the transistor, and other terminal of the resistor being grounded.
5. The circuit as claimed in claim 1, wherein the transistor is any or a combination of N-type
transistor and P-type transistor.
6. The circuit as claimed in claim 1, wherein the circuit is configured to reduce noise power
density of the input signal.
7. The circuit as claimed in claim 1, wherein the circuit is configured to control signal-tonoise ratio associated with the input signal.
14
8. The circuit as claimed in claim 1, wherein the input signal comprises any or a combination
of analog signal and digital signal.
9. The circuit as claimed in claim 1, wherein the electric power source comprises any or a
combination of voltage source, current source, dependent source, and independent source.
10. The circuit as claimed in claim 1, wherein the circuit provides a fast response time.