CIRCUIT FOR SUPRESSING RINGING IN HIGH SPEED CMOS OUTPUT BUFFER DRIVING TRANSMISSION LINE LOAD
Field of invention
The present invention relates to integrated circuit output buffers and, more specifically, to variable impedance output buffers for improving an output of such buffers during state transitions.
Background of the invention
The communication of digital signals over wires and cables gives rise to a number of problems. Some of these problems arise when communicating information between IC's or even over the short distances traversed on a single circuit board. In fact, in the context of the high speed IC's with rise / fall times of less than one nanosecond, transmission line effects are so severe that signal lines of more than one inch must be treated as transmission lines. Thus, high speed output buffers must be designed to consider these transmission line effects.
FIGURE 1 illustrates an output buffer coupled to a transmission line. At the output stage of an integrated circuit, an output buffer is typically needed to transfer signals to the signal lines. The term "buffer" may also refer to an entire 1C dedicated solely to driving the signal lines. An output buffer 16 coupled to a transmission line 14 is illustrated in FIGURE 1. The transmission line has characteristic impedance Z0. The output buffer 16 includes a pull up device and a pull down device, which exhibits output impedance RLH 106, when the output undergoes a low-to-high transition, and output impedance RHL 108 when undergoing a high-to-low transition. These impedances are, for the most part, contributed by pull-up and pull-down transistors at the output stage of the buffer.
FIGURE 2 is a schematic diagram of a driver which may be employed in one of the output buffer devices 16, shown in FIGURE 1.
FIGURE 3A illustrates the output voltage of an output buffer 16 as it undergoes an output transition from a high state to a low state. The output waveform exhibits an intermediate step before falling to the low state. This step is caused by the fact that for a high-to-low transition, the resistor RHL in series with the characteristic impedance Z0 acts as a voltage divider. The height of the step depends on the relative values of RHL and Z0, and the length of the step depends upon the round trip electrical delay of the output signal through the transmission line. For high speed data transfer with rise / fall times less than Ins, the impedance of output buffers are intentionally made much smaller than transmission line impedance. The low output driver impedance helps to achieve plateau level near to the low logic level which helps to achieve fall time specifications. In the open circuit context, one skilled in the art can easily understand that the transition of the output signal generated by the output buffer, keeping RHL less than the characteristic impedance of the transmission line, may result in severe undershoots and overshoots related to the desired steady state value.
FIGURE 3B illustrates the output voltage of an output buffer as it undergoes an output transition from a high state to a low state. FIGURE 3B shows the waveform at the output node 28 keeping RHL much less than the transmission line impedance. In addition the problems associated \vith ringing like over voltage, threshold crossing etc. may degrade the performance of the system.
Accordingly, there is a need to provide an improved output buffer that eliminates the ringing effects and at the same time meets the high speed specifications.
Therefore, there is a need of an output buffer module providing constant output impedance for driving transmission line loads in the integrated circuits. Moreover, the module further improves the output of the integrated circuits during state transitions
Summary of the invention
It an object of the present invention to provide an output buffer circuit for improving an output of the buffer during state transitions.
To achieve said objectives, the present invention provides an output buffer circuit for suppressing ringing during state transitions by generating a variable output impedance proportional to a transmission line impedance, said buffer circuit comprising:
a first impedance control circuit generating a first control signal, said control circuit receiving a first input from an output terminal and a second input from an input data signal;
a pull down NMOS transistor having a drain connected to said output terminal, a source connected to a ground voltage, and a gate connected to an output of said first impedance control circuit, said NMOS transistor receiving said first control signal for adjusting its impedance;
a second impedance control circuit generating a second control signal, said second control circuit receiving a first input from said output terminal and a second input from an second input data signal; and
a pull up PMOS transistor having a drain connected to said output terminal, a source connected to a supply voltage, and a gate connected to an output of said second impedance control circuit, said PMOS transistor receiving said second control signal for adjusting its impedance.
Further, the present invention provides an impedance control circuit generating a control signal for varying an impedance of a output node comprising:
a first PMOS transistor having a source connected to a supply voltage, a drain connected to a control signal, and a gate connected to a data signal through an inverter;
a second PMOS transistor having a source connected to the control signal, a drain connected to a ground voltage, and a gate connected to an output voltage node;
a first NMOS transistor having a drain connected to the control signal, a source connected to a ground terminal, and a gate connected to the data signal through said inverter; and
a second NMOS transistor having a drain connected to the output voltage node, a source connected to the ground terminal, and a gate connected to the control signal.
Further, the present invention provides an impedance control circuit generating a control signal for varying an impedance of a output node comprising:
a first PMOS transistor having a source connected to a supply voltage, a drain connected to a control signal and a gate connected to a first data input through an inverter;
a second PMOS transistor having a source connected to the control signal, a drain connected to a ground voltage and a gate connected to an output node;
a first NMOS transistor having a drain connected to the output node, a source connected to a virtual node, and a gate connected to a second data input; and
a second NMOS transistor having a drain connected to the source of said first NMOS transistor through said virtual node, a source connected to the ground voltage, and a gate connected to the control signal.
Further, the present invention provides an impedance control circuit generating a control signal for varying an impedance of a output node comprising:
a first NMOS transistor having a drain connected to a supply voltage, a source connected to a control signal, and a gate connected to a first data signal,
a first PMOS transistor having a source connected to the control signal, a drain connected to a ground voltage, and a gate connected to an output node,
a second NMOS transistor having a drain connected to the control signal, a source connected to the ground voltage, and a gate connected to a second data signal; and
a third NMOS transistor having a drain connected to the output node, a source connected to the ground voltage, and a gate connected to the control signal
Further, the present invention provides an impedance control circuit generating a control signal for varying an impedance of a output node comprising:
a first NMOS transistor having a drain connected to a supply voltage, a source connected to a control signal, and a gate connected to a first data signal;
a first PMOS transistor having a source connected to the control signal, a drain connected to a ground voltage, and a gate connected to an output node,
a second NMOS transistor having a drain connected to the output node, a source connected to a virtual node, and a gate connected to a second data signal; and
a third NMOS transistor having a drain connected to the source of the second NMOS transistor through said virtual node, a source connected to the ground voltage, and a gate connected to the control signal.
Brief Description of the drawings
The present invention is described with the help of accompanying drawings.
FIGURE 1 illustrates an output buffer coupled to a transmission line.
FIGURE 2 is a schematic diagram of a driver which may be employed in one of the output buffer devices 16, shown in FIGURE 1.
FIGURE 3A illustrates the output voltage of an output buffer as it undergoes an output transition from a high state to a low state.
FIGURE 3B illustrates the output voltage of an output buffer affected by ringing as it undergoes an output transition from a high state to a low state.
FIGURE 4 is a block diagram of an output buffer circuit according to the present invention.
FIGURE 5 illustrates a block diagram of the proposed control circuit.
FIGURE 6 is the schematic diagram of an output buffer pull down device according to one embodiment of the present invention.
FIGURE 7 is an alternate schematic diagram of the previous embodiment of output buffer pull down devices.
FIGURE 8 is the schematic diagram of another embodiment of the output buffer pull down device
FIGURE 9 is the alternate schematic diagram of the previous embodiment of output buffer pull down devices,
Detailed Description of the Invention
The preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the preferred embodiments. The present invention can be modified in various forms. The preferred embodiments of the present invention are only provided to explain more clearly the present invention to the ordinarily skilled in the art of the present invention. In the accompanying drawings, like reference numerals are used to indicate like components.
The present invention provides a modified CMOS output buffer to suppress ringing at the output of a high speed CMOS output buffer.
Accordingly, the present invention operates as follows to avoid the above stated ringing problem. Referring to FIGURE 4, the impedance of output buffer is set relatively low with respect to transmission line impedance during the initial transition period. The impedance is then dynamically controlled during the final transition period where the ringing occurs
FIGURE 4 is a block diagram of the output buffer 16 coupled to the transmission line 14 at node 28. An NMOS transistor 34 is a pull down driver coupled to the node 28, a ground voltage and an output of the impedance control circuit 42. The impedance control circuit 42 includes a pair of inputs coupled to the output node 28 and a data signal ND. The impedance control circuit 42 generates a control signal which is subsequently provided to the gate of the NMOS transistor 34. The control signal varies the impedance of the pull down transistor 34, where the ringing occurs. More particularly, if the voltage at the output node 28 decreases beyond the ground voltage, the control circuit 42 operates to increases the impedance of the NMOS driver to offset the decrease in impedance of pull-down driver that would otherwise occur if the gate of the NMOS transistor was connected directly to the input data signal ND. The control circuit 42 is a feedback path between the output node 28 and the gate of the NMOS transistor 34. When ND switches from a High to Low logic level, the control circuit 42 passes ND to the gate of the NMOS transistor 34, those skilled in the art will understand that the output impedance may be made relatively small through the use of a low impedance component at the output buffer stage. When the NMOS transistor 34 is fully switched ON, the pull down device conducts current for discharging output node 28. As the voltage of the output node 28 decreases towards a ground voltage, the control circuit 42 decreases the voltage magnitude of control signal and the impedance of pull down transistor increases.
FIGURE 5 is a block level representation of the impedance control circuit 42 as shown in FIGURE 4. The pull up device 36 is controlled by the data signal ND and a pull down device 38 is controlled by the PAD signal 28. The pull up / pull down devices of the present invention can be implemented in various alternate forms and are not limited by the way of examples and embodiments shown in the drawing.
FIGURE 6 illustrates one embodiment of the impedance control circuit 42. In FIGURE 6, the control circuit 42 includes a PMOS transistor 36 and 38, an NMOS transistor 40 and an inverting device 30. The gate of the PMOS transistor 36 is coupled to the supply node Vdde, a data signal ND through the inverting device 30 and the control signal 29. The gate of the PMOS transistor 38 is coupled to the ground node gnde, an output node

28 and the control signal 29. The NMOS transistor 40 is coupled to the ground node gnde, the data signal ND through an inverting device 30 and the control signal 29.
When the pull down driver is enabled, the data signal ND is at a high logic level, now the PMOS transistor 36 is ON and the NMOS transistor 40 is OFF and the control circuit 42 biases the pull down transistor 34 to a high logic level. As the voltage at the output node 28 decreases the PMOS transistor 38 of the control circuit 42 is gradually turned ON and the voltage of the control signal 29 decreases to increase the impedance of the pull down transistor 34, When the pull down driver is disabled ND is at a low logic level and the NMOS transistor 40 is turned ON to bring the control signal 29 to a low logic level, thus turning off the pull down driver.
FIGURE 7 is an alternative embodiment of the present invention shown in FIGURE 6. The only difference is that the NMOS transistor 40 is removed from the control circuit 42 and added in series with the pull down transistor 34, to disable the pull down driver, when the data signal ND is at a low logic level. A complementary structure can easily be implemented for the pull up driver 32.
FIGURE 8 illustrates another embodiment of the impedance control circuit 42. The PMOS transistor 36 with an inverted ND signal as input has been replaced by an NMOS transistor with an ND data signal as its input. The drawback in this embodiment is that the initial drive of the pull down driver 34 is reduced from the voltage Vdde to (Vdde-Vm) resulting in an increased driver area.
FIGURE 9 is an alternative embodiment of the proposed previous architecture. The only difference is that the NMOS transistor 40 is removed from the control circuit 42 and added in series with the pull down transistor 34, to disable the pull down driver, when the data signal ND is at a low logic level. A complementary structure can easily be implemented for pull up driver 32.
Although the disclosure of circuit has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the disclosure.

We claim:
1) An output buffer circuit for suppressing ringing during state transitions by
generating a variable output impedance proportional to a transmission line
impedance, said buffer circuit comprising:
a first impedance control circuit generating a first control signal, said control circuit receiving a first input from an output terminal and a second input from an input data signal;
a pull down NMOS transistor having a drain connected to said output terminal, a source connected to a ground voltage, and a gate connected to an output of said first impedance control circuit, said NMOS transistor receiving said first control signal for adjusting its impedance;
a second impedance control circuit generating a second control signal, said second control circuit receiving a first input from said output terminal and a second input from an second input data signal; and
a pull up PMOS transistor having a drain connected to said output terminal, a source connected to a supply voltage, and a gate connected to an output of said second impedance control circuit, said PMOS transistor receiving said second control signal for adjusting its impedance.
2) The output buffer circuit as claimed in claim 1, wherein said first impedance
control circuit operatively increases an impedance of said NMOS transistor, when
a voltage at the output terminal decreases beyond a ground voltage.
3) The output buffer circuit as claimed in claim 1, wherein said first impedance
control circuit passes the first input to the gate of said NMOS transistor, when the
first input switches from a high logic level to a low logic level.
4) An impedance control circuit generating a control signal for varying an impedance of an output node comprising:
a first PMOS transistor having a source connected to a supply voltage, a drain connected to a control signal, and a gate connected to a data signal through an inverter;
a second PMOS transistor having a source connected to the control signal, a drain connected to a ground voltage, and a gate connected to an output voltage node,
a first NMOS transistor having a drain connected to the control signal, a source connected to a ground terminal, and a gate connected to the data signal through said inverter, and
a second NMOS transistor having a drain connected to the output voltage node, a source connected to the ground terminal, and a gate connected to the control signal
5) The impedance control circuit as claimed in claim 4, wherein said first PMOS
transistor is in ON state, when the data signal is at a high logic level.
6) The impedance control circuit as claimed in claim 4, wherein said first NMOS
transistor is in OFF state, when the data signal is at a high logic level.
7) An impedance control circuit generating a control signal for varying an
impedance of an output node comprising:

a first PMOS transistor having a source connected to a supply voltage, a drain connected to a control signal and a gate connected to a first data input through an inverter;
a second PMOS transistor having a source connected to the control signal, a drain connected to a ground voltage and a gate connected to an output node;
a first NMOS transistor having a drain connected to the output node, a source connected to a virtual node, and a gate connected to a second data input; and
a second NMOS transistor having a drain connected to the source of said first NMOS transistor through said virtual node, a source connected to the ground voltage, and a gate connected to the control signal.
8) An impedance control circuit generating a control signal for varying an impedance of an output node comprising:
a first NMOS transistor having a drain connected to a supply voltage, a source connected to a control signal, and a gate connected to a first data signal;
a first PMOS transistor having a source connected to the control signal, a drain connected to a ground voltage, and a gate connected to an output node;
a second NMOS transistor having a drain connected to the control signal, a source connected to the ground voltage, and a gate connected to a second data signal; and
a third NMOS transistor having a drain connected to the output node, a source connected to the ground voltage, and a gate connected to the control signal.
9) An impedance control circuit generating a control signal for varying an impedance of an output node comprising:
a first NMOS transistor having a drain connected to a supply voltage, a source connected to a control signal, and a gate connected to a first data signal;
a first PMOS transistor having a source connected to the control signal, a drain connected to a ground voltage, and a gate connected to an output node;
a second NMOS transistor having a drain connected to the output node, a source connected to a virtual node, and a gate connected to a second data signal; and
a third NMOS transistor having a drain connected to the source of the second NMOS transistor through said virtual node, a source connected to the ground voltage, and a gate connected to the control signal.
10) An output buffer circuit substantially as herein described with reference to and as
illustrated in the accompanying drawings
11) An impedance control circuit generating a control signal for varying an
impedance of an output node substantially as herein described with reference to
and as illustrated in the accompanying drawings