CLASS D AMPLIFIER CIRCUIT
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a class D amplifier circuit
and, in particular, relates to a class D amplifier circuit which
can realize the reduction of distortion and power loss at the time
of inputting a small signal.
[0002]
The class D amplifier circuit converts an input signal into
a pulse width modulation signal having constant amplitude and
amplifies the power of the pulse width modulation signal. The
class D amplifier circuit is used for amplifying the power of an
audio signal. Since the class D amplifier circuit operates based
on binary values, the loss of a transistor can be reduced to a
large extend and so a high efficiency can be realized
advantageously.
[0003]
Such a kind of the class D amplifier circuit includes an
integration circuit for integrating an input signal, a comparison
circuit for comparing the output signal of the integration circuit
with a predetermined triangular signal, and a pulse width amplifier
for amplifying the output signal of the comparison circuit to
thereby output as pulse signal. The output signal of the pulse
width amplifier is fed back to the input side of the integration
circuit. The output signal of the pulse width amplifier passes
a low pass filter configured by a coil and a capacitor and so obtained

as an analog signal for driving a load such as a speaker. In recent
years, a filter-less class D amplifier circuit has been realized
in which a low-pass filter is eliminated.
[0004]
As described in JP-A-2006-42296, in order to avoid the power
loss at the time where the input signal has no signal component,
that is, at the time of no input-signal, the class D amplifier
circuit employs a differential input system and a delay circuit
to thereby set a duty ratio of an output pulse at the time of no
input-signal to several %. Fig. 4 is a block diagram showing such
a class D amplifier circuit 200. For the sake of convenience,
this figure shows only the main portion of the amplifier, and a
feedback circuit and an integration circuit etc. are omitted. The
class D amplifier circuit 200 compares an input signal Vi+ to a
positive input terminal and an input signal Vi+- to a negative
input terminal with a triangular wave output from a triangular
wave generation circuit 20 by using comparators 12a, 12b,
respectively to thereby pulse-width modulates the input signals.
[0005]
As shown in Fig. 5, at the time of no input-signal, each of
the output signal A of the comparator 12a and the output signal
B of the comparator 12b is a pulse signal having a duty ratio of
50%. When these pulse signals are subjected to the logical
operation by using a circuit configured by inverters 13a, 13b and
NAND circuits 14a, 14b, each of the output signal OutP of a positive
output terminal and the output signal OutM of a negative output

terminal output via an output stage circuit 40 does not contain
any output pulse. Thus, the power loss at the time of no
input-signal can be reduced. However, in general, since there
arises a dead zone near the input crossover due to the accuracy
etc. of the comparators 12, the pulse signal output disappears
or distortion appears at the time of inputting no signal or a small
signal. Thus, the class D amplifier circuit 200 employs a delay
circuit 30 having a delay amount W to thereby generate a signal
Bd. Therefore, as shown in Fig. 5, since a pulse signal having
a pulse width W is output as each of the output signals OutP, OutM
at the time of no input-signal, the modulation width can be
accurately reflected and the distortion can be reduced at the time
of the small input signal.
[0006]
As explained above, the distortion at the time of the small
input signal can be reduced by outputting the pulse having the
width W at the time of no input-signal. However, since a current
flows into a load such as a speaker when the pulse width "W of the~
output pulse is large, there arises the power loss and also heat
generated by such the power loss cannot be neglected. Accordingly,
the pulse width W of the output pulse is required to be as small
as possible,, preferably.
[0007]
Although the output pulses are output to the load (not shown)
via the output stage circuit 40, in general the output stage circuit
40 is configured by buffers which are connected in a multi-stage

manner. In this case, in order to transmit the output pulse
correctly, the output pulse of the certain buffer is required to
exceed the threshold voltage of the buffer of the next-stage.
However, if the waveform of the output pulse is dulled due
to the input capacity of the buffer, the pulse can not be transmitted
sufficiently to the buffer of the next stage, there may arise a
case that there appears no output pulse. When the output pulse
disappears, the distortion is generated at the time of the. small
input signal. On the other hand, if the delay amount W of the
delay circuit 30 is set to be large, at the time that the delay
amount of the output stage circuit 40 becomes small due to a condition
such as a power supply or the temperature, the pulse width W at
the time of no input-signal becomes large. Thus, there, arises
a problem that the power loss at the load such as the speaker becomes
large and an amount of the heat generated from the load increases.
[0008]
SUMMARY OF THE INVENTION
The invention is made in view of the aforesaid problem and
intended to realize the reduction of distortion and power loss
at the time of inputting a small signal in a class D amplifier
circuit.
[0009]
In order to solve the aforesaidproblem, the present invention
provides the following arrangements.
(1) A class D amplifier circuit, comprising:
a pulse width modulator which pulse-width-modulates input

signals to generate first and second signals, respectively;
a pulse generator which generates first and second output
pulse signals to be output outside, based on the first and second
signals; and
an adjustor which adjusts pulse widths of the first and second
outputpulse signals soas to have predetermined widths respectively
in a state where the input signal has no signal component, based
on the first and second output pulse signals or a signal of a
predetermined node of the pulse generator.
(2) The class D amplifier circuit according to (1), wherein
the pulse generator includes:
a delay unit which delays the second signal to generate a
delayed second signal and can control a delay time of the second
signal;
a pulse signal generator which inputs the first signal and
the delayed second signal to generate the first and second pulse
signals; and
a buffer unit which amplifies power of the first and second
pulse signals to generate the first and second output pulse signals,
respectively, and outputs the first and second output pulse signals
to the outside, and
the adjustor includes:
a pulse detector which detects presence or non-presence of
a pulse in the first and second output pulse signals, or in a signal
of a predetermined node of the buffer unit; and

a delay time controller which controls the delay time of the
delay unit according to a detection result of the presence or
non-presence of the pulse.
(3) The class D amplifier circuit according to (2), wherein
the delay time controller controls the delay time of the delay
unit so as to be longer when the pulse is not detected, and controls
the delay time of the delay unit so as to be shorter when the pulse
is detected.
(4) The class D amplifier circuit according to (2), wherein
the pulse detector detects the non-presence state of the pulse
with a first period and detects the presence state of the pulse
with a second period longer than the first period.
(5) The class D amplifier circuit according to (4), wherein the
first and second-periods are out of an audible frequency range.
(6) The class D amplifier circuit according to (1), wherein
the pulse generator includes inverter buffers coupled in a
multi-stage manner, and the predetermined node of the pulse
generator being a node between the adjacent inverter buffers.
[0010]
According to the invention, since the pulse widths of the
first output pulse signal and the second output pulse signal are
adjusted in accordance with the first output pulse signal and the

second output pulse signal or the signal of the predetermined node
of the pulse generator, the state where the output pulse does not
exist at all can be prevented from occurring and the pulse width
is set to be the necessary and sufficient minimum value. Thus,
the reduction of the distortion and the power loss can be realized
at the time of a small input signal.
[0012]
According to the invention, since the first output pulse signal
and the second output pulse signal or the signal of the predetermined
node of the buffer unit is monitored, the presence or non-presence
of the pulse in the first output pulse signal and the second output
pulse signal can be directly or indirectly detected. Further,
since the delay time is adjusted in accordance with the presence
or non-presence of the pulses, the reduction of the distortion
and the power loss can be realized at the time of a small input
signal.
[001-3]
According to the present invention, the delay time controller
controls the delay time of the delay unit so as to be longer when
the pulse is not detected, and controls the delay time of the delay
unit so as to be shorter when the pulse is detected. In this case,
since the delay time of the delay unit is set to be longer when
the pulse is not detected, the pulse can be made appear, and so
the distortion can be reduced at the time of a small input signal.
Further, since the delay time of the delay unit is set to be shorter
when the pulse is detected, the pulse width can be made smaller

and so the power loss can be reduced.
[0014]
According to the present invention, the pulse detector detects
the non-presence state of the pulse with a first period and detects
the presence state of the pulse with a second period which is longer
than the first period. In this case, since the non-presence state
of the pulse can be detected earlier than the detection of the
presence state of the pulse, it is possible to detect the
disappearance of the pulse as early as possible to thereby surely
reduce the distortion at the time of a small input signal.
Furthermore, each of the first period and the second period is
set to be out of the audible frequency range, so that the generation
of noise due to the switching of the pulse width can be prevented.
[0031]
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram showing the configuration of a class
D amplifier circuit 100 according to an embodiment.
Fig. 2 is a block diagram showing an example of the
configuration of a delay amount variable circuit and an up/down
counter.
Fig. 3 is a block diagram showing an example of the
configuration of the pulse monitor circuit
Fig. 4 i s a block diagram showing the configuration of a class
D amplifier circuit of a related art using a delay circuit.
Fig. 5 is a diagram showing output pulses at a time of no
input-signal and at a time of a small input signal.

[0015]
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
An embodiment according to the invention will be explained
with reference to the accompanying drawings. Fig. 1 is a block
diagram showing the configuration of a class D amplifier circuit
100 according to the embodiment. In the figure, elements identical
to those of Fig. 4 are referred to by the common symbols. As shown
in this figure, the class D amplifier circuit 100 includes a positive
input terminal,, a negative input terminal, a positive output
terminal and a negative output terminal. An input signal Vin+
is supplied to the positive input terminal and an input signal
Vin- is supplied to the negative input terminal. A pulse width
modulation signal Out P is output from the positive output terminal
and a pulse width modulation signal Out M is output from the negative
output terminal. That is, the input signals Vin are applied in
a form of a differential input. The pulse width modulation signals
Out P, OutM are coupled to a load such as a not-shown- speaker.
As a result, the load such as the speaker is operated by a difference
signal of OutP and OutM. In this embodiment, although the amplifier
circuit is configured as a filter-less type class D amplifier
circuit which is coupled to the load by not using a low pass filter,
the amplifier circuit may be configured as a normal type class
D amplifier circuit which is coupled to the load via a low pass
filter.
[0016]
The class D amplifier circuit 100 includes a PWM signal

generating portion XI which is configured by resistors Rl to R6,
capacitors Cl to C4, an operational amplifier 11, comparators 12a,
12b and a triangular wave generating circuit 20, a logic circuit
portion X2 which is configured by inverters 13a, 13b and NAND
circuits 14a, 14b, and an adjusting portion X3 which is configured
by an output stage circuit 40, a delay amount variable circuit
50, a pulse monitor circuit 60 and an up/down counter 70.
[0017]
In the PWM signal generating portion XI, the positive input
terminal of the operational amplifier 11 is supplied with the input
signal Vin+ via the resistor Rl and also a feedback signal via
the resistor R3 . The negative input terminal of the operational
amplifier 11 is supplied with the input signal Vin- via the resistor
R2 and also a feedback signal via the resistor R4 . T-type secondary
differentiating circuits are provided between the positive output
terminal and the negative input terminal of the operational
amplifier 11 and the negative output terminal and the positive
input terminal of the operational amplifier, respectively. The
differentiating circuit between the negative output terminal and
the positive input terminal of the operational amplifier 11 is
configured by the capacitors Cl, C3 and the resistor R5 which is
provided between the connection point between these capacitors
and the ground. The differentiating circuit between the positive
output terminal and the negative input terminal of the operational
amplifier 11 is configuredby the capacitors C2, C4 and the resistor
R6 which is provided between the connection point between these
10

capacitors and the ground. Since each of the differentiating
circuits is provided in a feedback loop of the operational amplifier
11, the operational amplifier including the amplifier and the
differentiating circuit acts as an integration circuit which
composes the input signal Vin and the feedback signal, then subjects
the composed signal to the secondary differentiation and outputs
an integration signal.
[0018]
The triangular wave generating circuit 20 generates a
triangular wave signal having constant amplitude. The frequency
of the triangular wave signal is set be higher than that of the
input signal Vin. In this embodiment, the maximum frequency of
the input signal Vin is 20 KHz and the frequency of the triangular
wave signal is 200 KHz. The spectrum of the triangular wave signal
may be spread in a view point of reducing unnecessary
electromagnetic radiation. The PWM signal generating portion
generates a pulse-width modulated signal A and a pulse-width
modulated signal B based on the triangular wave signal and the
integration signal. Each of the comparators 12a, 12b outputs a
high level when the level of the integration signal exceeds the
level of the triangular wave signal, while outputs a low level
when the level of the integration signal becomes lower than the
level of the triangular wave signal.
[0019]
The delay amount variable circuit 50 delays the output signal
B to generate an output Bd. The delay amount variable circuit
11

50 can change the delay amount in accordance with a control signal
CTL from the up/down counter 70. Fig. 2 is a block diagram showing
an example of the configuration of the delay amount variable circuit
50 and the up/down counter 70. The up/down counter 70 is a counter
which counts a not-shown clock signal in a manner of increasing
a count value when an up signal is made active, while reducing
the count value when a down signal is made active. The up/down
counter 70 outputs the control signal CTL of n bits (n is a natural
number equal to or more than 2) representing the count value, to
the delay amount variable circuit 50.
[0020]
The delay amount variable circuit 50 includes an inverter
InvlO configured by transistors TrPl to TrP4 and transistors TrNl
to TrN3, a capacitor Cll, an inverter Invll, a constant current
circuit 51 and a selection circuit 52. The inverter InvlO charges
and discharges the capacitor Cll and the magnitude of a driving
signal for the capacitor is determined in accordance with a current
flowing through the transistor TrPl. When the driving current-
becomes large, since the charge/discharge time period of the
capacitor Cll becomes short, the delay time of the delay amount
variable circuit 50 becomes short. In contrast, when the driving
current becomes small, since the charge/discharge time period of
the capacitor Cll becomes long, the delay time of the delay amount
variable circuit 50 becomes long.
[0021]
The constant current circuit 51 and the selection circuit
12

52 have a function of adjusting an amount of the current flowing
into the transistor TrPl. The constant current circuit 51 includes
n constant current sources 51-1, 51-2, ... 51-n, and the selection
circuit 52 includes n switches SW1, SW2, ... SWn, The on/off states
of the n switches SW1 to SWn are controlled by the respective bits
of the n-bit control signal CTL, respectively. In this embodiment,
the current amounts of the constant current sources 51-1 to 51-n
are set to be larger as the suffixes thereof becomes larger. The
control signal CTL controls the switches SW1 to SWn in a manner
that the constant current source outputting a smaller current value
is selected from the constant current sources 51-1 to 51-n as the
count value of the up/down counter 70 is larger and that the constant
current source outputting a larger current value is selected from
the constant current sources 51-1 to 51-n as the count value of
the up/down counter 7.0 is smaller.
The configuration of the delay amount variable circuit 50
shows merely an example, and the invention may employ the delay
amount ^variable circuit having various kinds of configuration' so
long as the delay amount can be changed in accordance with the
count value of the up/down counter 70.
[0022]
The explanation will be returned to Fig. 1. The logic circuit
portion X2 inputs the output signal A and the output signal Bd
which is obtained by delaying the output signal B by the delay
amount variable circuit 50, and outputs an NAND signal which is
obtained by subjecting the inverted signal of the output signal
13

A and the output signal Bd to the NAND logical operation and also
outputs an NAND signal which is obtained by subjecting the output
signal A and the inverted signal of the output signal Bd to the
NAND logical operation. The external load, such as the speaker
is driven by the difference between these NAND signals . The output
stage circuit 40 is configured by coupling the inverter buffers
in a multi-stage manner.
[0023]
The pulse monitor circuit 60 detects the presence or
non-presence of the output pulse output from the output stage
circuit 40 and outputs the up signal or the down signal to the
up/down counter 70 in accordance with the detection result. To
be concrete, the pulse monitor circuit outputs the down signal
when the output pulses are detected, while outputs the up signal
when the output pulses are not detected. Thatis, in this embodiment,
the delay amount is made small to narrow the output pulse width
when the output pulses are- detected, while the delay amount is
made large to appear the output pulse width when the output pulses
are not detected.
Alternatively, the pulse monitor circuit 60 may monitor the
signal of a node between the adjacent buffers of the output stage
circuit 40 to detect the present or non-presence of the output
pulse.
[0024]
Fig.3 is a block diagram showing an example of the
configuration of the pulse monitor circuit 60. The pulse monitor
14

circuit 60 is configured by an up signal generating portion 60a
for generating the up signal and a down signal generating portion
60b for generating the down signal. In this embodiment, pulses
pP, pM input into the inverters of the final stage of the multi-stage
buffers of the output stage circuit 40 are output to an AND circuit
61 of the up signal generating portion 60a.
[0025]
Thus, the AND circuit 61 outputs a reset signal of a low level
when at least one of the pulses pP, pM, which are respectively
inverted signals of the output pulses OutP, OutM, becomes a low
level. The reset signal is supplied to the reset terminals of
D flip-flops FF1, FF2. Each of the D flip-flops FF1, FF2 sets
the logical level of the output signal thereof to a low level forcedly
when the voltage of the reset terminal thereof becomes the low
level. Thus, when each of the output pulses OutP, OutM is the
low level and so there exists no pulse during two periods of a
clock signal Ckl, the up signal becomes the high-level.
[0026]
An inverter 62 inverts the up signal and supplies the inverted
up signal to the reset terminals of the D flip-flops FF3, FF4.
Each of the D flip-flops FF3, FF4 sets the logical level of the
output signal thereof to a low level forcedly when the voltage
of the reset terminal thereof becomes the low level. Thus, when
the output pulses OutP, OutM alternatively exhibit a high-level
pulse, that is, when the up signal does not becomes the high level
at all during two periods of a clock signal Ck2, the down signal
15

becomes the high level.
[0027]
In this case, the frequency of the clock signal Ckl is set
to be sufficiently larger than that of the clock signal Ck2 . For
example, the frequency of the clock signal Ckl is set to be 100
KHz and the frequency of the clock signal Ck2 is set to be 1 Hz.
The frequency of each of these clock signals is out of the audible
frequency range (20 Hz to 20 KHz) . The reason why the frequency
of the clock signal Ckl is set to be 20 KHz or more and the frequency
of the clock signal Ck2 is set to be 20 Hz or less is as follows.
That is, when the up signal or the down signal becomes the high
level, the pulse widths of the output pulses OutP, OutM are changed
or the output pulses OutP, OutM are generated. As a result, when
the switching of the up signal or the down signal is within the
audible frequency range, the noise arises. Thus, the frequency
of each of the clock signal Ckl and the clock signal Ck2 is set
out of the audible frequency range.
[0028]
Further, since the frequency of the clock signal Ckl is set
to be quite larger than that of the clock signal Ck2, the up signal
is output immediately when the output pulses OutP, OutM disappear,
while the down signal is slowly output relatively when the output
pulses OutP, OutM appear. Thus, the time period where the output
pulses OutP, OutM disappear can be made as small as possible, so
that the distortion can be suppressed from being generated at the
time of the small input signal. Further, when the output pulses
16

are detected, since the delay amount is controlled to be made small,
that is, the output pulse width is controlled to be made short,
the output pulse width can be kept to almost the minimum value.
Thus, the reduction of the distortion and the lower loss at the
time of the small input signal can be realized.
[0029]
According to the aforesaid configuration, the following
operation is performed by the embodiment. That is, the pulse
monitor circuit 60 detects the presence or non-presence of the
output pulses OutP, OutM output from the output stage circuit 40.
The pulse monitor circuit 60 outputs the up signal to the up/down
counter 70 when none of the output pulses OutP, OutM exist and
outputs the down signal to the up/down counter 7 0 when the output
pulses OutP, OutM exist. The up/down counter 70 counts the value
in accordance with the up signal and the down signal, and outputs
the signal for increasing the delay amount of the delay amount
variable circuit 50 when the count value is large, that is, when
the output pulses OutP, OutM disappear. "In this case, the delay
amount is set to be larger as the time period where none of the
output pulses OutP, OutM exist becomes longer. In contrast, when
the count value is small, that is, when the output pulses OutP,
OutM exist, the counter outputs the signal for reducing the delay
amount of the delay amount variable circuit 50. In this case,
the delay amount is set to be smaller as the time period where
the output pulses OutP, OutM exist becomes longer.
[0030]
17

When the delay amount of the delay amount variable circuit
50 becomes larger, since the output pulse width is made larger,
the output pulses OutP, OutM appear. In contrast, when the delay
amount of the delay amount variable circuit 50 becomes smaller,
the output pulse width is made smaller. In this embodiment, since
such the control is performed continuously, the state where the
output pulse does not exist at all can be prevented from occurring
also at the time of the no input-signal. Thus, the distortion
at the time of the small input signal can be reduced. Further,
since the pulse width is set to be the necessary and sufficient
minimum value, the reduction of the power loss can be realized.
18

WE CLAIM
1. A class D amplifier circuit, comprising:
a pulse width modulator which pulse-width-modulates input
signals to generate first and second signals, respectively;
a pulse generator which generates first and second output
pulse signals to be output outside, based on the first and second
signals; and
an adjustor which adjusts pulse widths of the first and second
output pulse signals so as to have predetermined widths respectively
in a state where the input signal has no signal component, based
on the first, and second output pulse signals or a signal of a
predetermined node of the pulse generator.
2. The class D amplifier circuit according to claim 1, wherein
the pulse generator includes:
a delay unit which delays the second signal to generate a
delayed second signal and can control a delay time of the second
signal;
a pulse signal generator which inputs the first signal and
the delayed second signal to generate the first and second pulse
signals; and
a buffer unit which amplifies power of the first and second
pulse signals to generate the first and second output pulse signals,
respectively, and outputs the first and second output pulse signals
to the outside, and
the adjustor includes:
19

a pulse detector which detects presence or non-presence of
a pulse in the first and second output pulse signals, or in a signal
of a predetermined node of the buffer unit; and
a delay time controller which controls the delay time of the
delay unit according to a detection result of the presence or
non-presence of the pulse.
3. The class D amplifier circuit according to claim 2, wherein
the delay time controller controls the delay time of the delay
unit so as tc be longer when the pulse is not detected, and controls
the delay time of the delay unit so as to be shorter when the pulse
is detected.
4. The class D amplifier circuit according to claim 2, wherein
the pulse detector detects the non-presence state of the pulse
with a first period and detects the presence state of the pulse
with a second period' longer than the first period.
5. The class D amplifier circuit according to claim 4, wherein
the first and second periods are out of an audible frequency range .
6. The class D amplifier circuit according to claim 1, wherein
the pulse generator includes inverter buffers coupled in a
multi-stage manner, and the predetermined node of the pulse
generator being a node between the adjacent inverter buffers.

A pulse monitor circuit detects the presence or non-presence
of the output pulses output from an output stage circuit. The
pulse monitor circuit outputs an up signal to the up/down counter
when the output pulses do not exist at all and outputs a down signal
to the up/down counter when the output pulses exist. The up/down
counter outputs a signal for increasing the delay amount of a delay
amount variable circuit when a count value is large, that is, when
the output pulses disappear. In contrast, when the count value
is small, that is, when the output pulses exist, the counter outputs
the signal for reducing the delay amount of the delay amount variable
circuit.