Claims:We Claim:

1. A method for clock generation and locking the same from high data rate frequency hopping frame of tactical radio, comprising:
receiving RF input signals including data samples;
demodulating the received input signals for recovering data signals in responsive to the incoming data samples representatives of the phasing signal portion of the digital data signal;
segregating the incoming data samples into one or more sample sequences having different information bit from the demodulated signal;
correlating the segregated one or more sample sequence against a hop frequency modulation code reference sequence to provide an output signal indicative of correlated data samples and of the data signal detection;
generating an asynchronous pulse in detection of the unique word of the output signal;
resetting the counter at a predetermined value and determine the modulo of the value to get the values of 0 and N-1,
generating binary bits in accordance to the duty cycle of the recovered symbol clock;
clearing the jitter in the symbol clock and to produce a clock corresponding to the payload data rate, wherein the payload data rate is an integer multiple of the symbol clock rate; and
collecting the actual information bits from the hopping from using the recovered clock by PLL and storing the same for further processing.

2. The method as claimed in claim 1, wherein the step of generating the asynchronous pulse using an edge detection circuit to generate a glitch which is used as a reset to the counting.

3. The method as claimed in claim 1, wherein the counting width is such that it is able to count X+C, where C is a constant.

4. The method as claimed in claim 1, wherein the step of correlating uses a pattern detection circuit to get the flag for start of payload frame.

5. The method as claimed in claim 1, wherein the step of resetting includes resetting asynchronously by the output of asynchronous pulse generator using counter and also offsetting between transmit and receive clock.

6. The method as claimed in claim 5, wherein a tolerance of C is added to maximum value of the counter X, wherein the counter modulo value consists of divided by N circuit and outputs the remainder value for each division, the modulo value range is 0 to N-1.

7. The method as claimed in claim 1, wherein the step of generating to store 1’s and 0’s according to the duty cycle requirement of the recovered symbol clock using a Look Up Table (LUT).

8. The method as claimed in claim 1, wherein the step of clearing includes clearing of the jitter in the recovered symbol clock and generate the bit clock frequencies which are integer multiple of symbol clock.

9. A system for clock generation and locking the same from high data rate frequency hopping frame of tactical radio, comprising:
a RF receiver for receiving RF input signals including data samples;
a demodulator coupled with the RF receiver for recovering data signals in responsive to the incoming data samples representatives of the phasing signal portion of the digital data signal;
a deframer coupled with the demodulator to segregate the incoming data samples into one or more sample sequences having different information bit from the demodulated signal;
a unique word detector coupled with the deframer for correlating the deframed one or more sample sequence against a hop frequency modulation code reference sequence to provide an output signal indicative of correlated data samples and of the data signal detection;
an asynchronous pulse generator coupled with the correlator/unique word detector for generating an asynchronous pulse in detection of the unique word of the output signal;
a counter and modulo value generator coupled to the asynchronous pulse generator to reset the counter at a predetermined value and determine the modulo of the value to get the values of 0 and N-1;
a binary mapper coupled to the a counter and modulo value generator for generating binary bits in accordance to the duty cycle of the recovered symbol clock;
a PLL unit coupled with the binary mapper for clearing the jitter in the symbol clock and to produce a clock corresponding to the payload data rate, wherein the payload data rate is an integer multiple of the symbol clock rate; and
a data buffer coupled with the PLL unit for collecting the actual information bits from the hopping from using the recovered clock by PLL and storing the same for further processing.

10. The system as claimed in claim 9, wherein the frequency hopping frame includes overhead symbols, synchronization symbols, unique word, payload and end of frame (EOF).

11. The system as claimed in claim 9, wherein the use transmission frame has sufficient number of unique words which are embedded in hopping frame. , Description:

Field of the Invention
The invention relates to digital communication systems, and more particularly, to a digital radio system apparatus and method for clock recovery and clock locking scheme or technique from high data rate frequency hopping frame of tactical radio. The present scheme applied for very high data rate where higher order modulation scheme is used for data transmission in which clock jitter is prominent.

Background
The field has greatly grown over the past decades and the use of digital radio is widespread. Spread spectrum systems and, in particular, frequency hopping transmission systems, have produced results in communications, navigation and test systems that were not possible with standard signal formats. Frequency hopping signal transmission systems are a type of spread spectrum system in which the wideband signal is generated by hopping from one frequency to another over a large number of frequency choices. In order to increase the efficiency of digital radios employing spread spectrum characteristics, digital engineers have raised the number of modulation levels and have generally dealt with modulation/demodulation techniques, spectral shaping and synchronization schemes. This has led to widespread and more efficient use of the digital radio systems. Some of the patent describes various method and system on the above subject matter.

For example, US Patent 5019825 describes a method of coherently interruptible frequency hopped chirp generator where a signal generating synthesizer and a chirp generator with digitally stored chirp samples in which both are phase locked to a reference clock and responsive to a timing and control circuit. The digitally stored chirp signal samples are D/A converted and mixed with a fixed frequency signal generated by the synthesizer forming translated chirp signal. The translated chirp signal are output being controlled by a timing and controlled circuit so that a plurality of coherently interruptible and frequency selectable chirp sub-pulses are formed.

In another example, US Patent 8456242 describes a novel scheme frequency locked loop. A locked loop circuit includes an oscillator and extrapolator. The oscillator generates an output signal in respond to a controlled value. The extrapolator determines, based on a first state of the oscillator and a transfer function of the oscillator the controlled value of the oscillator to transition the oscillator to a second operating state.

In yet another example, US Patent 4654859 describes to a frequency synthesizer for frequency hopping communication system. A wireless data communication network utilizes a frequency synthesizer to achieve a systematic frequency hopping arrangement wherein frequency is incremented by two times the channel spacing from lowest frequency to highest frequency. When adjusting the frequency from highest to lowest a one time the channel spacing frequency hop is utilized for the first and half and last half and two times the frequency spacing is utilized otherwise. In this manner alternating frequencies are selected so that the same frequency is only utilized once during any complete cycle and the size of frequency transition is held to a minimum allowing a narrow bandwidth filter and inexpensive implementation of the phase locked loop portion of the synthesizer.

In yet another example, US Patent US 7426220 describes a method and apparatus for aligning the clock signal of transceiver in a multiple access communication system utilizing programmable multi-tap phase locked loops.

In view of the above arts, there is a need in the art for a method or system or apparatus for clock recovery and clock locking scheme or technique from high data rate frequency hopping frame of tactical radio with specific functionality/application.

Object of the Invention
The objective of the present invention is to implement a novel scheme for clock recovery and clock locking circuit from burst frame of frequency hopping tactical radio. Once the unique word is detected, a pulse of one clock cycle is generated. The asynchronous pulse generator uses an edge detection circuit to generate a glitch which is used as a reset to the counter. The counter width is such that it is able to count X+C. The counter output is provided to the Modulo N generator circuit where outputs the value between 0 and N-1. The modulo N value is input to the binary mapper where it outputs a binary 0 or 1. The generated clock in this method is equal to the payload symbol rate in a bursty frame and it is jittery. A PLL is employed to clean the jitter in the clock and produce a clock corresponding to the payload data rate, which is an integer multiple of the symbol clock rate.

Summary of the Invention
An aspect of the present invention is to address at least the above-mentioned problems and/or disadvantages and to provide at least the advantages described below.

Accordingly, in one aspect of the present invention provides a method for clock generation and locking the same from high data rate frequency hopping frame of tactical radio. In one embodiment, the method includes receiving RF input signals including data samples, demodulating the received input signals for recovering data signals in responsive to the incoming data samples representatives of the phasing signal portion of the digital data signal, segregating the incoming data samples into one or more sample sequences having different information bit from the demodulated signal, correlating the segregated one or more sample sequence against a hop frequency modulation code reference sequence to provide an output signal indicative of correlated data samples and of the data signal detection, generating an asynchronous pulse in detection of the unique word of the output signal, resetting the counter at a predetermined value and determine the modulo of the value to get the values of 0 and N-1, and further generating binary bits in accordance to the duty cycle of the recovered symbol clock, clearing the jitter in the symbol clock and to produce a clock corresponding to the payload data rate, wherein the payload data rate is an integer multiple of the symbol clock rate, and collecting the actual information bits from the hopping from using the recovered clock by PLL and storing the same for further processing.

In another aspect of the present invention provides a system for clock generation and locking the same from high data rate frequency hopping frame of tactical radio. In an embodiment, the system includes a RF receiver for receiving RF input signals including data samples, a demodulator coupled with the RF receiver for recovering data signals in responsive to the incoming data samples representatives of the phasing signal portion of the digital data signal, a deframer coupled with the demodulator to segregate the incoming data samples into one or more sample sequences having different information bit from the demodulated signal, a unique word detector coupled with the deframer for correlating the deframed one or more sample sequence against a hop frequency modulation code reference sequence to provide an output signal indicative of correlated data samples and of the data signal detection, an asynchronous pulse generator coupled with the correlator/unique word detector for generating an asynchronous pulse in detection of the unique word of the output signal, a counter and modulo value generator coupled to the asynchronous pulse generator to reset the counter at a predetermined value and determine the modulo of the value to get the values of 0 and N-1, a binary mapper coupled to the a counter and modulo value generator for generating binary bits in accordance to the duty cycle of the recovered symbol clock, a PLL unit coupled with the binary mapper for clearing the jitter in the symbol clock and to produce a clock corresponding to the payload data rate, wherein the payload data rate is an integer multiple of the symbol clock rate and a data buffer coupled with the PLL unit for collecting the actual information bits from the hopping from using the recovered clock by PLL and storing the same for further processing.

Other aspects, advantages, and salient features of the invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses exemplary embodiments of the invention.

Brief description of the drawings
The above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which:

Figure 1 illustrates a system block diagram of clock recovery & locking scheme, according to one embodiment of the present invention.

Figure 2 illustrates a frequency hopping frame format.

Figure 3 illustrates a flow chart of a method for clock generation and locking scheme from high data rate frequency hopping frame of tactical radio, according to one embodiment of the present invention.

Persons skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and may have not been drawn to scale. For example, the dimensions of some of the elements in the figure may be exaggerated relative to other elements to help to improve understanding of various exemplary embodiments of the present disclosure.

Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures.

Detail description of the invention
The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the invention. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.

The terms and words used in the following description and claims are not limited to the bibliographical meanings, but, are merely used by the inventor to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention are provided for illustration purpose only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.

It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise.

Figure 1 illustrates the system block diagram of clock recovery & locking scheme. The system includes RF receiver & ADC unit, a demodulator unit, deframer unit, a unique word detector unit, asynchronous pulse generator unit, a counter unit, a modulo value generator unit, a binary mapper unit, a PLL unit and a data buffer unit. The RF receiver & ADC unit 1 is used to receive transmitted RF signal. The Demodulator unit 2 is used for demodulating the modulated data. The FH frame’s deframer unit 3 segregates the different information bit from demodulated symbol. The Unique word (UW) detector unit 4 correlates the known pattern which is embedded in a burst hopping frame. The Asynchronous pulse generator unit 5 uses edge detection circuit to generate an asynchronous pulse from detected UW which is used for resetting the counter. The Counter unit 6, the counter width is such that it is able to count X+C, C is a constant. The Modulo value generator 7 and the Binary mapper 8, modulo N value is input to the binary mapper which outputs a binary 0 or 1 according to the duty cycle of the recovered symbol clock which is used as a reset pulse for PLL. Phase locked loop (PLL) block 9 produces a jitter free clock for the system. Data buffer block 10 stores the data bits for further processing.

The following algorithm is used for above mentioned method
1. Clock recovery
N = (Sampling rate) / (payload symbol rate)
Oversampling = (Sampling rate)/(symbol rate over the air)
X = (number of modulated symbols in a frame)* Oversampling

Figure 2 illustrates the block diagram of frame format for frequency hopping. Overhead symbol block 11 is the overhead symbols to compensate the RF ON/OFF time, PLL/PA/LNA/AGC settling time. Synchronization symbol block 12 is used to compensate the timing and carrier synchronization timing of the demodulator block. Unique word block 13 is the known pattern for clock recovery and locking from a jittery receiver. Payload block 14 is the actual information bits. End of frame (EOF) 15 is a known pattern to indicate the receiver to shift to another frequency for hopping.

Figure 3 illustrates a flow chart of a method for clock generation and locking scheme from high data rate frequency hopping frame of tactical radio, according to one embodiment of the present invention. As soon as received the hop frame at step 16, the de-framer at step 17 start collecting data using its own recovered clock. If unique word (UW) at step 18 is detected, it generates an asynchronous pulse at step 19 and it is used for resetting the counter at step 20 which is counting up to X+C. The counter output is provided to the Modulo N generator at step 21 circuit where outputs the value between 0 and N-1. The modulo N value is input to the binary mapper at step 22 where outputs is a binary 0 or 1 according to the duty cycle of the recovered symbol clock. A PLL at step 23 is employed to clean the jitter in the CLK and produce a clock corresponding to the payload data rate, which is an integer multiple of the symbol clock rate. Actual information bits are collected from hopping frame using recovered clock by PLL and stored for further processing.

While several embodiments have been provided in the present disclosure, it should be understood that the disclosed systems and methods might be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the intention is not to be limited to the details given herein. For example, the various elements or components may be combined or integrated in another system or certain features may be omitted, or not implemented.

In addition, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as coupled or directly coupled or communicating with each other may be indirectly coupled or communicating through some interface, device, or intermediate component whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and could be made without departing from the spirit and scope disclosed herein.

We Claim:

1. A method for clock generation and locking the same from high data rate frequency hopping frame of tactical radio, comprising:
receiving RF input signals including data samples;
demodulating the received input signals for recovering data signals in responsive to the incoming data samples representatives of the phasing signal portion of the digital data signal;
segregating the incoming data samples into one or more sample sequences having different information bit from the demodulated signal;
correlating the segregated one or more sample sequence against a hop frequency modulation code reference sequence to provide an output signal indicative of correlated data samples and of the data signal detection;
generating an asynchronous pulse in detection of the unique word of the output signal;
resetting the counter at a predetermined value and determine the modulo of the value to get the values of 0 and N-1,
generating binary bits in accordance to the duty cycle of the recovered symbol clock;
clearing the jitter in the symbol clock and to produce a clock corresponding to the payload data rate, wherein the payload data rate is an integer multiple of the symbol clock rate; and
collecting the actual information bits from the hopping from using the recovered clock by PLL and storing the same for further processing.

2. The method as claimed in claim 1, wherein the step of generating the asynchronous pulse using an edge detection circuit to generate a glitch which is used as a reset to the counting.

3. The method as claimed in claim 1, wherein the counting width is such that it is able to count X+C, where C is a constant.

4. The method as claimed in claim 1, wherein the step of correlating uses a pattern detection circuit to get the flag for start of payload frame.

5. The method as claimed in claim 1, wherein the step of resetting includes resetting asynchronously by the output of asynchronous pulse generator using counter and also offsetting between transmit and receive clock.

6. The method as claimed in claim 5, wherein a tolerance of C is added to maximum value of the counter X, wherein the counter modulo value consists of divided by N circuit and outputs the remainder value for each division, the modulo value range is 0 to N-1.

7. The method as claimed in claim 1, wherein the step of generating to store 1’s and 0’s according to the duty cycle requirement of the recovered symbol clock using a Look Up Table (LUT).

8. The method as claimed in claim 1, wherein the step of clearing includes clearing of the jitter in the recovered symbol clock and generate the bit clock frequencies which are integer multiple of symbol clock.

9. A system for clock generation and locking the same from high data rate frequency hopping frame of tactical radio, comprising:
a RF receiver for receiving RF input signals including data samples;
a demodulator coupled with the RF receiver for recovering data signals in responsive to the incoming data samples representatives of the phasing signal portion of the digital data signal;
a deframer coupled with the demodulator to segregate the incoming data samples into one or more sample sequences having different information bit from the demodulated signal;
a unique word detector coupled with the deframer for correlating the deframed one or more sample sequence against a hop frequency modulation code reference sequence to provide an output signal indicative of correlated data samples and of the data signal detection;
an asynchronous pulse generator coupled with the correlator/unique word detector for generating an asynchronous pulse in detection of the unique word of the output signal;
a counter and modulo value generator coupled to the asynchronous pulse generator to reset the counter at a predetermined value and determine the modulo of the value to get the values of 0 and N-1;
a binary mapper coupled to the a counter and modulo value generator for generating binary bits in accordance to the duty cycle of the recovered symbol clock;
a PLL unit coupled with the binary mapper for clearing the jitter in the symbol clock and to produce a clock corresponding to the payload data rate, wherein the payload data rate is an integer multiple of the symbol clock rate; and
a data buffer coupled with the PLL unit for collecting the actual information bits from the hopping from using the recovered clock by PLL and storing the same for further processing.

10. The system as claimed in claim 9, wherein the frequency hopping frame includes overhead symbols, synchronization symbols, unique word, payload and end of frame (EOF).

11. The system as claimed in claim 9, wherein the use transmission frame has sufficient number of unique words which are embedded in hopping frame.