DESC:TECHNICAL FIELD
The present disclosure relates to a CMOS chip gas sensor. In particular, embodiments include a gas sensor array comprising the CMOS chip gas sensor with an in-plane nano heater.

BACKGROUND OF THE DISCLOSURE AND PRIOR ARTS
Presently, gas sensing is used in a variety of fields including pollution monitoring, hazardous gas detection, and industrial process control. Typically, metal oxides such as tin dioxide (SnO2), zinc oxide (ZnO) are used as sensing elements along with metal catalysts such as platinum (Pt) or palladium (Pd). One of the problems in metal oxide sensor is that the film responds to a variety of reducing and/or oxidizing gases. Hence the sensing a specific gas selectively becomes difficult.

Conventionally, a sensor array was designed with each element of the array functionalized with different sensing film. But, designing a sensor array with each element of array functionalized with different sensing film requires multiple lithography steps which are very expensive. Also, the metal oxides typically require an out of plane heater, sitting underneath the sensing element, to activate the sensing element which necessitates additional lithography step. The sensor array fabrication requires multiple lithographic steps to deposit materials selectively to each array element which involves high cost, high power and large response time.

Conventionally, the gas sensitive structure are fabricated using the wide band gap semiconducting oxides such as zinc oxide (ZnO), titanium dioxide (TiO2), tin dioxide (SnO2), because of their versatile material properties and robust nature. The metal oxide based commercial gas sensors are commonly used for sensing inflammable hydrocarbon gases such methane CH4, hydrogen H2 and other toxic gases such as carbon monoxide (CO), nitrogen oxide (NOX), and sulphur oxide (SOX). However, the metal oxide based gas sensors suffer from three limitations. First limitation is relatively high operating temperature (=300° c), second limitation is large power dissipation (0.5-1Watt) and third limitation is cross sensitivity of gases to each other.

Further, for sensing gases, the temperature of the sensing oxide layer should be raised to a particular value which requires large amount of power. Therefore, nano crystalline materials are used to reduce the operating temperature. Nano crystalline materials with controlled composition are of increasing interest in gas sensing because of large surface to volume ratio which enhances the reaction probability with the target gases. So, an efficient gas sensor system should contain a gas sensor array with micro/nano heater along with nano crystalline materials. In the gas sensor array, each element of the sensor is functionalized by some metal oxide using multiple lithography processes which increases the cost of the sensors. Furthermore, some conventional integrated sensor array use hard shadow mask which are not scalable.

Hence, there is a need for a gas sensor array which can overcome the aforementioned limitation in the prior-art.

SUMMARY OF THE DISCLOSURE
The shortcomings of the prior art are overcome and additional advantages are provided through the present disclosure. Additional features and advantages are realized through the techniques of the present disclosure. Other embodiments and aspects of the disclosure are described in detail herein and are considered a part of the claimed disclosure.

In one embodiment, the present disclosure provides for a CMOS chip gas sensor. The, CMOS chip gas sensor comprising a base substrate layer, an intermediate substrate layer formed over the base substrate layer, at least two patterned metal layers formed on the intermediate substrate layer. A first metal layer of the at least two metal layers is configured as a heater and a second metal layer of the at least two metal layers is configured as an electrode comprising a gap for depositing predetermined gas sensing metal oxide material in the gap, at predetermined angle of incidence with respect to the base substrate layer. Further, a notch region is formed in the intermediate substrate layer to create suspended structures of a portion of the first and second metal layers at the notch region; and contact pads are provided on the at least two metal layers for electric probing.

In one embodiment, the heater is configured for inducing heat to the metal oxide material.

In one embodiment, a gap is formed in the suspended structure of the second metal layer at the notch region.

In one embodiment, a predetermined metal oxide material is deposited in the gap, at predetermined angle of incidence with respect to the base substrate layer.

In one embodiment, electrical property of the metal oxide material changes on exposure to gas.

In one embodiment, the metal layers have varying cross sectional areas.

In one embodiment, material composition of the base substrate layer is Silicon (Si).

In one embodiment, material composition of the intermediate substrate layer is Silicon Dioxide (SiO2).

In one embodiment, material composition of the metal layers is platinum (Pt).

In one embodiment, the metal oxide material deposited in the gap is selected from a group comprising WO3, V2O5, ZnO and SnO2, using process technique selected from a group comprising radio frequency (RF) sputtering, e-beam evaporation, and thermal evaporation

In one embodiment, the at least two contact pads is formed over the intermediate substrate layer by a method selected from a group comprising radio frequency (RF) sputtering DC sputtering, e-beam evaporation, and thermal evaporation.

In one embodiment, the present disclosure provides for a sensor array comprising a CMOS chip gas sensor comprising a base substrate layer, an intermediate substrate layer formed over the base substrate layer, a plurality of at least two metal layers formed on the intermediate substrate layer. Each of the plurality of the two metal layers comprising a first metal layer of the at least two metal layers is configured as a heater and a second metal layer of each of the plurality of at least two metal layers is configured as an electrode comprising a gap for depositing predetermined metal oxide material in the gap, at predetermined angle of incidence with respect to the base substrate layer. Further, a notch region is formed in the intermediate substrate layer to create suspended structures of a portion of the first and second metal layers at the notch region. At least two contact pads of predetermined thickness and predetermined length are provided on the at least two metal layers for electric probing.

In one embodiment, orientation of each of the plurality of the two metal layers is different to act as shadow mask for depositing the predetermined metal oxide material, at a predetermined angle of incidence for each of the element of the array.

In one embodiment, the predetermined metal oxide material in at least one of each of the plurality of the two metal layers is different.

In one embodiment, at least one of the plurality of the two metal layers is deposited with a different predetermined metal oxide material, with different angle of incidence with respect to the base substrate layer.

In one embodiment, the present disclosure provides for a method of manufacturing CMOS chip gas sensor array. The method comprising acts of forming a base substrate layer; forming an intermediate substrate layer formed over the base substrate layer, forming plurality of at least two metal layers formed on the intermediate substrate layer, wherein first metal layer of the at least two metal layers is configured as a heater and second metal layer of the at least two metal layers is configured as an electrode comprising a gap; providing a notch region in the intermediate substrate layer to create suspended structures of a portion of the first and second metal layer at the notch region.

In one embodiment, the intermediate substrate layer is thermally formed over the base substrate layer.

In one embodiment, the at least two metal layers are formed using lithography process selected from a group comprising photo-lithography process, laser lithography process, e-beam lithography process.

The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
The novel features and characteristics of the disclosure are explained herein. The embodiments of the disclosure itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings. One or more embodiments are now described, by way of example only, with reference to the accompanying drawing in which:

Figure 1: shows top and side views of CMOS chip gas sensor according to an embodiment of the present disclosure.
Figure 2: shows a magnified portion ‘A’ indicated in Figure 1 according to an embodiment of the present disclosure.
Figure 3a: shows Scanning Electron Microscope (SEM) image of the CMOS gas sensor chip according to an embodiment of the present disclosure.
Figure 3b: shows a magnified portion “B” indicated in Figure 3a to illustrate a nano gap created between the electrodes according to an embodiment of the present disclosure.
Figure 4: shows manufacturing steps of CMOS gas chip sensor array according to an embodiment of the present disclosure.
Figure 5a: shows top view of the CMOS gas chip sensor array comprising plurality of CMOS gas chip sensors oriented in different direction from one another according to the present disclosure.
Figure 5b: shows top view of the CMOS gas chip sensor array comprising plurality of CMOS gas chip sensors oriented in different direction from one another and also comprising walls to portion each CMOS gas chip sensor array according to the present disclosure.
Figure 6: shows direction of deposition of various metal oxides onto the CMOS gas chip sensor array of Figure 5a and Figure 5b.
Figure 7a: shows a metal oxide deposited on the CMOS chip gas sensor bridging the nano gap of the electrode and gap between the heater and electrode according to an embodiment of the present disclosure.
Figure 7b: shows a metal oxide deposited on the CMOS chip gas sensor bridging only the nano gap of the electrode according to an embodiment of the present disclosure.
Figure 7c: shows ZnO deposited on the CMOS chip gas sensor according to an embodiment of the present disclosure.
Figures 8a and 8b: shows gas sensing mechanism in a CMOS chip gas sensor according to an embodiment of the present disclosure.
Figure 9: shows a graph showing I-V characteristic of the CMOS chip gas sensor array, indicating the heating according to an embodiment of the present disclosure.
Figures 10a and 10b: shows a simulation result of an in plane heater in the CMOS chip gas sensor according to an embodiment of the present disclosure.
Figure 11: shows a graph showing I-V characteristic result from the simulation result of the in plane heater according to an embodiment of the present disclosure.

The figures depict embodiments of the disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the disclosure described herein.

DETAILED DESCRIPTION OF THE DISCLOSURE
The foregoing has broadly outlined the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. The novel features which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

It is to be noted at this point that all of the above described components, whether alone or in any combination, are claimed as being essential to the disclosure, in particular the details depicted in the drawings and reference numerals in the drawings are as given below.

Referral Numerals

Description Referral numeral
Base substrate layer 1
Intermediate substrate layer 2
First metal layer 3a
Second metal layer 3b
Notch region 4
Contact pads 5, 6
Suspended structure of a portion of first metal layer 7a
Suspended structure of a portion of second metal layer 7b
Nano gap in the second metal layer (electrode) 8
Metal oxide deposited in the nano gap 8a
CMOS chip gas sensor 100
A Sensor array 200
Walls 300

The present disclosure relates to a gas sensor. More particularly, the present disclosure provides a method of forming a gas sensor array with a suspended in-plane micro/nano heater which serves as a shadow mask to grow in-plane metal oxide film to bridge a nano gap metal electrode as a sensing film. The method uses top-down processing technique to form nanostructured sensor. The method involves steps of creating an in-plane heater for the gas sensor array. Next, different metal oxides are deposited on different array elements of the gas sensor array using side-walls of heater and electrodes as shadow masks. The in-plane metal oxide film is grown as a sensing film, with a particular angle of incidence with respect to base substrate layer, which is used to bridge the nano gap metal electrode. The nano gap is created by electro migration technique to host the sensing element, but other techniques can also be used to create gap.

Figure 1 illustrates top and side views of CMOS chip gas sensor (100) according to an exemplary embodiment of the present disclosure. The CMOS chip gas sensor (100) comprising a base substrate layer (1) made of Silicon (Si), an intermediate substrate layer (2) made of Silicon Dioxide (SiO2), formed over the base substrate layer (1), at least two metal layers (3a and 3b) made of platinum (Pt), formed on the intermediate substrate layer (2). A first metal layer (3a) and a second metal layer (3b) are configured as a heater and an electrode respectively. The metal layers (3a, 3b) have varying cross sectional areas and are spaced apart by a predetermined gap ranging from about 10 nm to 1000 nm. The electrode comprising a gap for depositing predetermined metal oxide material in the gap. The gap in the electrode is a nano gap. The heater is configured for inducing heat to the metal oxide material. Further, in one embodiment, a notch region (4) is formed in the intermediate substrate layer (2) to create suspended structures (7a, 7b) of a portion of the first metal layer (3a) and the second metal layer (3b) respectively at the notch region (4). Plurality of contact pads (5, 6) are provided on the at least two metal layers (3a and 3b) for electric probing. In one embodiment, the at least two contact pads (5, 6) are formed over the intermediate substrate layer (2) by a method selected from a group comprising radio frequency (RF) sputtering DC sputtering, e-beam evaporation, thermal evaporation. In one embodiment the gap is formed in the region which is having cross section area less than the cross section area of other part on the second metal layer (3b).

Figure 2 illustrates magnified portion ‘A’ indicated in the Figure 1 according to an embodiment of the present disclosure. The notch region (4) formed in the intermediate substrate layer (2) creates suspended structures (7a and 7b) of a portion of first metal layers (3a) and the second metal layer (3b) at the notch region (4).

Figure 3a illustrates Scanning Electron Microscope (SEM) image of the CMOS gas sensor chip (100).

Figure 3b illustrates a magnified portion “B” indicated in Figure 3a to illustrate a nano gap (8) created between the electrodes according to an embodiment of the present disclosure. The nano gap (8) in the electrode along with predetermined metal oxide deposited at the nano gap (8) is an active sensing part in the CMOS chip gas sensor (100). The nano gap electrode of the CMOS chip gas sensor (100) is created by standard electro-migration technique. By applying large electric ?eld (across the long metal line), the momentum of the moving electrons is transferred to metal atoms that occupy the lattice sites of the metal line, which results in gradual movement of the metal atoms and finally a nano gap (8) is created in the second metal layer (electrode). The figure 3b clearly shows the creation of the nano gap (8) at high voltage (1.6 V). A predetermined metal oxide is shadow deposited, with a predetermined angle of incidence ranging from 0 degree to 360 degrees with respect to base substrate layer (1), at the nano gap (8) to bridge/close the nano gap (8) of the electrode and to bridge the gap between the first metal layer (3a) and the second metal layer (3b). Hence, the bridged nano gap (8) is acting as an active CMOS chip gas sensor (100) for sensing presence of a predetermined gas. The metal oxide with proper temperature provided by the in-plane heater senses the presence of gas when the gas comes in vicinity of the deposited metal oxide on the electrode.

Figure 4 illustrates manufacturing steps of CMOS gas chip sensor array (200) according to an embodiment of the present disclosure. Firstly, the method of manufacturing CMOS chip gas sensor array (200), comprising acts of forming a base substrate layer (1). In one embodiment, the base substrate layer (1) is a p-type Silicon wafer. Other substrates such as n-type Silicon wafer, other semiconducting substrates such as Germanium, and other insulating substrates such as glass can also be used. The Silicon wafer is polished and cleaned using RCA for growing an intermediate substrate layer (2). The intermediate substrate layer (2) is formed by thermally growing over the base substrate layer (1). In one embodiment, the intermediate substrate layer (2) is silicon dioxide layer which is grown using dry oxidation. Other intermediate substrate layers such as CVD grown Silicon oxide, spin-on glass, silicon nitride etc. can also be used. The intermediate substrate layer (2) is coated with poly methyl methacrylate (PMMA)/EL9 resist for about 100 nm. Other e-beam photoresists such as HSQ, or other optical photoresists such S1813 can also be used. After photoresist coating of the intermediate substrate layer (2), a plurality of at least two metal layers (3a and 3b) are formed on the intermediate substrate layer (2). The metal layers (3a and 3b) are formed by pattering the coated photoresist using Raith eLiNE and thereafter thin films of Pt is radio frequency (RF) sputtered with a thickness of about 50 nm after which lift off is performed. The metal layers (3a, 3b) are configured into a first metal layer (3a) as a heater and a second metal layer (3b) as an electrode comprising a gap. The gap can be formed by any known method in the art, for example, but not limiting to, etching and heating. After the lift off, the lithography process is carried onto the intermediate substrate layer (2) to realize four contact pads (5, 6) contacting the heater and the electrode. The Reactive Ion Etching (RIE) is performed to release the oxide to form the suspended heater and sensors using gases such as CF4 of 50 sccm, oxygen (O2) of 20sccm, power of 100W, pressure of 100mTorr and time of 20 minutes. A notch region (4) is formed in the intermediate substrate layer (2) by the Reactive Ion Etching process. The notch region (4) thus created creates a suspended structure (7a) of a portion of the first metal layer (3a) and a suspended structure (7b) of a portion of the second metal layer (3b) at the notch region (4). The RIE time is optimized so that only a central thin beam portion of the metal layers (3a, 3b) is released because of lateral etch, whereas relatively bigger contact pads (5, 6) are intact and give enough support to beam of the metal layers (3a, 3b). In one embodiment, the plurality of first metal layers (3a) of the plurality of CMOS chip gas sensor (100) forms a plurality of side walls to act as shadow mask, allowing the predetermined metal oxide material in only one angle of incidence with respect to base substrate layer, to be deposited to bridge the gap on predetermined second metal layer (3b). Predetermined metal oxide material is deposited with a specific angle of incidence ranging from 0 degrees to 360 degrees with respect to base substrate layer (1) to close the gap for each of the plurality of the two metal layers (3a and 3b). The metal oxide deposited bridges the nano gap (8) created in the electrode (second metal layer) and gap between the electrode and the heater. In one embodiment, orientation of each of the plurality of the two metal layers (3a and 3b) is different to act as shadow mask for depositing the predetermined metal oxide material on the predetermined nano gap (8) of the CMOS chip gas sensor (100), with a specific angle of incidence with respect to base substrate layer (1). In one embodiment, at least one of the plurality of the two metal layers (3a and 3b) is deposited with a different predetermined metal oxide material. In one embodiment, the at least two metal layers (3a, 3b) are formed using lithography process selected from a group comprising photo-lithography process, laser lithography process, e-beam lithography process.

Figure 5a shows top view of the sensor array (200) comprising plurality of the CMOS chip gas sensors (100) according to the present disclosure. In one embodiment, the sensor array (200) is a 2X2 sensor array, i.e. the array comprises a total of four CMOS chip gas sensors (100). In one embodiment, the plurality of first metal layers (3a) of the plurality of CMOS chip gas sensor (100) forms a plurality of side walls to act as shadow mask, allowing the predetermined metal oxide material in only one angle of incidence with respect to base substrate layer, to be deposited to bridge the gap on predetermined second metal layer (3b). In one embodiment, orientation of each of the plurality of the two metal layers (3a and 3b) is different to act as shadow mask for depositing the predetermined metal oxide material on the metal layer (3b) at the nano gap (8), with a specific angle of incidence with respect to base substrate layer. In one embodiment, the predetermined metal oxide material deposited in the metal layers (3b) is different, i.e. the first metal layer (3a) which is a heater becomes a shadow mask for depositing the predetermined metal oxide onto the nano gap (8) of the electrode of the second metal layer (3b), only when the angle of incidence with respect to base substrate layer, matches a predefined value.

Figure 5b illustrates top view of the CMOS gas chip sensor array (200) comprising plurality of CMOS gas chip sensors (100) oriented in different direction from one another and also comprising plurality of walls (300) to portion or partition each CMOS gas chip sensor (100) according to an exemplary embodiment of the present disclosure. The plurality of walls (300) are formed on the intermediate substrate layer (2) of predetermined thickness such that the walls (300) acts as a mask for deposition of the predetermined metal oxide on a predetermined CMOS gas chip sensor. The plurality of walls (300) is formed using lithography process selected from a group comprising photo-lithography process, laser lithography process, e-beam lithography process.

Figure 6 illustrates direction of deposition of various metal oxides onto the CMOS gas chip sensor array (200) of Figure 5a and Figure 5b. In an exemplary embodiment, a predetermined metal oxide material (8a) is deposited in the nano gap (8) of the electrode. Electrical property of the metal oxide material changes on exposure to gas. The metal oxide material (8a) deposited in the nano gap (8) of the electrode is selected from a group comprising WO3, V2O5, ZnO, BaTiO3, CuO, SnO2 etc. The deposition of the various metal oxides are done for each of the array element. The angle of incidence during deposition is different for each element in the array. This helps the heater element to act as shadow mask.

Figure 7a illustrates a metal oxide (8a) deposited on the CMOS chip gas sensor (100) at the nano gap (8) created in the electrode and also the gap between the heater [first metal layer (3a)] and the electrode [second metal layer (3b)] according to an exemplary embodiment of the present disclosure. Bridging or closing the gap between the electrode and the heater enhances sensing efficiency. The metal oxide (8a) is deposited using the sputtering optimization by applying shadow structure technique. The heater/first metal layer (3a) acts as mask to deposit a metal oxide on electrodes (3b) by sputtering, by appropriately tilting and rotating the substrate. The shadow deposition technique can be realized by sputtering, e-beam evaporation, and thermal evaporation.

Figure 7b illustrates a metal oxide (8b) deposited on the CMOS chip gas sensor (100) bridging only the nano gap (8) of the electrode [second metal layer (3b)] according to an exemplary embodiment of the present disclosure. The metal oxide (8a) is deposited using the sputtering optimization by applying shadow structure technique. The heater/first metal layer (3a) acts as mask to deposit a metal oxide on electrodes (3b) by sputtering, by appropriately tilting and rotating the substrate. The shadow deposition technique can be realized by sputtering, e-beam evaporation, and thermal evaporation.

Figure 7c illustrates ZnO deposited on the sensor (100) according to an exemplary embodiment of the present disclosure. The metal oxides are deposited on the electrodes using the sputtering optimization by applying shadow mask technique. The heater/first metal layer beam (3a) acts as mask to deposit a metal oxide on electrodes by sputtering, by appropriately tilting and rotating the substrate. The shadow deposition technique can be realized by sputtering, e-beam evaporation, thermal evaporation. For example, ZnO is deposited parallel to the substrate by reactive sputtering by tilting the substrate close to 90oC. Only one element of the array is covered by ZnO due to the shadow effect of metal layers. The tilt angle can be adjusted appropriately to get mixture of metal oxides, as appropriate to generate array elements with different sensing characteristics.

Figures 8a and 8b illustrates gas sensing mechanism in a CMOS chip gas sensor (100) according to an embodiment of the present disclosure. In an exemplary embodiment, ZnO (metal oxide) is known to be a potential candidate for gas sensor. A polycrystalline semiconductor has the structure with a large number of grains and grain boundaries. In contrast to the single crystalline materials, polycrystalline materials give rise to local potential barriers between the grains. The electrical properties of the surface of a thin film and the surface boundaries between the grains are affected by the adsorption and desorption of gaseous molecules. Oxygen ions can be found at the grain boundaries. However, this reaction is typically activated at high temperature, thus necessitating the integration of micro heater along with metal oxide. At elevated temperature, O2 is chemisorbed by gaining electrons from the surface. Due to these adsorptions, the barrier height or resistance of the material increases (Ro) as shown in Figure 8a. Hydrogen molecules react with the adsorbed oxygen and negatively charged electrons come back to the bulk and hence the barrier height or resistance decreases as shown in Figure 8b. This is true for n-type metal oxide. However for p-type metal oxide, the resistance increases. Therefore, by measuring the change in the resistance of the semiconductor oxide thin films, various gases can be detected. The sensitivity is defined as S=?R/Ro×100 where, ?R is the change of resistance and Ro is the initial resistance before introducing the Hydrogen.

Figure 9 illustrates a graph showing I-V characteristic of the CMOS chip gas sensor array (200), indicating the heating according to an embodiment of the present disclosure. The graph illustrates that, resistance of the electrode (sink) is changing with applied voltage on the heater (source). Thus, one can adjust the sensitivity of the gas sensor using the heater.

Figures 10a and 10b illustrates a simulation result of an in-plane heater in the CMOS chip gas sensor (100) according to an embodiment of the present disclosure. High temperature is generated at the middle of the suspended heater. Most of the gas sensing operation occurs at around 300oC and this temperature can be achieved easily at very low power (5mW) by this suspended heater.
Figure 11 illustrates the power versus temperature curve to represent the heating efficiency of the in-plane heater, to heat the nano gap electrode, according to an embodiment of the present disclosure. The I-V characteristic results for the source and sink (Figure 9) to identify the power dissipation (source) and corresponding temperature at nano gap electrode (sink).

Additional features and advantages are realized through various techniques provided in the present disclosure.

Advantages
In an embodiment of the present disclosure, nanostructured sensor is realized using simple top-down processing technique.

In an embodiment of the present disclosure, heating element is realized in-plane with sensing element.

In an embodiment of the present disclosure, the nano gap is created by electro migration technique to host the sensing element.

In an embodiment of the present disclosure, the gas sensor array can be easily integrated using post processing of Complementary Metal Oxide Semiconductor (CMOS) chip.

In an embodiment of the present disclosure, the metal oxide is deposited selectively on the nano gap region by shadow deposition technique, by adjusting the angle of incidence with respect to base substrate layer.

Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by any claims that issue on an application based here on. Accordingly, the disclosure of the embodiments of the invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

Equivalents
With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity.

It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes but is not limited to,” etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to inventions containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should typically be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, typically means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, and C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). In those instances where a convention analogous to “at least one of A, B, or C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, or C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase “A or B” will be understood to include the possibilities of “A” or “B” or “A and B.”

In addition, where features or aspects of the disclosure are described in terms of Markush groups, those skilled in the art will recognize that the disclosure is also thereby described in terms of any individual member or subgroup of members of the Markush group.

While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.
,CLAIMS:1. A CMOS chip gas sensor (100), comprising:
a base substrate layer (1);
an intermediate substrate layer (2) formed over the base substrate layer (1),
at least two metal layers (3a and 3b) formed on the intermediate substrate layer (2), wherein first metal layer (3a) of the at least two metal layers (3a and 3b) is configured as a heater and second metal layer (3b) of the at least two metal layers (3a and 3b) is configured as an electrode comprising a gap for depositing predetermined metal oxide material in the gap;
a notch region (4) is formed in the intermediate substrate layer (2) to create suspended structures (7a and 7b) of a portion of the first and second metal layers (3a and 3b) respectively at the notch region (4); and
contact pads (5, 6) are provided on the at least two metal layers (3a and 3b) for electric probing.

2. The CMOS chip gas sensor (100) as claimed in claim 1, wherein the heater is configured for inducing heat to the metal oxide material.

3. The CMOS chip gas sensor (100) as claimed in claim 1, wherein a nano gap (8) is formed in the suspended second metal layer (3b) by electro-migration.

4. The CMOS chip gas sensor (100) as claimed in claim 1, wherein a predetermined metal oxide material (8a) is deposited at predetermined angle of incidence to bridge the gap between the first metal layer (3a) and the second metal layer (3b), and the nano gap (8) in the second metal layer (3b).

5. The CMOS chip gas sensor (100) as claimed in claim 4, wherein electrical property of the metal oxide material (8a) changes on exposure to gas.

6. The CMOS chip gas sensor (100) as claimed in claim 1, wherein the metal layers (3a, 3b) have varying cross sectional areas.

7. The CMOS chip gas sensor (100) as claimed in claim 1, wherein material composition of the base substrate layer (1) is Silicon (Si).

8. The CMOS chip gas sensor (100) as claimed in claim 1, wherein material composition of the intermediate substrate layer (2) is Silicon Dioxide (SiO2).

9. The CMOS chip gas sensor (100) as claimed in claim 1, wherein material composition of the metal layer (3) is platinum (Pt).

10. The CMOS chip gas sensor (100) as claimed in claim 1, wherein the metal oxide material deposited in the gap forms a gas sensitive portion and the metal oxide material is selected from a group comprising WO3, V2O5, ZnO, CuO, BaTiO3, and SnO2.

11. The CMOS chip gas sensor (100) as claimed in claim 1, wherein the at least two contact pads (5, 6) is formed over the intermediate substrate layer (2) by a method selected from a group comprising radio frequency (RF) sputtering, DC sputtering, e-beam evaporation, thermal evaporation.

12. A sensor array (200) comprising:
a CMOS chip gas sensor (100) comprising a base substrate layer (1);
an intermediate substrate layer (2) formed over the base substrate layer (1);
plurality of at least two metal layers (3a and 3b) formed on the intermediate substrate layer (2), wherein each of the plurality of the two metal layers (3a and 3b) comprising:
first metal layer (3a) of the at least two metal layers (3a and 3b) is configured as a heater and second metal layer (3b) of each of the plurality of at least two metal layers (3a and 3b) is configured as an electrode comprising a gap for depositing predetermined metal oxide material in the gap to form a gas sensitive portion;
a notch region (4) is formed in the intermediate substrate layer (2) to create a suspended structures (7a and 7b) of a portion of the first and second metal layers (3a and 3b) respectively at the notch region (4); and
at least two contact pads (5, 6) of predetermined thickness and predetermined length are provided on the at least two metal layers (3a and 3b) for electric probing.

13. The sensor array (200) as claimed in claim 12, wherein orientation of each of the plurality of the two metal layers (3a and 3b) is different to act as shadow mask for depositing the predetermined metal oxide material, and allow the nano gap in an element of the sensor array (200) to be bridged only when predetermined angle of incidence is used for deposition.

14. The sensor array (200) as claimed in claim 12, wherein the predetermined metal oxide material in at least one of each of the plurality of the two metal layers (3a and 3b) is different.

15. The sensor array (200) as claimed in claim 12, wherein at least one of the plurality of the two metal layers (3a and 3b) is deposited with a predetermined metal oxide material at a predetermined angle of incidence.

16. The sensor array (200) as claimed in claim 12, wherein the plurality of first metal layers (3a) of the plurality of CMOS chip gas sensor (100) forms a plurality of side walls to act as shadow mask, allowing the predetermined metal oxide material in only one angle of incidence with respect to base substrate layer, to be deposited to bridge the gap on predetermined second metal layer (3b).

17. A method of manufacturing CMOS chip gas sensor array (200), comprising acts of:
forming a base substrate layer (1);
forming an intermediate substrate layer (2) formed over the base substrate layer (1),
forming form plurality of at least two metal layers (3a and 3b) formed on the intermediate substrate layer (2), wherein first metal layer (3a) of the at least two metal layers (3a and 3b) is configured as a heater and second metal layer (3b) of the at least two metal layers (3a and 3b) is configured as an electrode comprising a gap to form a gas sensitive portion; providing a notch region (4) in the intermediate substrate layer (2) to create suspended structures (7a and 7b) of a portion of the first and second metal layers (3a and 3b) respectively at the notch region (4); and
angular deposition of predetermined metal oxide material, with a predetermined angle of incidence to bridge the gap for each of the plurality of the two metal layers (3a and 3b).

18. The method as claimed in claim 17, wherein orientation of each of the plurality of the two metal layers (3a and 3b) is different to act as shadow mask for depositing the predetermined metal oxide material.

19. The method as claimed in claim 17, wherein at least one of the plurality of the two metal layers (3a and 3b) is deposited with a different predetermined metal oxide material.

20. The method as claimed in claim 17, wherein the intermediate substrate layer (2) is thermally formed over the base substrate layer (1).

21. The method as claimed in claim 17, wherein the at least two metal layers (3a, 3b) are formed using lithography process selected from a group comprising photo-lithography process, laser lithography process, e-beam lithography process.