Description
BACKGROUND
1. Field of the Invention
The invention relates generally to communication system and more particularly to a communication receiver providing enhanced performance.
2, Related Art
In a communication system, a sequence of bits representing data is encoded and modulated before transmitting over a communication channel The transmitter's front-end, the communication channel and the receiver's front-end often introduce noise and impairments to the transmitted signal. Such noise and impairments to the transmitted signal pose challenges at the receiver for demodulating and decoding the signal to the desired performance. In general receiver performance may be quantified in terms of bit error rate (BKR), signal to noise ratio (SNR) or convergence-time, among other metrics known to those skilled in the art.
Often, the receiver is designed to adaptively adjust its internal parameters/ values to compensate for the impairments prior to decoding the transmitted data bit to the desired accuracy. For example, values of various filter coefficients may be adaptively adjusted to attain the desired receiver performance. The coefficients are adjusted based on an error signal generated as the difference between the data referred at two different points in the signal processing path of the receiver.
In order to enable a receiver to adjust its internal parameters before decoding a data sequence, a dummy data sequence (often referred to as a training sequence) is transmitted prior to transmitting data. The receiver adjusts its internal parameters (to target a receiver performance metric) during the transmission of training sequence. As a result, the data sequence following the training sequence is decoded with the desired receiver performance.
Additionally, certain receiver architectures rely on past-decisions to augment the decision on the presently received signal (corresponding to a transmitted symbol).
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be described with reference to the following accompanying
drawings.
Figure 1 is a block diagram of a Gigabit Ethernet transceiver providing an example
environment in which present invention may be implemented.
Figure 2 is a flowchart illustrating the generation of the error signal in accordance with an
aspect of the present invention
Figure 3 is a block diagram illustrating generation of the error signal in accordance with an
aspect of the present invention.
Figure 4 depicts a decision feedback sequence estimator (DFSE) based on the parallel decision feedback decoder (PDFD) approach in a prior embodiment.

Figure 5a is a block diagram of a Gigabit Ethernet transceiver implemented in accordance with the present invention.
Figure 5b-5g illustrate various phases of operation of the Gigabit Ethernet transceiver in accordance with the present invention.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.
DETAILED DESCRIPTION 1. Overview
According to an aspect of the present invention, a receiver generates a predicted data/symbol sequence and computes an error signal as the difference between the predicted-symbol and the received signal. The internal parameters of the receiver are adjusted based on the computed error signal. In one embodiment, such predicted data sequence is generated by simulating the conditions at the corresponding transmitter during the training-phase. As a consequence of using predicted symbols as opposed to the use of symbols derived from the received signal, the error signal is determined more accurately.
According to another aspect of the present invention, a receiver using past-state information for decoding a present symbol determines the past-state information using the predicted symbols. This results in the receiver having an accurate past-state information (as opposed to using past-state information derived from the received signal), thereby allowing the receiver to converge within bounded-time.
In an example embodiment of the present invention the use of predicted symbols to generate past-state information is applied to a parallel decision feedback decoder (PDFD). The present invention also provides an optimal architecture that uses a single set of adaptation logic for the multiple feedback equalizers required by the PDFD.
Several aspects of the invention are described below with reference to examples for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details, or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the features of the invention.
2. Example Communication Receiver
The invention is described and illustrated with reference to a Gigabit Ethernet transceiver for better understanding and to highlight its salient features. It may be appreciated that the invention is described with reference to the example system merely for illustration. The extension of the approaches to other communication systems will be apparent to one skilled in the relevant art by reading the disclosure provided herein, and such implementations arc contemplated to be covered by various aspects of the present invention. Accordingly, the operation of a Gigabit Ethernet transceiver is described first below.

Figure 1 is a block diagram of a Gigabit Ethernet transceiver 100. The transceiver 100 connects to the CAT-5 cable via an RJ-45 connector connected to a line transformer 190. On the other end, 100 interfaces to an Ethernet MAC 180 over an interface such as the gigabit media independent interface (GMII) or the reduced GMII (RGMII).
As there are four independent twisted-pair channels, the transceiver makes use of four equivalent front-end modules - 101a, 101b, 101c and 101d to process the signals received on them to a point where they can be processed by a common receiver 140.
Transceivers using Gigabit Ethernet make use of all four twisted-pairs of the CAT-5 unshielded twisted-pair (UTP) cable operating in full-duplex employing a 5-level pulse amplitude modulation (PAM) signaling scheme to achieve a data rate of 1000Mbps in both directions at a bit error-rate (BER) of 10-9 at a range of up to 100 metres.
The use of a 5-level signaling scheme in 1000BASE-T vs. a 3-level scheme used in 100BASE-TX results in an additional signal to noise ratio requirement of 6dB for the 1000BASE-T receiver to attain the same BER performance as 100BASE-TX.
Additionally, the use of a full duplex signaling scheme whereby the transceiver both transmits and receives on the same twisted-pair results in leakage of the transmitted signal into the receiver due to imperfections in the hybrid-canceller that is used to subtract the transmitted signal from the signal seen at the receiver. Another impairment that arises from the use of full-duplex transmission on the same twisted-pair is echo, which is a result of the transmitted signal being reflected back to the receiver due to impedance variations along the cable.
Further, cross-coupling between each of the signal-pairs results in both near-end and far-end cross-lalk - NEXT and FEXT respectively depending on the point of coupling. NEXT happens when the signal transmitted on one of the twisted-pairs of the local transceiver couples and interferes with the received signal on another twisted-pair at the local transceiver. FEXT occurs when the signal transmitted on one of the twisted-pairs of the local transceiver couples and interferes with the received signal on another twisted-pair at the remote transceiver.
In addition to these impairments, the gigabit receiver has to combat dispersive effects of the channel which result in smearing of symbols resulting in inter-symbol-interference (ISI) of the received signals. In the following we shall describe one of the front-end receiver modules 101a in further detail.
101a comprises analog-front-end 110a. Analog front end 110a comprises hybrid canceller, receive filters and a variable gain amplifier (VGA), collectively referred to as 111a and an analog to digital converter 112a. The hybrid canceller of Il1a is responsible for isolating the transmittcd-signal from 170a, from the received-signal (transmitted by the link-partner) such that the signal at the output of the hybrid-canceller that is fed into the ADC 112a comprises of only signal components of the link-partner's transmission. The filters of 111a are responsible for rejecting unwanted frequency components of the signal, while the VGA adjusts the signal-level at the input to ADC 112a to a level such that the output of 112a

does not clip. The ADC 112a converts the analog-signal to a digital-signal so that it can be processed digitally to compensate for channel and analog-front-end impairments, and to demodulate the transmitted data from the resultant compensated signal. Gain-control module 120a determines the gain to be applied by the VGA of 111a.
As mentioned previously, impairments such as echo, trans-hybrid-leakage and NEXT are a direct consequence of the full-duplex transmission utilized by the gigabit transceiver. As these impairments are caused by transmissions emanating from the transceiver 100 itself, they can be estimated and cancelled from the received signal, improving the signal-quality and consequently, overall system performance. The echo-canceller 125a uses knowledge of the signal transmitted on the same twisted-pair as the receiver 101a to determine an estimate of the echo in the received signal as a result of the transmission by 170a. Likewise, the NEXT-cancellers 126a, 127a and 128a, respectively generate estimates of the near-end cross-talk on the receive pair connected to 101a, as a result of transmissions on pairs corresponding to transmit analog front-ends 170b, 170c and 170d. The summation block 130a computes the sum of the estimates of the echo and NEXT-signals from 125a, 126a, 127a and 128a, respectively. Element 131a is responsible for subtracting this estimate from the signal at the output of 112a, resulting in an input to the feed-forward equalizer (FFE) 132a.
In one embodiment, the Gigabit Ethernet receiver employs the use of a decision feedback equalization scheme in order to compensate for the dispersive effects of the channel which results in the received signal having both pre-cursor and post-cursor inter-symbol-interfercnce (ISI). The FFE 132a is responsible for cancelling the effects of pre-cursor ISI, rendering the output of 132a minimum-phase in nature. The feed-back equalizer (FBE) 135a computes an estimate of the post-cursor ISI, which is subtracted from the output of 132a by element 133a and fed to decision device 134a, which computes estimates of the transmitted 5-PAM symbol.
Ethernet-transceivers typically employ the use of a sub-sampled signal-processing architecture where the signal is sampled and processed at baud-rate as opposed to using a rate which satisfies the Nyquist-criterion. As a direct consequence of this, it becomes critical that the ADC samples the received signal at the correct sampling-instant.
As a consequence of the digital processing of the signal by 101a being done at baud-rate, the sampling-instant of the ADC 112a is key to ensuring the maximal opening of the 'eye', and hence a suitably high SNR. While the ADC 112a samples the analog signal at the output of 111a at baud-rate - 125MHz as specified in IEEE 802.3-2002 Specification Clause 40 (hereafter referred to as "Gigabit Ethernet standard"), the timing-control module 137a controls the sampling-instant or sampling-phase at which 112a samples the signal. Additionally, as the levels of echo, NEXT, and dispersive effects are a function of the channel itself, the coefficients of the cancellers - 125a, 126a, 127a, 128a and equalizers -132a and 135a are dependent on the cable used. Moreover, these may also vary in time as a result of environmental variations. Thus, these filters are realized as adaptive filters.
Like 101a, front-end receivers 101b, 101c and 101d determine estimates of the 5-PAM signal transmitted by the link-partner. The collection of estimates is fed into the Common Receiver 140, which among other functions, is responsible for translating the 4-dimensional

5-level PAM (4D-5PAM) signal to the originally transmitted bit-stream by applying the necessary decoding and dcscrambling functions; prior to sending it to the external Ethernet MAC 180.
The common transmitter 160 is responsible for converting a bit-stream received from the Ethernet MAC 180 to a 4D-5PAM signal. It encompasses the functions of scrambling and encoding the data. Each of the 4-dimensions is fed through a separate transmit AFE - 170a, 170b, 170c and 170d, respectively, which among other functions are responsible for converting the digital signal to an analog one at the appropriate level, filtering it and transmitting to the line transformer 190 via the respective hybrid cancellers of receiver front-ends - 101a, 101b, 101c and lOld.
System Controller 150 controls and coordinates the functioning of the various elements of the transceiver 100 in accordance with the protocol and specification of the Gigabit Ethernet Standard. Among other functions, it controls the training of the various elements of the front-end receivers 101a through 101d adapting it them to the channel; as well as controlling the interfaces to the MAC 180.
The Gigabit Ethernet standard specifies a blind start-up scheme, whereby the receiver needs to estimate the channel conditions without the exact knowledge of the training sequence transmitted by the transmitter. The decision-feedback scheme as is well known to those skilled in the relevant art is a popular scheme for training adaptive filters under such conditions. Element 136a is responsible for computing the error between the input to the decision device and its output and is used among other purposes, for training the coefficients of the cancellers and equalizers in 101a.
The Gigabit Ethernet standard requires for blind startup using a pseudo-random training sequence (referred to as IDLEs). IDLEs are constituted of a 3-level PAM signal transmitted on each of the 4 twisted pairs. On completion of the training-phase where only IDLEs are transmitted, the transceivers enter the normal-phase during which a transmitter transmits data; in the absence of data reverting to the transmission of IDLEs.
While the IDLE sequence is constituted of a 3-PAM signal containing signal-levels drawn from the set of points {-2, 0,+2}, the 5-PAM signal used for data transmission is drawn from the set of points {-2,-l,0,+l,+2}. As mentioned previously, to achieve the same performance, the use of the 5-level signal set requires an additional 6dB of SNR-margin over the 3-level signal set. In order to compensate for the 6-dB additional requirement in SNR, provides for the use of trellis coded modulation (TCM) by the transmitter, allowing receivers to potentially realize the inherent coding-gain in the transmitted signal.
The Gigabit Ethernet standard specifies devices with multiple capabilities such as: standard/rate - 10BASE-T/100BASE-TX/1000BASE-T; and duplex -full/half-duplex. The auto-negotiation protocol specified in IEEE802.3 Specification Clause 28 (hereafter referred to as "Auto-negotiation protocol") is used by two transceivers on an UTP-cable to determine each other's capabilities so as to negotiate to a common mode of communication. When negotiating to the Gigabit-Ethernet mode, the conclusion of the auto-negotiation protocol results in one of the link partners being designated 'Master' and the other 'Slave',

Both Master and Slave startup differently with the Slave being silent for the first part of the training while the Master transmits IDLEs; and subsequently both Master and Slave transmitting IDLEs till training is complete. While training process is different for both Master and Slave transceiver, on conclusion of the training process, both Master and Slave are able to transmit and receive data from onc-another. A transceiver communicates it's 'loc rcvr_status' indicating its readiness to receive data from its link-partner via special encoding of its transmitted IDLE sequence.
A 33-bit linear-feedback-shift-register (LFSR) is used in the transmitter to both generate the IDLEs as well as to drive a data-scrambler which scrambles the data prior to transmission. The taps of the LFSR are different for both Master and Slave, requiring the receiver to synchronize to the LFSR state used by its link-partner prior to being able to correctly receive its transmission.
3. Generation of the Error Signal.
Figure 2 is a flowchart illustrating the generation of the error signal according to an aspect of the present invention. The flowchart is described with reference to Figure 1 merely for illustration. The flowchart begins in step 201 and control passes to step 210.
In step 210, the receiver predicts the transmitted symbol. In one embodiment the receiver predicts the symbol as the transmitted symbol associated with the currently received signal by simulating the conditions at the transmitter. For example with reference to description above, the receiver may simulate the state of the transmitter's LFSR and hence generate the IDLEs.
In step 230, the receiver generates an error signal based on the predicted symbol and the received signal. In an embodiment of the present invention, the receiver generates an error signal as the difference between the predicted symbol and the received signal corresponding to the current symbol. The received signal may be tapped at a desired point in the signal processing path. For example the received signal may be tapped after performing post-cursor and pre-cursor inter-symbol interference (ISI) compensation. The error signal may be used to adjust the values/parameters of the receivers in 101a-101d as noted above with reference to Figure 1. The flowchart ends in step 299.
As a consequence of using predicted symbols as opposed to the use of symbols derived from the received signal, the error signal is determined more accurately thereby resulting in enhanced performance.
4. Example of a Receiver Generating the Error Signal
As mentioned in the context of prior-art, the Gigabit Ethernet standard mandates a blind-startup scheme using the pseudo-random IDLE sequence which is generated using a 33'bit LFSR running at baud-speed. The receiver trains on the IDLE sequence using the error between the input to the decision device and its output to drive the adaptation of the feed-Ibrward equalizer, feedback equalizer, echo/NEXT cancellers, timing recovery loops.
An aspect of the present invention entails the transceiver performing an initial training using the decision-feedback scheme followed by a data-aided LMS approach. The initial-training is used until a time when the error is sufficiently-low or the 'eye' is open to an

extent where scrambler-seed recovery of the transmitter's scrambler state can be attempted. As the training is incomplete at this point in time - i.e. there are still some errors at the output of the decision device, a probabilistic approach to scrambler seed recovery is used, whereby the receiver assesses the likelihood of the link-partner's transmit LFSR state based on a series of decisions made by the receiver's decision device as opposed to using a single decision. The use of the probabilistic approach to scrambler-seed recovery can be used to lower the overall probability of incorrectly estimating the transmitter's LFSR-state. By adjusting the thresholds of the probabilistic scrambler seed recovery algorithm, the probability of incorrectly asserting the descrambler is locked (referred to as 'scrlock^T in the Gigabit Ethernet standard) can be made arbitrarily low.
On locking its descrambler to the link-partner's transmitter scrambler, the receiver declares 'scr locker whereby it is capable of using the methods of the transmitter, described in the Gigabit Ethernet standard to generate an exact replica of the transmitter's IDLE sequence. In the context of the present invention, these replica IDLEs are referred to as predicted-IDLEsorplDLEs.
According to an aspect of the present invention, pIDLEs may be used for the generation of an accurate error-signal in order to facilitate LMS adaptation of the FFE, FBE, Echo-cancellers, NEXT'Cancellers and the adaptive timing-control-loops.
Figure 3 is a block diagram illustrating generation of the error signal in accordance with the present invention. Gigabit-Ethernet transceiver 300 comprises four front-end receivers -301a, 301b, 301c and 301d each corresponding to one of the twisted pairs coming in from the U TP-cable over the line transformer 390. Transceiver 300 further comprises of a common receiver block 360 that processes the decisions of each of the decision devices of 301a, 301b, 301c and 301d.
On pair-A 301a, the output of the FEE 315a is subtracted from the output of the FFE 310a by element 311a. The output of 311a is fed to the decision device which estimates the PAM symbol transmitted by the transmitter on the corresponding twisted-pair.
During initial training the MUX 340a is configured to select the output decisions of 320a to feed both the error-computation module 330a and the feedback-filter 315a. The output of the error computation module 330a is likewise decision directed and is used to drive the adaptation of the various training-loops in the receiver. A similar process is repeated for each of the front-end receivers 301a, 301b, 301c and 301d.
Upon sufficient opening of the 'eye' on all the front-end receivers, the system controller 341 enables the recovery of the link-partner's transmit scrambler seed by module 350. Upon successfully locking to the link-partner transmitter's scrambler, 350 generates pIDLEs, the corresponding element of which is fed to each of the twisted-pair's front-end receivers - 301a, 301b, 301c and 301d. Once locked and generating valid pIDLEs, 341 may configure MUX 340a to output pIDLEs from 350 for the duration during which it is known that the link-partner is transmitting IDLEs. The pIDLEs represent correct decisions of the decision device 320a and hence, the quality of the inputs to 315a and 330a is improved, resulting in a 'better-quality' of error-signal leading to both faster and more effective training of the receiver. Once all loops are adequately trained and stable; and

prior to receiving data, 341 configures the MUXes of 301a, 301b, 301c and 301d to select the outputs of their corresponding decision device.
The manner in which the Predicted symbols may be used for loading the past state of a receiver according to an aspect of the present invention is illustrated with reference to the decision feedback sequence estimation scheme is described below.
3. Decision Feedback Sequence Estimation
In order to realize the full benefit of the trellis coded modulation scheme as employed by the Gigabit Ethernet transmitter, the receiver must use an appropriate decoding scheme. The choice of decoding scheme is usually a tradeoff between cost/complexity/benefit in the design - a more efficient decoding scheme resulting in higher SNR-margin that may be traded-off for increased range of operation or simpler fixed-point quantization of elements of the design.
While the optimal Maximum Likelihood Sequence fistimator (MLSE) is expected to fully realize the 6dB coding gain of the TCM-code, it has an exponential complexity that makes it difficult to implement. The more popular sub-optimal techniques are divided into two categories - (i) open-loop and (ii) closed-loop. Among the sub-optimal techniques, the closed-loop parallel decision feedback decoder (PDFD) has the best performance. The closed-loop PDFD applies a Viterbi-algorithm to traverse through the code trellis, but instead of choosing a single surviving-path (as a conventional Viterbi-decoder would), it estimates the post-cursor inter-symbol-interference (ISI) derived from tracing-back all the paths of the code trellis through independent feedback filters and subtracts these ISI estimates from the received signal to expand the trellis in the next clock cycle.
Figure 4 depicts a decision feedback sequence estimator (DFSE) based on the PDFD approach 460 in a prior embodiment. In its application to Gigabit-Ethernet, it is expected that the estimates of the post-cursor ISI are subtracted from the pre-cursor ISI-free signal by element 461 which feeds the resultant signal to the Viterbi core 462. Element 461 generates one estimate of ISI-free signals based on the precursor ISI free signal and the outputs of each of the feed-back equalizers - 463a through 463h, each of which generate an independent estimate of the post-cursor-lSI depending on trace-back from each of the states of the Viterbi-core 462.
The Viterbi-core 462 processes each of the ISI-free signals from element 461 to determine the decision from the surviving path, the corresponding surviving state and the traceback (example of past states) from all states (including the surviving state) in every clock cycle. The MUX 464 uses the surviving state information determined by 462 to select the corresponding ISI-free input signal which is fed to element 465. 465 computes the difference between the 'decision from surviving-path' using the surviving state information, and the output of 464 to determine the error-signal. The error signal is used to drive the adaptation of the receiver to the channel and the impairments.
The Gigabit Ethernet trellis-code is an 8-state code. Hence, 462 generates 8 traceback paths to 8 FBEs - 463a through 463h, resulting to 8 estimates of the post-cursor ISI and correspondingly, 8 renditions of an ISI-free signal by 461 to the Viterbi-core 462.

5. Application of Present Invention to Gigabit Ethernet Transceiver
As mentioned in the context of prior-art, the Gigabit Ethernet transmitter employs the use of a trellis-coded modulation scheme on its transmissions. Among the suboptimal decoders, the closed-loop PDFD has the best performance, using past-decisions (with separate trace-backs from each state of the code-trellis) in conjunction with the received signal to derive inputs to the Viterbi core. However, if the PDFD is started up by applying the received signal at the input to the decoder with the feedback filters having no-past memory, there can be no guarantee of the convergence of the PDFD loop over a period of time. The fact that the incoming signal suffers from the impairments only makes matters worse.
Further as the adaptive-loops in the gigabit receiver are constantly running to track any changes in channel and/or clocks/timing, an accurate error signal is required to prevent the receiver-tracking loops from diverging. For the duration when the PDFD-loop has not converged, the output of the PDFD represents unreliable decisions. These unreliable decisions affect the error-signal and may make tracking-loops unstable.
An aspect of the present invention entails the receiver using the predicted-IDLEs determined during part of the scrambler seed recovery phase of training to correctly boot/start-up the PDFD-loop, while ensuring stability in the error signal, thereby not affecting the adaptive tracking loops in the receiver. Further, according to the teachings of the present invention, the PDFD-loop can be 'booted' in finite-time (equivalent to the number of taps in the feedback path of the loop) ensuring the ability to apply the PDFD to Gigabit Ethernet receivers.
The manner in which the Gigabit Ethernet receiver may be implemented incorporating various aspect of present invention is described below with reference to Figures 5a through 5g. Figure 5a is a block diagram of a Gigabit Ethernet transceiver implemented according to the present invention. Figures 5b through 5g depicts various stages/phases of operation of the transceiver in accordance with the present invention.
6. Transceiver in Slavc-mode
Considering startup in the 'Slave-mode' of operation, the system controller 580 of 500 on receiving the IDLEs transmitted by the Master triggers the first phase of training. Figure 5b depicts the connectivity of the various components of 500 during the first-phase of receiver training, which involves the adaptation of the FFE 530 and FBE 539 leading to the recovery of the link-partner transmitter's scrambler seed. The received signal processed by 501 flows through 529, which is initially configured to provide the same delay to the signals irom ail four twisted-pairs.
As the slave is initially silent, there is no Echo and NEXT in the received signal. The output of 562 is thus zero. Thus, element 563 which cancels the estimated echo and NEXT from the output of 529, has no effect on the input to 530 at this stage. The signal flows through the FFE 530 to enter element 532. Element 532 subtracts estimates of the post-cursor intert'erence estimated by the FBE 539 based on decisions of decision device 536, generating inputs to the decision device 536. Thus in the initial phase of receiver training elements 532, 536 and 539 constitute a decision feed-back loop.

MUX 535 selects the error-signal determined by element 537 as the difference between the input to 536 and the output of MUX 556. The error signal computed by element 537 is used to train the FFE, FBE and adaptive timing-loops to a point where the output decisions of 536 are sufficiently reliable; or in other-words the 'eye-diagram' of the input to 536 is sufficiently 'open'. System Controller 580 then triggers 557 to recover the state of the link-partner transmitter's scrambler. As described previously, according to an aspect of the present invention 557 on declaring 'scr_lock=r is additionally capable of generating plDLEs. At this stage, the receiver has also determined the relative skew between all 4-lines, the pair-swaps between the lines and the polarity-swaps on them.
System controller 580 then triggers the second phase of transceiver 500 training, as depicted in Figure 5c. During the second-phase of receiver training, 580 disables the adaptation of all transceiver elements. 580 adjusts the variable-length FIFO 529 to compensate for the relative-skew between lines and to compensate for the polarity swaps on the respective lines. Received samples from 501 flow through 529, getting compensated for skew and polarity-swaps before being passed to the FFE 530. Cross-over switch 531 swaps the outputs of 530 in accordance with the pair-swap determined on the line during the first phase of receiver training. The swapped signal feeds into delay-line 533 whose output is disabled. The delay-line 533 has a length equivalent to the trace-back depth of the Viterbi-core 552 in 555.
During the second-phase of training, the pIDLE generator 557 feeds pIDLEs to the closed-loop PDFD 555 through MUX 550. All eight outputs of MUX 554 are configured to output O's temporarily making the PDFD loop open. Element 551 of the PDFD computes the difference between the output of MUX 550 and each of the eight outputs of MUX 554, which form the input to the Vitcrbi-core 552. The Viterbi-core internally updates the branch-metrics for each state in the codc-trellis and determines the surviving-state. The 4D-SPAM symbol corresponding to the traceback from the surviving state corresponds to the output decision of 552. The trace-back symbols from each of the 8-states are also fed to their corresponding feedback-filter multiply-accumulate (MACs) 553a through 553h.
MUX 556 selects the output of 552, which is fed to the adaptive FBE 539 through crossover switch 538. Cross-over switch 538 compensates for pair-swaps applied by 531 as determined during the first-phase of training, while cross-over switch 540 un-does the effects of 538. The mechanism of un-swapping and swapping as performed by 538 and 540, respectively is necessary to preserve the continuity of the states of 539 which would be altered by the action of 531 during the second-phase of receiver training.
In the second-phase of training, 580 ensures that the received signal from 501 flows through 529, 563, 530 and 531 to completely filled the delay-line 533. Also, 580 ensures that the pIDLEs from 557 flow through 550, 551 and 552 to completely fill the Viterbi-core trace-back memory, the outputs of the Viterbi-core filling the pipe-line of stages -- 556, 538, 539 and 540. The conclusion of the second-phase of training results in the receiver being in a state when if enabled, the output of 533 would correspond with the output of 540, the resultant subtraction by element 534 resulting in a valid error signal at the input to MUX 535.

System controller 580 transitions 500 to the third-phase of training, depicted in Fig 5d. The transmitter 560 is enabled which results in a transmissions of the Slave's IDLEs on the line 590 and the generation of echo/NEXT which manifests itself in the received signal from 501. The transmit symbols from 560 are also fed to the echo/NEXT canceller 562, the output of which represents an estimate of the echo/NEXT component of the signal received from 501. Element 563 cancels the estimated echo/NEXT from the received signal. The output of delay-line 533 and cross-over switch 540 are enabled resulting in the computation of a valid error signal by element 534. This error signal is selected by MUX 535.
System controller 580 enables training of all the adaptive training-loops - the FFE, FBE, Echo/NEXT and the timing-controller. The error-signal is based on pIDLEs resulting in the adaptation being data-aided and hence, LMS as opposed to decision-directed as used in the first phase of receiver training. The LMS-based training results in robust performance.
On conclusion of the third-stage of training after achieving a level of desired training of the various transceiver components and prior to declaring Toc_rcvrstatus=r, 580 configures 500 into a fourth configuration, depicted in Figure 5e. MUX 550 is configured to select the output of 531 and MUX 554, the outputs of the individual FBFs 553a through 553h, to 551. As the adaptive FBE 539 is running on inputs not compensated for pair-swap while the FBF MACs 553a through 553h are, the coefficients generated by it are swapped by the crossover switch 558 before being applied to the FBFs - 553a through 553h.
As the memory of the Viterbi-core 552 and the FBFs - 553a through 553h was previously loaded with correct decisions in the form of pIDLEs, the closure of the PDFD-loop by 554 prior to feeding in of actual-line IDLEs by 550 results in the 'warm-booting' of the PDFD 555. Also, the error used by the adaptation-loops is generated using PIDLEs, ensuring the convergence of the adaptive loops. A further benefit of the transceiver apparatus of 500 is that it requires only one instance of adaptation logic for the FBF 539, allowing for the same coefficients to be applied to the 553a through 553h. 553a through 553h may thus be realized as a simple multiply and accumulate unit, not requiring separate coefficient memory and adaptation logic of a full-fledged adaptive feedback filter such as 539.
580 enables the receive interface between 559 and 580. Likewise, the transmit interface from 580 to 560 is also enabled once 500 detects 'rem-rcvr-status=1' (indicating the link-partners Toc-rcvr-status-1'). System controller 580 configures the adaptive-loops to tracking mode wherein they adapt themselves to slow variations in the channel. The transceiver 500 is now ready for transmission and reception of data over the UTP-cable by the external Ethernet MAC 580.
7. Transceiver in Master-mode
Considering the startup of in the 'Master-mode' of operation, the system controller 580 of 500 triggers transmitter 560 to transmit IDLEs, While the link-partner (Slave) is initially silent, the signal received by 501 represents the echo and NEXT of the IDLE transmission by 500. In a first phase of training, 580 configures the signal paths of 500 as depicted in Ingure 5f The signal received by 501 flows through 529 to 563, which is responsible for cancelling the estimates of the echo/NEXT as determined by 562, from the input to the FFE 530. The signal flows through 530 and 531 and through the decision feedback loop represented by elements 532, 536, 556, 538, 539 and 540. As in the slave-case, MUX 535

selects the error-signal computed by 537 as the difference between the input to 536 and the output of 536. As the signal received by 501 during the first phase of receiver training is constituted entirely of echo and NEXT, 580 enables the adaptation of the echo/NEXT canceller 562.
After detecting the start of transmission of IDLEs by the link-partner, system controller 580 enables the second-phase of transceiver training, also depicted in Figure 5f. During the second-phase, 580 further enables the adaptation of the FFE 530 and FBE 539. Once the adaptation of the transceiver has reached a stage where the outputs of decision device 556 are sufficiently reliable, system controller 580 triggers 557 to recover the state of the link-partner transmitter's scrambler. As described previously, according to an aspect of the present invention, on declaring 'scr-lock^l' 557 is additionally capable of generating plDLEs. At this stage, the receiver has also determined the relative skew between all 4-lines, the pair-swaps between the lines and the polarity-swaps on them, 500 enters a third-phase of training as depicted in Figure 5g.
In the third-phase of training, 580 disables the adaptation of all transceiver elements. Variable-length FIFO 529 is adjusted to compensate for the relative skew between lines and to compensate for the polarity swaps on the respective lines. Variable-length FIFO 561 is adjusted to compensate for the relative skew between lines, allowing for the echo/NEXT estimates to be aligned to the skew-compensated received signal from 529, Cross-over switch 531 swaps the outputs of 530 in accordance with the pair-swap determined in the second-phase of transceiver training, above. The swapped signals feed into Delay-line 533 whose output is disabled. The delay-line 533 has a length equivalent to the trace-back depth of 552 in 555.
pIDLE generator 557 feeds pIDLEs to the closed-loop PDFD 555 through MUX 550. All eight outputs of MUX 554 are configured to output 0's temporarily making the PDFD loop open. Element 551 of the PDFD computes the difference between the output of MUX 550 and each of the eight outputs of MUX 554, which form the input to the Viterbi-core 552. The Viterbi-core internally updates the branch-metrics for each state in the code-trellis and determines the surviving-state. The 4D-5PAM symbol corresponding to the traceback from the surviving state corresponds to the output decision of 552. The trace-back symbols from each of the 8-statcs are also fed to their corresponding feedback-filter MACs 553a through 553h. MUX 556 selects the output of 552, which is fed to the adaptive FBE 539 through cross-over switch 538. Cross-over switch 538 compensates for pair-swaps applied by 531 as determined during the second-phase of training, while cross-over switch 540 un-does the effects of 538 on the output of 539,
In the third-stage of training, 580 ensures that the signal entering 562 subsequent to skew-compensation by 561 has traversed through the length of 562 before being subtracted from the skew-corrected and polarity corrected signal from 530, by element 563, the resultant signal flowing through 530, 531 and completely filling the delay-line 533. Also, 580 ensures that the pIDLEs from 557 flows through 550, 551 and 552 to completely fill the Viterbi-core trace-back memory, the outputs of the Vitcrbi-core filling the pipe-line stages of 556, 538, 539 and 540. The conclusion of the third-phase of training results in the receiver in a state when if enabled, the output of 533 would correspond with the output of

540, the resultant subtraction by element 534 resulting in a valid error signal at the input to MUX 535.
System-controller 580 transitions 500 to the fourth-phase of training, connectivity of which is as depicted in Fig 5d. The output of delay-line 533 and cross-over switch 540 are enabled resulting in the computation of a valid error signal by 534. The error-signal of 534 is
selected by MUX 535.
580 enables training of all the adaptive training-loops - the FFE, FBE, Echo/NEXT and the timing-controller. The error-signal is based on pIDLEs resulting in the adaptation being data-aided and hence, LMS as opposed to decision-directed, resulting in better performance.
On conclusion of the fourth-stage of training after achieving a level of desired training of the various transceiver components and prior to declaring 'loc__rcvr_status=r, 580 configures 500 into a fifth configuration, represented by Figure 5e. MUX 550 is configured to select the output of 531 and MUX 554, the outputs of the individual FBFs 553a through 553h, to 551. As the adaptive FBE 539 is running on inputs not compensated for pair-swap while the FBF MACs 553a through 553h are, the adaptive coeffs generated by it are swapped by the cross-over switch 558 before being applied to the FBFs - 553a through 553h,
As the memory of the Viterbi-core 552 and the FBFs - 553a through 553h was previously loaded with correct decisions in the form of pIDLEs, the closure of the PDFD-loop by 554 and the feeding in of actual-line IDLEs results in the 'warm-booting' of the PDFD 555. Also, the error used by the adaptation-loops is generated using PIDLEs, ensuring the convergence of the training loops. A further benefit of the transceiver apparatus of 500 is that it requires only one instance of adaptation logic for the FBF 539, allowing for the same coefficients to be applied to the 553a through 553h. 553a through 553h may thus be realized as a simple multiply and accumulate unit, not requiring separate coefficient memory and adaptation logic of a full-fledged adaptive feedback filter such as 539.
580 enables the receive interface between 559 and 580. Likewise the transmit interface from 580 to 560 is also enabled once 500 detects 'rem_rcvr_status=r (indicating the link-partners Toc-rcvr-status=r). System controller 580 configures the adaptive-loops to tracking mode wherein they adapt themselves to slow variations in the channel. The transceiver 500 is now ready for transmission and reception of data by the external Ethernet MAC 580,
8. Conclusion
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims: 1/ We claim,
1. A method of generating an error signal in a communication receiver, wherein said
communication receiver receiving an input signal transmitted by a link partner, wherein
said input signal comprises plurality of transmitted symbols, said method comprising:
Generating a predicted symbol corresponding to a symbol transmitted by said link-partner; and
Obtaining an error signal using said predicted symbol and said corresponding input signal, wherein said error signal is used for training, said training comprising the adjustment of a plurality of parameters in said communication receiver.
2. The method of claim 1, wherein said generating generates said predicted symbol without using said input signal.
3. The method of claim 1, wherein said generating generates the predicted symbol by simulating the conditions of a linear feedback shift register comprised in said link partner, wherein a pseudo random sequence is generated using said linear feedback shift registers.
4. The method of decoding a plurality of data symbols using plurality of past state information in conjunction with an input signal, wherein said input signal is received by a communication receiver from a corresponding link partner, said method comprising the steps of
Generating a plurality of predicted symbols;
Determining plurality of said past state information using said plurality of predicted symbols;
5. A communication receiver receiving an input signal, wherein a plurality of training
symbols is encoded in said input signal, said input signal transmitted by a corresponding
link partner, said communication receiver comprising:
A first adaptive feedback device providing an estimate of post-cursor inter-symbol interference using the outputs of a first decision device;
A first subtractor device generating an inter-symbol interference compensated signal from the input signal and said feedback device;
Said first decision device providing decisions on possible encoded symbol from said compensated input signal;
A symbol decoder decoding said encoded symbol with a probability of error from said decision;
A symbol prediction block providing a plurality of predicted symbols as equivalent to said training symbols encoded in said input signal by simulating the conditions of said link partner, where in said symbol prediction block operative when said probability of error is below a threshold value;
A second decision device receiving said predicted symbols and generating predicted decisions from said predicted symbols;
A plurality of a second feedback equalizer, generating a plurality of feedback signals based an corresponding plurality of past-state information of said second decision device and said predicted decisions; wherein said plurality of secondary feedback equalizers deriving their adaptive coefficients from said first adaptive feedback device
6. A communication receiver receiving an input signal, wherein a plurality of symbols is
encoded in said input signal, said input signal transmitted by a corresponding link partner,
said communication receiver comprising:

A first decision device providing decisions on a first plurality of symbols comprised in said input signal received from said link-partner;
A second decision device providing decisions on a second plurality of symbols comprised in said input signal received from said link-partner.
7. The communication receiver of claim 6, wherein said second decision device generates
decisions with a higher reliability than said first decision device.
8. The apparatus for enhancing the blind training of an adaptive communications receiver,
said apparatus comprising:
A controller capable of configuring the transceiver components and controlling their adaptive training;
A decision device to estimate the transmitted symbols;
A training sequence predictor capable of predicting and regenerating the training sequence transmitted by the transmitter;
An error computation device capable of being configured by the controller to compute the error between the received signal and the output of the decision-device; or the error between the received signal and the predicted training sequence by claimed training sequence predictor.
9. The apparatus for a closed-loop receiver structure that relies on past state memory of the
loop in conjunction with the presently received signal to arrive at decisions on the presently
received data, such apparatus comprising:
A controller device that is capable of configuring and controlling the elements of the said closed-loop receiver;
A feed-forward device that computes output decisions;
A feed-back device which uses the output decisions and states of the feed-forward device to compute feedback outputs;
A first selector-devicc that is capable of selecting the inputs to a combiner-device;
The combiner device that is capable of combining the outputs of the first selector device with signals from a second-selector device to produce inputs to said feed-forward device;
A second selector device that is capable of selecting the inputs to said closed-loop
receiver.
10. The apparatus for generating coefficients for the feed-back device claimed in 16, said
apparatus comprising:
A first adaptive feedback device capable of using the outputs of the feed-forward-device of said closed-loop receiver as inputs; said adaptive feedback device being further capable of computing adaptive coefficients based on an error-signal; said adaptive feedback device capable of supplying such coefficients to the said feedback device;
A delay-element capable of delaying an instance of the input to the second selector device of said closed-loop receiver;
An error computation device capable of computing an error signal between the