Claims:1. A system (100) of direction finding for wideband antenna, said system comprising:
a processor (106) configured to:
convert a received set of signals to digital set of signals, the set of signals are received from a plurality of antennas (102);
perform parallel processing of the digital set of signals of the plurality of antennas synchronously at variable clock rates; and
extract, from the processed set of signals the pulse characteristics of emitters, wherein based on the extraction of the pulse characteristics of emitters from the processed set of signals, the processor (106) configured to estimate angle of arrival to determine location of target.

2. The system as claimed in claim 1, wherein the processor (106) is a digital signal processor that comprises one or more analogue to digital converter (ADCs) (108, 110), clock synthesizer (116), one or more reconfigurable field programmable gate array (FPGAs) (112, 114) and one or more interface (136), wherein metal housing enclosed design architecture comprises metal core, multi-layer multiple mixed signals carrying substance, printed circuit board (PCB) with components are placed in angular orientation for optimum utilization of space.

3. The system as claimed in claim 2, wherein the one or more ADCs comprise single channel high speed ADCs (108) and single channel low speed ADCs (110), wherein the one or more ADCs configured to convert the received set of signals to digital set of signals.

4. The system as claimed in claim 3, wherein the single-channel high-speed AC and DC coupled ADC of the one or more ADCs are parallel and isolated across the channel, the single-channel high-speed ADC is implemented with high SNR.

5. The system as claimed in claim 2, wherein the clock synthesizer (116) generates a plurality of coherent clock outputs with any or a combination of different clock frequency and I/O standard.

6. The system as claimed in claim 2, wherein the one or more FPGAs simultaneously capture the digital set of signals from the plurality of the antennas to perform parallel processing of the digital set of signals for wideband direction finding estimation.

7. The system as claimed in claim 1, wherein the processed set of signals comprise processing of 1 to 15 combinations of baseline interferometry data for higher accuracy in direction finding estimation.

8. The system as claimed in claim 1, wherein a receiver is configured with embedded direct digital synthesizer (DDS), wherein the digital baseband quadrature component is generated within the one or more FPGAs using DDS.

9. A processing apparatus (106) configured in the system for direction finding for wide band antenna, the processing apparatus comprising:
one or more ADCs to convert a received set of signals to digital set of signals;
one or more reconfigurable FPGAs perform parallel processing of the digital set of signals of the plurality of antennas synchronously at variable clock rates; and extract from the processed set of signals the pulse characteristics of emitters, wherein based on the extraction of the pulse characteristics of emitters from the processed set of signals, the processor configured to estimate direction finding to determine location of target.

10. A method (400) of direction finding for wideband antenna, the method comprising:
converting (402), at a processor, a received set of signals to digital set of signals, the set of signals received from a plurality of antennas;
performing (404), at the processor, parallel processing of the digital set of signals synchronously at variable clock rates; and
extracting (406), at the processor, from the processed set of signals the pulse characteristics of emitters, wherein based on the extraction of the pulse characteristics of emitters from the processed set of signals, the processor configured to estimate angle of arrival to determine location of target.

, Description:TECHNICAL FIELD
[0001] The present disclosure relates, in general, to direction finding, and more specifically, relates to a compact direction finding processing apparatus for wide band antenna system.

BACKGROUND
[0002] Direction finding is a technique in which radio frequency (RF) signal from the emitter are intercepted and processed to find the location of a target in azimuth and elevation. RF signal from the emitter is collected from more than one antenna to determine phase difference and amplitude ratio of RF signal of antennas to determine the angle of arrival (AOA) in azimuth and elevation. AOA technique using phase comparison between the antenna signals called the baseline interferometry (BLI). AOA using amplitude ratios between the RF from antennas are called the amplitude comparison AOA. Phase comparison AOA accuracy is of the order 0.5 degrees, whereas amplitude comparison has an accuracy of the order 5 degrees.
[0003] Ambiguity resolution is not required for amplitude comparison but accuracy suffers as compared to phase comparison AOA. Amplitude comparison AOA prone to inference and non-linearity introduced is subsequent RF stages moreover signal from the antenna can only be compared so long as two antenna patterns overlap. Due to the requirement of overlap of individual antenna pattern subsequent signal processing cannot improve the accuracy of AOA measurement by placing more number of antennas. In phase comparisons AOA, phase of RF signal which is proportional to distance travelled from emitter to antenna are compared to find the direction. Phase comparison is independent of varying amplitude in different RF channel. Much combination phase comparison baseline can be implemented to resolve ambiguity and improve accuracy.
[0004] In an existing system, two antennas based wide direction finding with ambiguity resolution based on time-difference-of-arrival (TDOA) is implemented, however, the existing system suffers from the limitation of latency of 30 mS, the complexity of ambiguity resolution with reduced accuracy and the existing system can work only for the pulsed signal. Another existing system may include four squinted antennas based wideband DF system that works for both pulse and continuous wave (CW) signal. This system suffers from the limitation of lack of accuracy. Further, in another known art, azimuth and elevation for a narrowband system with the combination of 4 antennas can be determined, however, the existing known art is used to find the direction of interference for cancellation for communication.
[0005] Although multiple systems exist, these systems suffer from significant drawbacks. Therefore, there is a need in the art to provide a system that can accept the RF from a plurality of antennas and process them simultaneously to resolve ambiguity and create a combination of baseline interferometry data for enhanced angular accuracy.

OBJECTS OF THE PRESENT DISCLOSURE
[0006] An object of the present disclosure relates, in general, to direction finding, and more specifically, relates to a compact direction finding processing apparatus for wide band antenna system.
[0007] Another object of the present disclosure is to provide a system with digital processor hardware implementation for improved direction finding for wide band pulse and continuous wave (CW) signal.
[0008] Another object of the present disclosure is to provide a system that process a combination of baseline interferometry data for higher accuracy in direction finding.
[0009] Another object of the present disclosure is to provide a system that enables implementation of second order difference array algorithms to decouple antenna placement restraint with respect to wavelength.
[0010] Another object of the present disclosure is to provide a system that can generate multiple coherent clock outputs with different clock frequency and input/output (I/O) standard.
[0011] Another object of the present disclosure is to provide a system that includes printed circuit board (PCB) with components placed in angular orientation for optimum utilization of space.
[0012] Another object of the present disclosure is to provide a system that includes parallel single channel ADC implementation with signal to noise ratio (SNR) better than 48 dB and with isolation better than 54 dB
[0013] Another object of the present disclosure is to provide a system that resolve ambiguity and create a combination of base line interferometry data for enhanced angular accuracy.
[0014] Another object of the present disclosure finds the direction of emitter with latency less than 350 nsec.
[0015] Yet another object of the present disclosure provides a compact system.

SUMMARY
[0016] The present disclosure relates, in general, to direction finding, and more specifically, relates to a compact direction finding processing apparatus for wide band antenna system. The present disclosure relates to the direction finding (DF) processing method for the wideband antenna system. The system accepts the signal from RF front end at 30 -120 MHz IF to estimate the direction of the emitter in azimuth and elevation. A combination of 15 baseline interferometry (BLI) signal is derived from the antennas signal for improved angular accuracy. The system includes a field gate array-based programmable (FPGA) unit, high-speed analogue to digital converter (ADC) and second-order differential array algorithm implementation which results in compact, reliable, repeatability and reduced complexity of calibration across the band (2- 18 GHz) and wide temperature range.
[0017] The present scope of the disclosure is limited to the hardware design of the DF processing system which accept input from 9 antenna RF front end with wide IF frequency ranging from 30 to 120 MHz. The metal housing enclosed design architecture consists of 9 single channel high speed ADCs, 9 single channel of low speed ADC, 2 FPGAs i.e., (FPGA1 and FPGA2) clock synthesizer, QSPIs for booting FPGAs, NOR Flash, 2 DDR Memory, 4 Lanes of GTP acting as an interface between 2 FPGAs, 55 pin circular connector connected to FPGA2 interfaced to On Board Computer carrying Ethernet and few general purpose information via RS422, 1553B connected to FPGA2 used as a RT for communicating with OBC.
[0018] In an aspect, the present disclosure provides a system of direction finding for wideband antenna, the system including processor configured to convert a received set of signals to digital set of signals, the set of signals received from a plurality of antennas, perform parallel processing of the digital set of signals synchronously at variable clock rates, extract, from the processed set of signals the pulse characteristics of emitters, wherein based on the extraction of the pulse characteristics of emitters from the processed set of signals, the processor configured to estimate angle of arrival to determine location of target.
[0019] In an embodiment, the processor is a digital signal processor that can include one or more ADCs, clock synthesizer, one or more reconfigurable FPGAs and one or more interface, wherein metal housing comprises metal core, multi-layer multiple mixed signals carrying substance, printed circuit board (PCB) with components are placed in angular orientation for optimum utilization of space.
[0020] In another embodiment, the one or more ADCs comprise single channel high speed ADCs and single channel low speed ADCs, wherein the one or more ADCs configured to convert the received set of signals to digital set of signals.
[0021] In another embodiment, the single channel high speed AC and DC coupled ADC are parallel and isolated across the channel and implemented with high SNR.
[0022] In another embodiment, the clock synthesizer generates a plurality of coherent clock outputs with any or a combination of different clock frequency and I/O standard.
[0023] In another embodiment, the one or more FPGAs simultaneously capture the digital set of signals from the plurality of the antennas to perform parallel processing of the digital set of signals for wide band direction finding estimation.
[0024] In another embodiment, the processed set of signals can include processing of 1 to 15 combinations of baseline interferometry data for higher accuracy in direction finding estimation.
[0025] In another embodiment, a receiver is configured with embedded direct digital synthesizer (DDS), wherein the digital baseband quadrature component is generated within the one or more FPGAs using DDS.
[0026] In an aspect, the present disclosure provides a method of direction finding for wideband antenna, the method including converting, at a processor, a received set of signals to digital set of signals, the set of signals are received from a plurality of antennas, performing, at the processor, parallel processing of the digital set of signals synchronously at variable clock rates; and extracting, at the processor, from the processed set of signals the pulse characteristics of emitters, wherein the based on the extraction of the pulse characteristics of emitters from the processed set of signals, the processor configured to estimate angle of arrival to determine location of target.
[0027] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The following drawings form part of the present specification and are included to further illustrate aspects of the present disclosure. The disclosure may be better understood by reference to the drawings in combination with the detailed description of the specific embodiments presented herein.
[0029] FIG. 1A illustrates an exemplary representation of a digital processor hardware of direction finding system, in accordance with an embodiment of the present disclosure.
[0030] FIG. 1B illustrates an exemplary functional component of the digital processor hardware, in accordance with an embodiment of the present disclosure.
[0031] FIG. 1C illustrates an exemplary view of the clock scheme implementation, in accordance with an embodiment of the present disclosure.
[0032] FIG. 2 illustrates an exemplary view of the 15 combinations of baseline interferometry (BLI), in accordance with an embodiment of the present disclosure.
[0033] FIG. 3 illustrates a schematic view of the bearing discrimination using 4 antennas, in accordance with an embodiment of the present disclosure.
[0034] FIG. 4 illustrates an exemplary flow chart of the method of direction-finding for wideband antenna, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0035] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0036] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0037] The present disclosure relates, in general, to direction finding, and more specifically, relates to a system and method of direction finding for wideband antenna. The present disclosure relates to the direction finding (DF) processing method for the wideband antenna system. The system accepts the signal from RF front end at 30 -120 MHz IF to estimate the direction of the emitter in azimuth and elevation. A combination of 15 baseline interferometry (BLI) signal is derived from the antennas signal for improved angular accuracy. The system includes a field gate array-based programmable unit, high-speed ADC and second-order differential array algorithm implementation which results in compact, reliable, repeatability and reduced complexity of calibration across the band (2- 18 GHz) and wide temperature range. The present disclosure can be described in enabling detail in the following examples, which may represent more than one embodiment of the present disclosure.
[0038] FIG. 1A illustrates an exemplary representation of a digital processor hardware of direction finding system, in accordance with an embodiment of the present disclosure.
[0039] Referring to FIG. 1A, direction finding system 100 (also referred to as a system 100, herein) configured for the wideband antenna. The system 100 may include one or more antennas (102-1 to 102-9 (which are collectively referred to as 102, hereinafter)), one or more front end receivers (FERs) (104-1 to 104-9 (which are collectively referred to as 104, hereinafter)) and digital signal processor 106 also interchangeably referred to as processing apparatus 106. The present disclosure relates to digital signal processor 106 that can receive the set of signals from one or more antennas 102 and process them simultaneously to resolve ambiguity and create a combination of baseline interferometry (BLI) data for enhanced angular accuracy. Each of the one or more antennas 102 coupled to a receiver and configured to receive the set of signals from emitters, the set of signals pertaining to radio frequency (RF) signals. The present disclosure can find the direction of the emitter with a latency lesser than 350 nsec.
[0040] In an exemplary embodiment, the one or more antennas 102 as presented in the example may be 9 antennas. As can be appreciated, the present disclosure may not be limited to this configuration but may be extended to other configurations. In another exemplary embodiment, the receiver can be a digital receiver with an embedded direct digital synthesizer (DDS). The receiver can help in the generation of digital baseband quadrature Q from the in-phase I signal.
[0041] FIG. 1B illustrates an exemplary functional component of the digital processor hardware, in accordance with an embodiment of the present disclosure. Referring to FIG. 1B, digital processor hardware 106 of the system 100 can accept input from 9 antenna RF front end with wide IF frequency ranging from 30 to 120 MHz. The metal housing enclosed design architecture can include metal core, multi-layer multiple mixed signals carrying substance, where the printed circuit board (PCB) with components are placed in angular orientation for optimum utilization of space. The digital signal processor 106 can include one or more ADCs (108, 110), one or more field-programmable gate arrays (FPGAs) (112, 114), where one or more FPGAs can include a first FPGA 112 and a second FPGA 114. The digital processor hardware 106 can further include clock synthesizer 116, clock oscillators 134, quad serial peripheral interface (QSPIs) 118 for booting FPGAs, two NOR flash (120, 122), two double data rate (DDR) memory (124, 126), 4 lanes of GTP/GTX 136, 55 pin circular connector 128 and a supply module 138 to supply power to the PCB.
[0042] The digital signal processor 106 configured to receive the set of signals from the one or more antennas 102. The digital signal processor 106 can convert the received set of signals into a digital set of signals. The digital signal processor 106 can perform parallel processing of the digital set of signals of one or more antennas 102 synchronously at variable clock rates. The digital signal processor 106 can extract from the processed set of signals the pulse characteristics of the emitters, where based on the extraction of the pulse characteristics of the emitters from the processed set of signals of each of the one or more antennas 102, the digital signal processor 106 configured to estimate angle of arrival to determine the location of the target. The processed set of signals include a combination of baseline interferometry data.
[0043] In another embodiment, the GTP 136 can act as an interface between the first FPGA 112 and the second FPGA 114. System 100 can include the interface such as universal asynchronous receiver-transmitter (UART), Ethernet and MIL BUS 1553. The 55 pin circular connector 128 can be connected to the second FPGA 114 interfaced to On Board Computer (OBC) carrying Ethernet and a few general-purpose information via RS422 130, 1553B transceiver 132 and connected to the FPGA 114 used as a remote terminal (RT) for communicating with OBC.
[0044] In an exemplary embodiment, the one or more ADCs (108, 110) may include 9 parallel single-channel high-speed ADC 108 also interchangeably referred to as single-channel high-speed ADC 108 and 9 parallel single-channel low-speed ADC 110 also interchangeably referred to as single-channel low-speed ADC 110. One or more ADCs configured to convert the received set of signals into the digital set of signals.
[0045] In another embodiment, the high-speed AC coupled ADC at 250 MHz, can be compact. In an exemplary embodiment, the 9 parallel single-channel ADC implementation with SNR better than 48 dB and 9 parallel single-channel ADC implementation with isolation better than 54 dB. In another embodiment, the high-speed DC coupled ADC at 100 MHz can be compact. In an exemplary embodiment, the 9 parallel single-channel ADC implementation with SNR better than 48 dB and 9 parallel single-channel ADC implementation with isolation better than 54 dB.
[0046] The first FPGA 112 coupled to the one or more ADCs (108, 110), the GTP 136 can act as an interface between the first FPGA 112 and the second FPGA 114. The one or more FPGAs (112, 114) simultaneously capture the digital set of signals of one or more antennas 102 to perform parallel processing of the digital set of signals for wideband DF estimation. For example, the one or more FPGAs (112, 114) simultaneously capture the digitized data from 3 to 9 antennas based RF front end. Parallel processing can be performed up to 9 antenna data for wideband DF estimation.
[0047] Thus, the present disclosure with one or more fast ADCs (108, 110) and fast parallel processing blocks can cater for 9 wideband antennas output for DF estimation with less latency. The reconfigurable FPGAs (112, 114) based hardware for 3 to 9 antenna system for DF measurement increases the overall system reliability, repeatability and reduced complexity of calibration across the band (2- 18 GHz) and wide temperature range.
[0048] FIG. 1C illustrates an exemplary view of the clock scheme implementation, in accordance with an embodiment of the present disclosure.
[0049] Referring to FIG. 1C, the programmable clock synthesizer 116 coupled to the one or more ADCs (108, 110) configured to generate multiple coherent clock outputs with different clock frequency and I/O standard. The single low noise and low jitter flexible clock synthesizer 116 configured for clock generation to achieve compactness. For digital processing of the data, the input lines for in-phase signal and extended detector log video amplifier (EDLVA) signal coming from one or more FERs 104 need to be sampled at different clock rates. Different ADCs (108, 110) may require different format of clock inputs. The extended detector log video amplifier is one type of RF receiver.
[0050] Instead of using multiple clock oscillators, a single chip solution is derived which can be configured through SPI to generate multiple clock outputs of different frequency and output standard as shown in FIG.1C. This leads to hardware reduction with highly phased coherent clock outputs, which can improve the accuracy of the final phase and amplitude output. Also, the quadrature component is generated within the FPGA (112, 114) using the DDS block, which reduces the space on the PCB and reduces the cost of the system 100.
[0051] The digital receiver with the embedded DDS can perform the generation of digital baseband quadrature Q from in-phase I signal. System 100 can accept variable IF providing flexibility with RF design interface and circumventing need for 90° hybrid in RF chain. The receiver can reduce RF hardware complexity, enable precise phase matching across the channel and provide an enhanced signal to noise ratio (SNR) with decimation and reliability due to parallel processing with the synchronous clock.
[0052] The embodiments of the present disclosure described above provide several advantages. The one or more of the embodiments provide digital processor hardware 106 implementation for improved direction finding for wideband pulse and CW signal. System 100 processes a combination of baseline interferometry data for higher accuracy in direction finding, enables the implementation of second-order difference array algorithms to decouple antenna placement restraint with respect to wavelength. System 100 can resolve ambiguity and create 15 combinations of baseline interferometry data for enhanced angular accuracy. The present disclosure finds the direction of the emitter with the latency lesser than 350 nsec.
[0053] FIG. 2 illustrates an exemplary view of the 15 combinations of baseline interferometry (BLI), in accordance with an embodiment of the present disclosure.
[0054] Referring to FIG. 2, second-order difference array algorithms 200 can be implemented to decouple antenna placement restraint with respect to phase ambiguity resolution. In the mission critical airborne systems, the precise angle of arrival (AOA) of a signal is an important parameter to be estimated by the receiver as it can be exploited in a number of strategic and useful ways. However, due to the trade-off that generally exists between the accuracy and computation time of an algorithm, the choice of the AOA estimation algorithm must strike the right balance between accuracy and computational speed. The enhancement of the AOA estimation performance by combining the second-order differential array (SODA) interferometer with conventional first order ambiguity resolution methods to derive the optimal AOA estimates in a computationally efficient manner.
[0055] Consider a collinear array with three antennas as depicted in FIG.2. The first order phase delays are given by d_21 and d_32 base lines i.e., Ψ_21 and Ψ_32 respectively, where it is assumed that d_32