[0001] The present disclosure relates generally to field of digital electronics and communication. More particularly, the present disclosure provides a composite partial positive feedback based system for an amplifier.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Analog signal conditioning circuits such as voltage amplifiers, transconductance amplifiers, transimpedance amplifiers, current amplifier and filters etc. are extensively used in various biomedical applications such as bio-signal recording, cardiac electrical impedance tomography on-chip bio-impedance spectroscopy and scanning ion-conductance microscopy. These circuits suffer from high values of input referred noise power spectral density which contaminates the important information residing inside the signal of interest for these applications. The reason for high value of noise is attributed to the tradeoff between noise and stability in these circuits. The input referred noise power spectral density cannot be reduced beyond a certain extend owing to the necessary stability condition of the circuit to be fulfilled.
[0004] Existing solutions include use of single metal oxide silicon field effect transistor (MOSFET) or MOS transistor in partial positive feedback circuit. They only used partial positive feedback circuit but no composite MOS transistor in the feedback circuit. Another solutions include composite MOS transistors but did not mention about the use of composite MOS transistor in cross-coupled partial positive feedback circuit.
[0005] There is a need to overcome above mentioned problems of prior art by bringing a solution that uses composite MOS transistor and partial positive feedback collectively for optimizing noise-stability tradeoff and enhancing impedance for better DC offset and common mode rejection. Also, the solution provides better bio medical applications by using composite MOS transistor. The solution provides has a better optimization for tradeoff between noise and stability and facilitates achieving low values of input referred noise power spectral density.

OBJECTS OF THE PRESENT DISCLOSURE
[0006] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.
[0007] It is an object of the present disclosure to provide a device for Bio-signal recording and On-Chip Bio-Impedance Spectroscopy.
[0008] It is an object of the present disclosure to provide a device that helps in Cardiac Electrical Impedance tomography.
[0009] It is an object of the present disclosure to provide a device that facilitates Scanning Ion-Conductance Microscopy.
[0010] It is an object of the present disclosure to provide a device with Composite Partial Positive Feed-back (CPPF) circuit technique along with flexibility to the control transconductance and transconductance ratio values.
[0011] It is an object of the present disclosure to provide a device that has a better optimization for tradeoff between noise and stability and facilitates achieving low values of input referred noise power spectral density.
[0012] It is an object of the present disclosure to provide a device that has composite metal oxide silicon field effect transistor (MOSFET) or MOS transistor with an upper MOS transistor for saturation and lower MOS transistor for triode region, where the composite MOS transistor enables optimizing noise stability tradeoff.
[0013] It is an object of the present disclosure to provide a device that has composite MOS transistor and partial positive feedback collectively for optimizing noise-stability tradeoff and enhancing impedance for better DC offset and common mode rejection.

SUMMARY
[0014] The present disclosure relates generally to field of digital electronics and communication. More particularly, the present disclosure provides a composite partial positive feedback based system for an amplifier.
[0015] An aspect of the present disclosure pertains to a composite partial positive feedback based system for an amplifier, the system may include a first branch and a second branch. The first branch may include a first composite transistor including a set of transistor devices coupled to each other in series and a second composite transistor including a set of transistor devices coupled to each other in series, where the second composite transistor may be coupled to the first composite transistor in parallel, and where a drain voltage of each of a first transistor device of the first composite transistor and a first transistor device of the second composite transistor may be coupled to a first node. The second branch may include a third composite transistor including a set of transistor devices coupled to each other in series and a fourth composite transistor including a set of transistor devices coupled to each other in series, where the fourth composite transistor may be coupled to the third composite transistor in parallel, and where a drain voltage of each of a first transistor device of the third composite transistor and a first transistor device of the fourth composite transistor may be coupled to a second node. The drain voltage of the first transistor device of the second composite transistor may be fed to a gate of the first transistor device of the third composite transistor, and the drain voltage of the first transistor device of the third composite transistor may be fed to a gate of the first transistor device of the second composite transistor to effect a positive feedback configuration in the second composite transistor and the third composite transistor thereby boosting corresponding values of transconductance.
[0016] In an aspect, the effective transconductance of each of the first, second, third and fourth composite transistors may decrease by a factor defined as a function of respective scaling coefficients.
[0017] In an aspect, the effective transconductance and transconductance ratio of each of the first, second, third and fourth composite transistors may facilitates optimizing tradeoff between noise and stability for achieving low values of noise.
[0018] In an aspect, the system may include a first branch and a second branch. The first branch may include a first composite transistor including a set of transistor devices coupled to each other in series, a second composite transistor including a set of transistor devices coupled to each other in series, where the second composite transistor may be coupled to the first composite transistor in parallel, and where a drain voltage of each of a first transistor device of the first composite transistor and a first transistor device of the second composite transistor may be coupled to a first node, and a fifth composite transistor including a set of transistor devices coupled to each other in series. The second branch may include a third composite transistor including a set of transistor devices coupled to each other in series, a fourth composite transistor including a set of transistor devices coupled to each other in series, where the fourth composite transistor may be coupled to the third composite transistor in parallel, and a sixth composite transistor including a set of transistor devices coupled to each other in series, and where the fifth composite transistor and the sixth composite transistor may be configured to supply predefined minor current in the first branch and the second branch of the system , and where the drain voltage of each of a first transistor device of the first composite transistor of the first branch coupled at the first node and a first transistor device of the third composite transistor of the second branch coupled at a second node may be equal to gate voltage of each of the first transistor device of the first composite transistor and the first transistor device of the third composite transistor of the first branch and the second branch and the first transistor device of the fifth composite transistor of the first branch and the first transistor device of the sixth composite transistor of the second branch.
[0019] Another aspect of the present disclosure pertains to a composite partial positive feedback based operational amplifier (OP-AMP), the OP-AMP including a first branch and a second branch. The first branch may include a first composite transistor including a set of transistor devices coupled to each other in series and a second composite transistor including a set of transistor devices coupled to each other in series, where the second composite transistor may be coupled to the first composite transistor in parallel, and where a drain voltage of each of a first transistor device of the first composite transistor and a first transistor device of the second composite transistor may be coupled to a first node. The second branch may include a third composite transistor including a set of transistor devices coupled to each other in series and a fourth composite transistor including a set of transistor devices coupled to each other in series, where the fourth composite transistor may be coupled to the third composite transistor in parallel, and where a drain voltage of each of a first transistor device of the third composite transistor and a first transistor device of the fourth composite transistor may be coupled to a second node. The drain voltage of the first transistor device of the second composite transistor may be fed to a gate of the first transistor device of the third composite transistor, and the drain voltage of the first transistor device of the third composite transistor may be fed to a gate of the first transistor device of the second composite transistor to effect a positive feedback configuration in the second composite transistor and the third composite transistor thereby boosting corresponding values of transconductance.
[0020] In an aspect, the OP-AMP may include a first branch and a second branch. The first branch may include a first composite transistor including a set of transistor devices coupled to each other in series, a second composite transistor including a set of transistor devices coupled to each other in series, where the second composite transistor may be coupled to the first composite transistor in parallel, and where a drain voltage of each of a first transistor device of the first composite transistor and a first transistor device of the second composite transistor may be coupled to a first node, and a fifth composite transistor including a set of transistor devices coupled to each other in series. The second branch may include a third composite transistor including a set of transistor devices coupled to each other in series, a fourth composite transistor including a set of transistor devices coupled to each other in series, where the fourth composite transistor may be coupled to the third composite transistor in parallel, and a sixth composite transistor including a set of transistor devices coupled to each other in series, and where the fifth composite transistor and the sixth composite transistor may be configured to supply predefined minor current in the first branch and the second branch of the system , and where the drain voltage of each of a first transistor device of the first composite transistor of the first branch coupled at the first node and a first transistor device of the third composite transistor of the second branch coupled at a second node may be equal to gate voltage of each of the first transistor device of the first composite transistor and the first transistor device of the third composite transistor of the first branch and the second branch and the first transistor device of the fifth composite transistor of the first branch and the first transistor device of the sixth composite transistor of the second branch.
[0021] In an aspect, the effective transconductance of each of the first, second, third and fourth composite transistors may decrease by a factor defined as a function of respective scaling coefficients.

BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0023] The diagrams are for illustration only, which thus is not a limitation of the present disclosure, and wherein:
[0024] FIG. 1 illustrates an exemplary view of proposed composite partial positive feedback based system for an amplifier, in accordance with an embodiment of the present disclosure.
[0025] FIG. 2 illustrates exemplary view of the proposed composite partial positive feedback based system for an amplifier with an additional composite transistor, in accordance with an embodiment of the present disclosure.
[0026] FIG. 3 illustrates an exemplary view of the proposed composite partial positive feedback based system for an amplifier with the additional composite transistor for biomedical application, in accordance with an embodiment of the present disclosure.

DETAIL DESCRIPTION
[0027] In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
[0028] If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0029] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0030] The present disclosure relates generally to field of digital electronics and communication. More particularly, the present disclosure provides a composite partial positive feedback based system for an amplifier.
[0031] FIG. 1 illustrates an exemplary view of proposed composite partial positive feedback based system for an amplifier, in accordance with an embodiment of the present disclosure.
[0032] As illustrated in FIG. 1, the proposed system 100 (also referred to as system 100, herein) can include a first branch 102 and a second branch 104. The system 100 can be composite partial positive feedback (CPPF) based, for an amplifier. In an embodiment, the first branch 102 can include a first composite transistor 102-1, where the first composite transistor 102-1 can include a set of transistor devices 102-1-1, 102-1-2 coupled to each other in series. The first branch 102 can include a second composite transistor 102-2, where the second composite transistor 102-2 can include a set of transistor devices 102-2-1, 102-2-2 coupled to each other in series, where the second composite transistor 102-2 is coupled to the first composite transistor 102-1 in parallel, where a drain voltage of each of a first transistor device 102-1-1 of the first composite transistor 102-1 and a first transistor device 102-2-1 of the second composite transistor 102-2 is coupled to a first node.
[0033] In an embodiment, the second branch 104 can include a third composite transistor 104-1, where the third composite transistor can include a set of transistor devices 104-1-1, 104-1-2 coupled to each other in series. The second branch 104 can include a fourth composite transistor 104-2, where the fourth composite transistor 104-2 can include a set of transistor devices 104-2-1, 104-2-2 coupled to each other in series, where the fourth composite transistor 104-2 can be coupled to the third composite transistor 104-1 in parallel, and where a drain voltage of each of a first transistor device 104-1-1 of the third composite transistor 104-1 and a first transistor device 104-2-1 of the fourth composite transistor 104-2 is coupled to a second node.
[0034] In an embodiment, the drain voltage of the first transistor device 102-2-1 of the second composite transistor 102-2 can be fed to a gate of the first transistor device 104-1-1 of the third composite transistor 104-1, and the drain voltage of the first transistor device 104-1-1 of the third composite transistor 104-1 can be fed to a gate of the first transistor device 102-2-1 of the second composite transistor 102-2 to effect a positive feedback configuration in the second composite transistor 102-2 and the third composite transistor 104-1 thereby boosting corresponding values of transconductance.
[0035] In an embodiment, the effective transconductance of each of the first composite, second, third and fourth composite transistor can decrease by a factor defined as a function of respective scaling coefficients. In another embodiment, the effective transconductance and transconductance ratio of each of the first composite transistor 102-1, the second composite transistor 102-2, the third composite transistor 104-1 and the fourth composite transistor 104-2 can facilitate optimizing tradeoff between noise and stability for achieving low values of noise.
[0036] In an embodiment, the system 100 can include a first branch 102 and a second branch 104. The first branch can include a first composite transistor 102-1 including a set of transistor devices 102-1-1, 102-1-2 coupled to each other in series, a second composite transistor 102-2 including a set of transistor devices 102-2-1, 102-2-2 coupled to each other in series, where the second composite transistor 102-2 can be coupled to the first composite transistor 102-1 in parallel, and where a drain voltage of each of a first transistor device 102-1-1 of the first composite transistor 102-1 and a first transistor device 102-2-1 of the second composite transistor 102-2 can be coupled to a first node, and a fifth composite transistor 102-3 including a set of transistor devices 102-3-1, 102-3-2 coupled to each other in series.
[0037] In an embodiment, the second branch 104 can include a third composite transistor 104-1 including a set of transistor devices 104-1-1, 104-1-2 coupled to each other in series, a fourth composite transistor 104-2 including a set of transistor devices 104-2-1, 104-2-2 coupled to each other in series, where the fourth composite transistor 104-2 can be coupled to the third composite transistor 104-1 in parallel, and a sixth composite transistor 104-3 including a set of transistor devices 104-3-1, 104-3-2 coupled to each other in series, and where the fifth composite transistor 102-3 and the sixth composite transistor 104-3 can be configured to supply predefined minor current in the first branch 102 and the second branch 104 of the system 100 , and where the drain voltage of each of a first transistor device 102-1-1 of the first composite transistor 104-1 of the first branch 102 coupled at the first node and a first transistor device 104-1-1 of the third composite transistor 104-1 of the second branch 104 coupled at a second node can be equal to gate voltage of each of the first transistor device 104-1-1 of the first composite transistor 104-1 and the first transistor device 104-1-1 of the third composite transistor 104-1 of the first branch 102 and the second branch 104 and the first transistor device 102-3-1 of the fifth composite transistor 102-3 of the first branch 102 and the first transistor device 104-3-1 of the sixth composite transistor 104-3 of the second branch 104.
[0038] In an illustrative embodiment, the system 100 can be a CPPF based operational amplifier (OP-AMP). The OP-AMP can include a first branch 102 and a second branch 104. , the first branch 102 can include a first composite transistor 102-1, where the first composite transistor 102-1 can include a set of transistor devices 102-1-1, 102-1-2 coupled to each other in series. The first branch 102 can include a second composite transistor 102-2, where the second composite transistor 102-2 can include a set of transistor devices 102-2-1, 102-2-2 coupled to each other in series, where the second composite transistor 102-2 is coupled to the first composite transistor 102-1 in parallel, where a drain voltage of each of a first transistor device 102-1-1 of the first composite transistor 102-1 and a first transistor device 102-2-1 of the second composite transistor 102-2 is coupled to a first node.
[0039] In an embodiment, the second branch 104 can include a third composite transistor 104-1, where the third composite transistor can include a set of transistor devices 104-1-1, 104-1-2 coupled to each other in series. The second branch 104 can include a fourth composite transistor 104-2, where the fourth composite transistor 104-2 can include a set of transistor devices 104-2-1, 104-2-2 coupled to each other in series, where the fourth composite transistor 104-2 can be coupled to the third composite transistor 104-1 in parallel, and where a drain voltage of each of a first transistor device 104-1-1 of the third composite transistor 104-1 and a first transistor device 104-2-1 of the fourth composite transistor 104-2 is coupled to a second node.
[0040] In an embodiment, the drain voltage of the first transistor device 102-2-1 of the second composite transistor 102-2 can be fed to a gate of the first transistor device 104-1-1 of the third composite transistor 104-1, and the drain voltage of the first transistor device 104-1-1 of the third composite transistor 104-1 can be fed to a gate of the first transistor device 102-2-1 of the second composite transistor 102-2 to effect a positive feedback configuration in the second composite transistor 102-2 and the third composite transistor 104-1 thereby boosting corresponding values of transconductance.
[0041] In an illustrative embodiment, the OP-AMP can include a first branch 102 and a second branch 104. The first branch can include a first composite transistor 102-1 including a set of transistor devices 102-1-1, 102-1-2 coupled to each other in series, a second composite transistor 102-2 including a set of transistor devices 102-2-1, 102-2-2 coupled to each other in series, where the second composite transistor 102-2 can be coupled to the first composite transistor 102-1 in parallel, and where a drain voltage of each of a first transistor device 102-1-1 of the first composite transistor 102-1 and a first transistor device 102-2-1 of the second composite transistor 102-2 can be coupled to a first node, and a fifth composite transistor 102-3 including a set of transistor devices 102-3-1, 102-3-2 coupled to each other in series.
[0042] In an embodiment, the second branch 104 can include a third composite transistor 104-1 including a set of transistor devices 104-1-1, 104-1-2 coupled to each other in series, a fourth composite transistor 104-2 including a set of transistor devices 104-2-1, 104-2-2 coupled to each other in series, where the fourth composite transistor 104-2 can be coupled to the third composite transistor 104-1 in parallel, and a sixth composite transistor 104-3 including a set of transistor devices 104-3-1, 104-3-2 coupled to each other in series, and where the fifth composite transistor 102-3 and the sixth composite transistor 104-3 can be configured to supply predefined minor current in the first branch 102 and the second branch 104 of the system 100 , and where the drain voltage of each of a first transistor device 102-1-1 of the first composite transistor 104-1 of the first branch 102 coupled at the first node and a first transistor device 104-1-1 of the third composite transistor 104-1 of the second branch 104 coupled at a second node can be equal to gate voltage of each of the first transistor device 104-1-1 of the first composite transistor 104-1 and the first transistor device 104-1-1 of the third composite transistor 104-1 of the first branch 102 and the second branch 104 and the first transistor device 102-3-1 of the fifth composite transistor 102-3 of the first branch 102 and the first transistor device 104-3-1 of the sixth composite transistor 104-3 of the second branch 104.
[0043] In an illustrative embodiment, the system 100 based on CPPF for an amplifier, where the first composite transistor 102-1, with the set of transistor devices 102-1-1, 102-1-2 can be identical with the fourth composite transistor 104-2 with the set of transistor devices 104-2-1, 104-2-2 and the second composite transistor 102-2 with the set of transistor devices 102-2-1, 102-2-2 can be identical with the third composite transistor 104-1 with the set of transistor devices 104-1-1, 104-1-2 respectively. In another illustrative embodiment, the drain voltage of the first transistor device 102-2-1 of the second composite transistor 102-2 is fed to a gate of the first transistor device 104-1-1 of the third composite transistor 104-1, and the drain voltage of the first transistor device 104-1-1 of the third composite transistor 104-1 is fed to a gate of the first transistor device 102-2-1 of the second composite transistor 102-2 to effect a positive feedback configuration in the second composite transistor 102-2 and the third composite transistor 104-1 thereby boosting corresponding values of transconductance. In yet another illustrative embodiment, partial positive feedback configuration can facilitate modifying current flowing through the second composite transistor 102-2 and the third composite transistor 104-1 and the transconductance of the second composite transistor 102-2 and the third composite transistor 104-1 can increase. The increased transductance can enable improving stability of the system 100 along with achieving large value of open loop gain and gain bandwidth product respectively.
[0044] In an illustrative embodiment, the system 100 can facilitate controlling the transconductance and transconductance ratio values of the first composite transistor 102-1, the second composite transistor 102-2, the third composite transistor 104-1 and the fourth composite transistor 104-2 and optimizing tradeoff between noise and stability for achieving low values of noise for the system 100. In another illustrative embodiment, the CPPF based system 100 can enable improving common mode response and offset rejection owing to high output impedance and low transconductance ratio values for the first composite transistor 102-1, the second composite transistor 102-2, the third composite transistor 104-1 and the fourth composite transistor 104-2.
[0045] FIG. 2 illustrates exemplary view of the proposed composite partial positive feedback based system for an amplifier with an additional composite transistor, in accordance with an embodiment of the present disclosure.
[0046] As illustrated in FIG. 2, the system 100 the system 100 can include a first branch 102 and a second branch 104. The first branch can include a first composite transistor 102-1 including a set of transistor devices 102-1-1, 102-1-2 coupled to each other in series, a second composite transistor 102-2 including a set of transistor devices 102-2-1, 102-2-2 coupled to each other in series, where the second composite transistor 102-2 can be coupled to the first composite transistor 102-1 in parallel, and where a drain voltage of each of a first transistor device 102-1-1 of the first composite transistor 102-1 and a first transistor device 102-2-1 of the second composite transistor 102-2 can be coupled to a first node, and a fifth composite transistor 102-3 including a set of transistor devices 102-3-1, 102-3-2 coupled to each other in series.
[0047] In an embodiment, the second branch 104 can include a third composite transistor 104-1 including a set of transistor devices 104-1-1, 104-1-2 coupled to each other in series, a fourth composite transistor 104-2 including a set of transistor devices 104-2-1, 104-2-2 coupled to each other in series, where the fourth composite transistor 104-2 can be coupled to the third composite transistor 104-1 in parallel, and a sixth composite transistor 104-3 including a set of transistor devices 104-3-1, 104-3-2 coupled to each other in series, and where the fifth composite transistor 102-3 and the sixth composite transistor 104-3 can be configured to supply predefined minor current in the first branch 102 and the second branch 104 of the system 100 , and where the drain voltage of each of a first transistor device 102-1-1 of the first composite transistor 104-1 of the first branch 102 coupled at the first node and a first transistor device 104-1-1 of the third composite transistor 104-1 of the second branch 104 coupled at a second node can be equal to gate voltage of each of the first transistor device 104-1-1 of the first composite transistor 104-1 and the first transistor device 104-1-1 of the third composite transistor 104-1 of the first branch 102 and the second branch 104 and the first transistor device 102-3-1 of the fifth composite transistor 102-3 of the first branch 102 and the first transistor device 104-3-1 of the sixth composite transistor 104-3 of the second branch 104.
[0048] In an illustrative embodiment, the transconductance ratio values of the first composite transistor 102-1, the fourth composite transistor 104-2, the fifth composite transistor 102-3 and the sixth composite transistor 104-3 used in the system can depends upon width scaling coefficients like M3 and M1 respectively and facilitates reducing power overheads while establishing a tradeoff with gain bandwidth of the system 100.
[0049] FIG. 3 illustrates an exemplary view of the proposed composite partial positive feedback based system for an amplifier with the additional composite transistor for biomedical application, in accordance with an embodiment of the present disclosure.
[0050] As illustrated in FIG. 3, the system 100 can include a first branch 102 and a second branch 104. The first branch can include a first composite transistor 102-1 including a set of transistor devices 102-1-1, 102-1-2 coupled to each other in series, a second composite transistor 102-2 including a set of transistor devices 102-2-1, 102-2-2 coupled to each other in series, where the second composite transistor 102-2 can be coupled to the first composite transistor 102-1 in parallel, and where a drain voltage of each of a first transistor device 102-1-1 of the first composite transistor 102-1 and a first transistor device 102-2-1 of the second composite transistor 102-2 can be coupled to a first node, and a fifth composite transistor 102-3 including a set of transistor devices 102-3-1, 102-3-2 coupled to each other in series.
[0051] In an embodiment, the second branch 104 can include a third composite transistor 104-1 including a set of transistor devices 104-1-1, 104-1-2 coupled to each other in series, a fourth composite transistor 104-2 including a set of transistor devices 104-2-1, 104-2-2 coupled to each other in series, where the fourth composite transistor 104-2 can be coupled to the third composite transistor 104-1 in parallel, and a sixth composite transistor 104-3 including a set of transistor devices 104-3-1, 104-3-2 coupled to each other in series. In an illustrative embodiment, the system 100 can be operational transconductance amplifier based on CPPF and can be used for biomedical applications.
[0052] While embodiments of the present invention have been illustrated and described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the invention, as described in the claim.
[0053] In the foregoing description, numerous details are set forth. It will be apparent, however, to one of ordinary skill in the art having the benefit of this disclosure, that the present invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention.
[0054] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, ` components, or steps that are not expressly referenced.
[0055] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE PRESENT DISCLOSURE
[0056] The present disclosure provides a device for Bio-signal recording and On-Chip Bio-Impedance Spectroscopy.
[0057] The present disclosure provides a device that helps in Cardiac Electrical Impedance tomography.
[0058] The present disclosure provides a device that facilitates Scanning Ion-Conductance Microscopy.
[0059] The present disclosure provides a device with Composite Partial Positive Feed-back (CPPF) circuit technique along with flexibility to the control transconductance and transconductance ratio values.
[0060] The present disclosure provides a device that has a better optimization for tradeoff between noise and stability and facilitates achieving low values of input referred noise power spectral density.
[0061] The present disclosure provides a device that has composite metal oxide silicon field effect transistor (MOSFET) or MOS transistor with an upper MOS transistor for saturation and lower MOS transistor for triode region, where the composite MOS transistor enables optimizing noise stability tradeoff.
[0062] The present disclosure provides a device that has composite MOS transistor and partial positive feedback collectively for optimizing noise-stability tradeoff and enhancing impedance for better DC offset and common mode rejection.

Claims:1. A composite partial positive feedback based system (100) for an amplifier, said system (100) comprising:
a first branch (102) comprising:
a first composite transistor (102-1) comprising a set of transistor devices (102-1-1, 102-1-2)coupled to each other in series;
a second composite transistor (102-2) comprising a set of transistor devices (102-2-1, 102-2-2) coupled to each other in series, wherein the second composite transistor (102-2) is coupled to the first composite transistor (102-1) in parallel, and
wherein a drain voltage of each of a first transistor device (102-1-1)of the first composite transistor (102-1)and a first transistor device (102-2-1)of the second composite transistor (102-2) is coupled to a first node;
a second branch (104) comprising:
a third composite transistor (104-1) comprising a set of transistor devices (104-1-1, 104-1-2)coupled to each other in series;
a fourth composite transistor (104-2) comprising a set of transistor devices (104-2-1, 104-2-2) coupled to each other in series, wherein the fourth composite transistor (104-2) is coupled to the third composite transistor (104-1)in parallel, and
wherein a drain voltage of each of a first transistor device (104-1-1) of the third composite transistor (104-1) and a first transistor device (104-2-1) of the fourth composite transistor (104-2) is coupled to a second node,
wherein the drain voltage of the first transistor device (102-2-1) of the second composite transistor (102-2) is fed to a gate of the first transistor device (104-1-1) of the third composite transistor (104-1), and the drain voltage of the first transistor device (104-1-1) of the third composite transistor (104-1) is fed to a gate of the first transistor device (102-2-1) of the second composite transistor (102-2) to effect a positive feedback configuration in the second composite transistor (102-2) and the third composite transistor (104-1) thereby boosting corresponding values of transconductance.
2. The system (100) as claimed in claim 1, wherein the effective transconductance of each of the first composite transistor (102-1), second composite transistor (102-2), the third composite transistor (104-1) and the fourth composite transistor (104-2) decrease by a factor defined as a function of respective scaling coefficients.
3. The system (100) as claimed in claim 1, wherein the effective transconductance and transconductance ratio of each of the first composite transistor (102-1), the second composite transistor (102-2) , the third composite transistor (104-1) and the fourth composite transistor (104-2) facilitates optimizing tradeoff between noise and stability for achieving low values of noise.
4. The system (100) as claimed in claim 1, wherein the system (100) including :
a first branch (102) including :
a first composite transistor (102-1) including a set of transistor devices (102-1-1, 102-1-2) coupled to each other in series;
a second composite transistor (102-2) including a set of transistor devices (102-2-1, 102-2-2)coupled to each other in series, wherein the second composite transistor (102-2) is coupled to the first composite transistor (102-1) in parallel, and
wherein a drain voltage of each of a first transistor device (102-1-1) of the first composite transistor (102-1) and a first transistor device (102-2-1) of the second composite transistor (102-2) is coupled to a first node,
and a fifth composite transistor (102-3)including a set of transistor devices (102-3-1, 102-3-2) coupled to each other in series
a second branch (104) including:
a third composite transistor (104-1) including a set of transistor devices (104-1-1, 104-1-2) coupled to each other in series;
a fourth composite transistor (104-2) including a set of transistor devices (104-2-1, 104-2-2) coupled to each other in series, wherein the fourth composite transistor (104-2) is coupled to the third composite transistor (104-1) in parallel, and
a sixth composite transistor (104-3) including a set of transistor devices (104-3-1, 104-3-2) coupled to each other in series,
and
wherein the fifth composite transistor (102-3) and the sixth composite transistor (104-3) is configured to supply predefined minor current in the first branch (102) and the second branch (104) of the system (100) , and wherein the drain voltage of each of a first transistor device (102-1-1) of the first composite transistor (102-1) of the first branch (102) coupled at the first node and a first transistor device (104-1-1) of the third composite transistor (104-1) of the second branch (104) coupled at a second node is equal to gate voltage of each of the first transistor device (102-1-1) of the first composite transistor (102-1) and the first transistor device (104-1-1) of the third composite transistor (104-1) of the first branch (102) and the second branch (104) and the first transistor device (104-3-1) of the fifth composite transistor (102-3) of the first branch (102) and the first transistor device (104-3-1) of the sixth composite transistor (104-3) of the second branch (104).
5. A composite partial positive feedback based operational amplifier (OP-AMP), said OP-AMP including:
a first branch (100) including:
a first composite transistor (102-1) including a set of transistor devices (102-1-1, 102-1-2) coupled to each other in series;
a second composite transistor (102-2) including a set of transistor devices (102-2-1, 102-2-2) coupled to each other in series, wherein the second composite transistor (102-2) is coupled to the first composite transistor (102-1) in parallel, and
wherein a drain voltage of each of a first transistor device (102-1-1) of the first composite transistor (102-1) and a first transistor device (102-2-1) of the second composite transistor (102-2) is coupled to a first node;
a second branch (104) including:
a third composite transistor (104-1) including a set of transistor devices (104-1-1, 104-1-2) coupled to each other in series;
a fourth composite transistor (104-2) including a set of transistor devices (104-2-1, 104-2-2) coupled to each other in series, wherein the fourth composite transistor (104-2) is coupled to the third composite transistor (104-1) in parallel, and
wherein a drain voltage of each of a first transistor device (104-1-1) of the third composite transistor (104-1) and a first transistor device (104-2-1) of the fourth composite transistor (104-2) is coupled to a second node,
wherein the drain voltage of the first transistor device (102-2-1) of the second composite transistor (102-2) is fed to a gate of the first transistor device (104-1-1) of the third composite transistor (104-1), and the drain voltage of the first transistor device (104-1-1) of the third composite transistor (104-1) is fed to a gate of the first transistor device (102-2-1) of the second composite transistor (102-2) to effect a positive feedback configuration in the second composite transistor (102-2) and the third composite transistor (104-1) thereby boosting corresponding values of transconductance.
6. The OP-AMP as claimed in claim 5, wherein the OP-AMP including :
a first branch (102) including :
a first composite transistor (102-1) including a set of transistor devices (102-1-1, 102-1-2) coupled to each other in series;
a second composite transistor (102-2) including a set of transistor devices (102-2-1, 102-2-2) coupled to each other in series, wherein the second composite transistor (102-2) is coupled to the first composite transistor (102-1) in parallel, and
wherein a drain voltage of each of a first transistor device (102-1-1) of the first composite transistor (102-1) and a first transistor device (102-2-1) of the second composite transistor (102-2) is coupled to a first node,
and a fifth composite transistor (102-3) including a set of transistor devices (102-3-1, 102-3-2) coupled to each other in series
a second branch (104) including:
a third composite transistor (104-1) including a set of transistor devices (104-1-1, 104-1-2) coupled to each other in series;
a fourth composite transistor (104-2) including a set of transistor devices (104-2-1, 104-2-2) coupled to each other in series, wherein the fourth composite transistor (104-2) is coupled to the third composite transistor (104-1) in parallel, and
a sixth composite transistor (104-3) including a set of transistor devices (104-3-1, 104-3-2) coupled to each other in series,
and
wherein the fifth composite transistor (102-3) and the sixth composite transistor (104-3) is configured to supply predefined minor current in the first branch (102) and the second branch (104) of the OP-AMP , and wherein the drain voltage of each of a first transistor device (102-1-1) of the first composite transistor (102-1) of the first branch (102) coupled at the first node and a first transistor device (104-1-1) of the third composite transistor (104-1) of the second branch (104) coupled at a second node is equal to gate voltage of each of the first transistor device (102-1-1) of the first composite transistor (102-1) and the first transistor device (104-1-1) of the third composite transistor (104-1) of the first branch (102) and the second branch (104) and the first transistor device (102-3-1) of the fifth composite transistor (102-3) of the first branch (102) and the first transistor device (104-3-1) of the sixth composite transistor (104-3) of the second branch (104).
7. The OP-AMP as claimed in claim 5, wherein the effective transconductance of each of the first, composite transistor (102-1) , the second composite transistor (102-2), the third composite transistor (104-1) and the fourth composite transistor (104-2) decrease by a factor defined as a function of respective scaling coefficients.