1. A system comprising:
a set of one or more graph processing cores; and
a set of one or more dense compute cores, wherein the set of graph
processing cores and the set of dense compute cores are interconnected, and a
particular one of the set of dense compute cores comprises offload queue circuitry
to:
receive an offload request from a particular one of the set of graph
processing cores, wherein the offload request identifies one or more
functions in a workload to be performed by the particular dense compute
core;
queue the offload request;
configure compute circuitry and memory of the particular dense
compute core to perform the one or more functions;
monitor status of performance of the one or more functions by the
particular dense compute core; and
identify, to the particular graph processing core, the status of
performance of the one or more functions.
2. The system of Claim 1, wherein each graph processing core in the set of
graph processing cores comprises circuitry to implement a respective plurality of
multi -threaded pipelines.
3. The system of Claim 2, wherein each graph processing core in the set of
graph processing cores further comprises circuitry to implement one or more singlethreaded pipelines in addition to the plurality of multi -threaded pipelines.
4. The system of any one of Claims 1-3, wherein each dense compute core
in the set of dense compute cores comprises a respective array of compute circuits.
5. The system of Claim 4, wherein the array of compute circuits comprises
104 INTL-8098-IN
a two-dimensional systolic array.
6. The system of any one of Claims 4-5, wherein configuration of the
compute circuitry comprises configuration of the array of compute circuits.
7. The system of any one of Claims 4-6, wherein the memory of the
particular dense compute core comprises local scratchpad memory.
8. The system of any one of Claims 1-7, wherein one or more of the set of
graph processing cores are resident on a same die with the one or more of the set of
graph processing cores.
9. The system of Claim 8, wherein another one of the set of graph processing
cores in on a different die.
10. The system of any one of Claims 1-9, wherein each of the set of graph
processing cores is optimized for sparse computations associated with graph-based
data structures.