CONFIGURABLE DATA CONVERTER
Field of Invention
The instant invention relates to a configurable data converter.
Background of the Invention
Data converters play important role in the functioning of today's high-performance and mutli-purpose electronic systems. Systems having data converters are responsible for the crucial interface with the devices external to the system. For instance, analog to digital converters (ADC) act as important relays between the physical quantities to be analyzed and the digital processing system, which analyzes the quantities. Normally such conversion requires complicated and large circuitry and precisely matched electrical components, which is one of the most difficult tasks for the engineers. Data converters have vast application ranging from sensor systems to communication chips to digital cameras. Data converters have been designed and used in applications with speed requirements from a few Kilohertz (KHz) to a few Gigahertz (GHz) and resolutions ranging from single bit up to double bits.
Most processing equipments today are digital in nature and work only on digital inputs, whereas the signals received from the real world are real valued or analog in nature, in such situation requirement of analog to digital conversion and/or digital to analog conversion become essential. For example, when the real valued electrical signals/data is obtained from measuring instruments like pressure or temperature sensor, the amplitude of a speech signal, etc. for analog to digital conversion, it is fed to a converter which would comprise a counter and a comparator to provide signals which are binary valued. In a digital or binary representation, a signal is represented by a word which is composed of a finite number of bits. The number of bits is termed as the word length, henceforth denoted by N. Since each bit in the word is either a 0 or 1, the number of possible combinations is finite. The maximum number of possible binary numbers with N bits is equal to 2N. Since an infinite number of real values exist in a given analog range, the binary or digital representation is necessarily an approximate one.
The data converter design space encompasses a wide range of resolutions, bandwidths, accuracies, and design and power requirements. Different designs serve the requirements of different applications and performance needs. The design space is governed by the fundamental trade-offs between speed and performance of electronic systems, which translates to trade-offs between resolution and throughput rate. All data converters require one or more steps for conversion in which the input signal is compared with a reference. The amount of hardware required for this purpose is usually traded off with the time taken for such conversion.
In some cases, at the extreme of design spectrum, silicon area adds another dimension to the trade-offs. Brief comparisons of different ADC architectures are shown in below mentioned table.
(Table Removed)
The table shows well-known analog to digital converters including flash converters, dual-slope, ramp, sigma-delta, successive approximation, etc and their design disadvantages Presently, flash converters are the only known way of obtaining all the output bits in parallel. A N-bit flash converter requires of the order of 2N comparators. If the input signal ranges from 0 to R, the range from 0 to R is divided into 2N levels. These comparators each output a 1 or 0 depending on whether the analog input x exceeds or is below the corresponding level. Decoding logic uses these 2N variables to generate the N output bits The decoding logic is made up of gates. Practical considerations limit the number of inputs (fan-in) and fan-out of each gate. As a result, the delay due to decoding logic increases as O (N log2 N)) or faster. These considerations limit the word length of a flash converter. Since all the bits of a flash converter are obtained simultaneously, the time required to generate the output bits once the analog input has been presented is small.
For example, 3 bits can represent let the output of the microphone and may be denoted by V1, V2, and V3. The number represented by the 3 bits (in millivolts) is given by V1 + 2V2 +
4V3. In general, with N bits, the digital representation is equal to ΣNi=1 2i-1 • Vi . Note that
the significance of VN is the highest (it is weighted by 2N); this bit is termed as the Most Significant Bit (MSB). Conversely, V\ is termed as the Least Significant Bit (LSB) Various combinations of the three bits V1, V2, and V3 can represent Eight (8) possible values The minimum value is 0, which is represented by all three bits being 0. The maximum value is 7, which is represented by all three bits being equal to 1 .
These converters find an N-bit binary word, which best approximates a given analog value x, where N is an integer. An Analog to Digital Converter (ADC) for N bits has N
output bits labelled V1 to VN, where each Vi, i = 1,2, ....N is either 0 or 1. Given an analog input whose value is denoted by a number x, the ADC is required to determine the values
of V1, to VN such that the error |x-Σ Ni=12i-1 Vi| is minimized. For example, if N is
chosen to be 3, then the following table gives the outputs of a 3-bit ADC for different values of x. The range of values of x is assumed to be 0 to 8.

(Table Removed)
Other approaches such as dual-slope and successive approximation methods require considerably less hardware. However, in these methods, the bits cannot be computed in parallel As a result, the time taken to generate the binary approximation, which is termed as the conversion time, is much higher than for a flash ADC.
The conversion time is closely related to the sampling rate that can be handled by the data converter. This is the rate at which input samples can be accepted. Obviously, the ADC cannot take up the next sample until the previous one has been converted.
A new, frequency domain approach called sigma-delta conversion samples the input signal at a high rate to achieve A/D conversion. The scheme requires the extensive use of filters and additional hardware. An additional drawback is the need for the circuitry to work at a high speed; typically much higher than the sampling rate. This also creates hurdles with regard to hardware or circuit realization of such methods.
Similar problems exist for digital to analog converters (DAC) which, in most cases are simply inverted steps when compared with various ADC steps of operation. Hence, all data converters require one or more steps for conversion in which the input signal is
compared with a reference (digital or analog). The amount of hardware required for this purpose usually trades off with the time taken for conversion.
Object and Summary of the Invention
To obviate the aforesaid drawbacks the object of the instant invention is to provide configurable capability for the data converters.
Another object of invention is to provide flexibility to ascertain the configuration according to the application therefore enhancing the security feature by allowing on-board encryption.
Yet another object of the invention is to free the processor from configuration tasks and thus enabling faster data processing.
Yet another object of the present invention is utilizing faster clock and using a subset of the entire set of registers thus same data converter can be made to operate at a faster rate, while reducing the resolution, this provides the flexibility to switch between speeds and
resolutions.
The data conversion challenge is essentially a search on a reference space for a given input signal. Currently available data converters lie at slow end of the spectrum of converters as they incorporate a serial search that takes longer time for conversion. Solution provided by the present invention is capable of providing configurability along with certain level of parallelism in the search of the input against a reference wherein the configuration capability provides a scheme for configuring the local memory whereby alternative scheme for digital error correction may be incorporated.
Brief Descriptions of the Drawings
The present invention is described with the help of accompanying drawings:
Figure-1 shows the conventional analog to digital converter.
Figure-2 shows the present invention.
Figure-3 illustrates timing diagram for multiple ramp converter.
Figure-4 illustrates an embodiment for the present invention as applicable for multiple ramp conversions.
Figure-5 shows another embodiment for the present invention as applicable for the multiple ramp conversions.
Figure-6 shows timing diagram for a single ramp and multiple comparators.
Figure-7 shows an embodiment for digital to analog converter in accordance with the present invention.
Detail Description of the Invention
Present invention deals with the architecture of configurable data converter, which utilizes the advantage of highly dense memory elements in the very large scale integration technology. The embodiment described herein and hereafter describes the invention with reference to analog to digital converters. However, the same concept may be applied for the digital to analog converters.
Ramp ADCs are based on a well-established technique for A/D conversion. Consider an analogue sample x, shown in Figure-1 by a dashed line. The ramp is a signal that increases linearly with time, i.e. it is of the form
Ramp (t) = kt,
Where Ramp (t) denotes the ramp as a signal that is dependent on the variable t (which denotes time), and k is a constant that is termed as the gain or slope of the ramp. The clock is a periodic signal with time period T, which is of the form
m = 0, 1,2, ...
In other words, clock (t) is 0 from time t=0 to t=T/2, 1 from t=T/2 to T, 0 from time t=T to t=3T/2, 1 from time t=3T/2 to 2T, and so on.
Let t = 0 denote the time when the process of converting a given sample x starts. At this time, the counter starts to count from an initial value of zero (0), and the ramp starts from an initial value of zero (0) and begins to increase at a constant time rate towards a maximum value of say, R.
When the ramp and the signal values coincide, say at some time tO, the counter stops. The reading on the counter is the digital equivalent of the sample x, and is read off at this point. The ramp and the counter are reset to their initial values at the start of conversion, so that the next sample can be taken up and converted.
The number of bits in the counter indicates the resolution of the converter. The resolution of the converter determines the precision to which the sample x has been represented in digital form
In a ramp converter, the counter is usually implemented by means of a set of N flip-flops or latches The flip-flop is a memory element that can have an output, which is either a 1 or a 0. In addition to flip-flops or latches, a counter requires combinational logic, which is usually realized by using logic elements such as gates or multiplexers.
A Ramp ADC, which produces an output of N bits, needs a N-bit counter. Such a counter would need N flip-flops. In such a case, the maximum count on the counter is given by 2N -1; including the initial state of all zeroes, the total number of possible output words is
2N. For example, a 10-bit ADC would have a counter with 10 flip flops, which would have a maximum count of
2N- 1 =210- 1 = 1024- 1 = 1023
The speed of a Ramp ADC is typically slow, because of limitations on the speed of the
counter and the time taken to reach the maximum count, i.e. the worst-case conversion
time is large.
The number of logic elements required for implementing the counter increases rapidly
with N, and this also contributes to the low speed of Ramp ADCs, particularly for a large
number of bits. The proposed invention relates to a scheme, which overcomes such
limitations.
Figure-2 shows the proposed conversion scheme. In its simplest form, a N-bit ADC in the proposed invention uses 2N flip-flops or, preferably, latches. All the latches are initially reset to state "0", except the first one, which contains a "1". The scheme uses a ramp and a clock as in a typical Ramp ADC. At t=0, the value of the ramp is also 0. Once the conversion process is initiated, the ramp increases at a constant rate. The clock is also turned on at the same time. With each clock period, the " 1" moves from one latch to the next; the latch which previously contained the " 1" takes on the value of its predecessor, which was a 0 (since only one latch contains a "1"). The first latch takes on the value of the last latch; the set of latches can be thought of as a ring.
When the ramp equals the sample value x, the comparator signals end of conversion, and the clock is no longer effective, i.e. the circulation of the "1" element from one latch to the next stops. At this point, the latch which contains the "1" indicates the conversion code. The code itself may be held in a register, which its corresponding latch in the above enables mentioned ring.
Alternatively, the entire group of registers is used in the following way. At each clock, each register (which contains a N bit word) takes on the value of its predecessor, and the
circulation stops when the ramp equals the sample value. In this case, 2N registers, each containing N bits, are needed.
In ideal condition the ramp output should be a straight line with a constant slope but cannot be realized in practice as shown in Figure-3. In practice one obtains a characteristic with a droop, this means that the time at which the ramp equals the sample signal x will be different from the ideal case. The proposed invention is an attempt to correct this non-linearity, which may be achieved by configuring the appropriate registers. This configuration can also be applied to correct other defects, which may be present at the time of manufacture, or arises due to ageing or environmental factors.
Multiple ramps may be used to improve the speed and linearity. As shown in Figure-4, one can have two ramps, the first of which starts from 0 to R/2 in place of R and the other which rises from R/2 to R. This allows the search for the right configurability, to be done in half the time, here the cost for additional ramp is almost negligible.
Figure-5 shows an embodiment, which uses single ramp and two comparators. The first comparator operates as usual, while the second comparator has a threshold, which is offset from the first by R/2. The first comparator signals end of conversion in case the signal lies in a range 0 to R/2; the configuration word in then found in the first half of the registers set i.e. in the first 2N-1 registers. The second comparator has a threshold offset of R/2, i.e. its output becomes equal to 1 when the ramp equals x + R/2. The output of second comparators is used when the signal lies in the range R/2 to R. In such a case, configuration word is found in the second half of the register set. Multiple comparators operating in parallel can be used to obtain higher conversion speed. Here the use of single ramp avoids potential alignment and non-linearity problems. Figure-6 shows the timing diagram of single ramp and multiple comparator arrangement as described in Figure-5. However this configuration is scalable in terms of comparator utilization.
Embodiments outlined here uses very little switching. Extremely low power designs are possible using the proposed invention, because the switching can be limited to only two
shift registers or memory cells. The power consumption of the ramp will need to be added, however this is extremely low compared to any other architecture. The above idea may be applied in reverse to formulate a digital to analog conversion.
The invention herein is described with reference to an analog to digital converter however, a person skilled in the art will appreciated that the concept of the invention can be easily implemented for the a digital to analog converter (DAC), wherein the analog comparator is replaced by a digital comparator and process can be carried out in reverse order to obtain an analog signal form a given digital signal. The embodiment for DAC is illustrated in Figure-7.
It is believed that the present invention and many of its attendant advantages will be understood by the foregoing description. It is also believed that it will be apparent that various changes may be made in the form, construction and arrangement of the components thereof without departing from the scope and spirit of the invention or without sacrificing all of its material advantages. The form herein before described being merely an exemplary embodiment thereof, it is the intention of the following claims to encompass and include such changes.

We claim:
1. A configurable data converter comprising:
a comparator having a first and second inputs for comparing its first and second inputs;
an array of memory elements for providing an output of said converter; a pointer for pointing to a row or column of said array; and a control block having a clocking system receiving output of said comparator and providing a control signal to said pointer, such that whenever a conversion operation is initiated the control block resets the pointer and starts shifting serially said pointer according to clocking system of said control block and on receipt of output of the comparator selects instantaneous row or column pointed by the pointer, and provides contents of the selected row or column at the output of the converter which corresponds to a data converted equivalent to a received signal.
2. A configurable data converter as claimed in claim 1, wherein said comparator is
an analog comparator comprising at least one operational amplifier having at least
one of its input as a reference voltage input.
3. A configurable data converter as claimed in claim 1, wherein said comparator is
digital comparator comprising at least one operational amplifier having at least
one of its input as a reference voltage input
4. A configurable data converter as claimed in claim 1, wherein shifting of said
pointer is done at positive, negative or both clock edge of the clocking system.
5. A configurable data converter as claimed in claim 1, wherein configuration of the
memory array element is determined according to the desired output code.
6. A configurable data converter as claimed in claim 1, wherein said control block
provides a logic for selecting a mode for setting the pointer to point at a fixed row
or column of the memory array element and altering the content of the memory array element at each clock edge of the clocking system according to the desired output code.
7 A configurable data converter as claimed in claim 1, wherein altering of the
memory array element content is done sequentially or parallely in a cyclic or in
accordance with the desired output code.
8 A method for configuring and converting data signals; said method comprising
the steps of:
providing comparator for comparing its first and second input signals;
providing an array of memory elements;
providing a pointer for pointing a row or column of said array;
providing a control block having a clocking system receiving output of
said comparator and providing a control signal to said pointer;
comparing said first and second input of the comparator;
initating pointer shifting operation simultaneously with the comparison
operation;
receiving output of the comparator at the control block;
selecting instantaneous row or column pointed by the pointer; and
outputting content of the selected row or column which corresponds to an
equivalent of the data signals.
9. A method for configuring and converting data signals as claimed in claim 8, wherein said step of initiating pointer shifting is done by the control block in accordance with the build in clocking system.
10 A method for configuring and converting data signals as claimed in claim 8, wherein said shifting of pointer is done at positive, negative or both clock edge of the clock provided by the clocking system of the control block.
11 A method for configuring and converting data signals as claimed in claim 8,
wherein said step of providing an array of memory elements having a step of
determining the configuration manner of said array according to the desired
output code.
12 A method for configuring and converting data signals as claimed in claim 8,
wherein said step of initiating pointer shifting operation comprising the step of
setting the pointer to point at a fixed row or column of the memory array and
altering the content of the memory array at each clock edge of the clocking
system according to the desired output code.

13. A configurable data converter substantially as herein described with reference to
and as illustrated in the accompanying drawings
14. A method for configuring and converting data signals substantially as herein
described with reference to and as illustrated in the accompanying drawings