Claims:1. A contriving system for configurable Radar waveform and test target generation, the system comprising:
a Field Programmable Gate Array (FPGA) in communication with a controller, the FPGA comprising one or more processors coupled with a memory storing instructions executable by the one or more processors to perform:
receive a first set of data packets pertaining to a set of signals to be generated by the FPGA;
extract a waveform coefficient from a dataset comprising waveform coefficients associated with pre-defined waveforms; and
contrive a Radar waveform taking into consideration the extracted waveform coefficient, and correspondingly generate the set of signals.
2. The system as claimed in claim 1, wherein the contriving of waveform comprises any or a combination of waveform synthesis, I/Q modulation, intermediate (I/F) frequency generation, linearization, filtering, timing and synchronization signals generation, and DC offset correction.
3. The system as claimed in claim 1, wherein the system comprises a waveform generation interface configured to generate and transmit one or more Radar waveforms with provision of on-the-fly configuration through the controller over a network.
4. The system as claimed in claim 1, wherein the system comprises a timing control generation interface configured to generate timing signals for one or more components of the system and also for providing health status of each of the one or more components to the controller.
5. The system as claimed in claim 1, wherein the system comprises a test target simulation interface configured to generate test targets through the controller over the network, and thereby evaluate performance of a Radar receiver.
6. The system claimed in claim 1, wherein the system incorporates provision of real-time overlapping of the test targets, and wherein the system facilitates precise control of a target waveform phase and amplitude that is crucial in discriminating the closely spaced test targets in real time.
7. The system apparatus as claimed in claim 1, the system comprises a digital to analog convertor with LO reference generated directly by an on-chip numerically controlled oscillator.
8. The system as claimed in claim 1, the system employs a unique PCB design made from derivative of FR4 dielectric material, thereby reducing fabrication complexity, providing better thermal management and associated cooling mechanism, resulting in cost reduction.
9. The system as claimed in claim 1, wherein single RF channel is used in time division multiplexing mode for transmitting the contrived waveform and the test waveform; wherein a switch control is configured to switch between contrived waveform generation mode and test waveform generation mode.
10. The system as claimed in claim 1, wherein the system comprises a sensitivity timing control (STC) interface configured to control sensitivity timing by introducing a pre-defined range based attenuation, thereby avoiding saturation of a Radar receiver.
, Description:TECHNICAL FIELD
[0001] The present disclosure relates to the field of Radar (Radio Detection and Ranging)-based technology. In particular, the present disclosure provides an efficient contriving system for configurable Radar waveform and test target generation.

BACKGROUND
[0002] The background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Performance of any modern RADAR system is significantly enhanced when it has the capability to generate various types of signal waveforms on-the-fly with the least changeover time. The signal can either be generated at Intermediate Frequency (IF) directly or using the base-band components, which are combined to form the IF signal. Some of the types of waveforms typically generated are continuous wave, frequency modulated, amplitude modulated or sweep signals.
[0004] Different types of waveforms are employed to enhance the radar performance, in terms of side lobe reduction, pulse compression ratio and overall system SNR. These radar waveforms can be completely characterized by carrier frequency, pulse width, Pulse Repetition Frequency (PRF), pulse modulation and Intermediate frequency bandwidth. Radar design dictates choice of carrier frequency, while pulse width and bandwidth are decided by processing gain and range resolution.
[0005] Therefore, it is very imperative for a Radar exciter to have flexible hardware which is configurable in terms of waveform selection at desired IF/direct RF level, with required timing/synchronization signals adaptable to Radar platform. In addition to this if target simulation capability is also built-in then such hardware becomes very much indispensable for any modern Radar.
[0006] Patent Document US20050040984A1 discloses a radar based application programmable waveform generator component of an apparatus that generates multiple waveforms and controls phase and amplitude of one or more parts of the generated waveforms. The invention incorporates a method that involves signal processing for I/Q modulation, linearization, filtering and DC offset correction in final waveform output to the transmitter. The method includes a processor and, two memory components primary for storing waveforms and secondary for processor memory and instruction execution. However, it includes many components that makes the system complex and costly.
[0007] Patent Document US7145504 discloses an arbitrary RADAR target synthesizer in which the targets are induced at ranges by time-delays from controller at RF level by using fiber optic means. Multiple RF channels are used to generate multiple targets with different ranges and Doppler at RF level. The synthesizer also includes a processor adapted to receive Target and waveform parameters and induce targets and up-convert it to RF level.
[0008] There is, therefore, a need in the art to provide a system that obviates above-mentioned limitations and is efficient, accurate, precise, and compact.

OBJECTS OF THE PRESENT DISCLOSURE
[0009] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.
[0010] It is an object of the present disclosure to provide a system for waveform, timing, and test target generation for radar exciter/receiver applications.
[0011] It is another object of the present disclosure to provide a system that can serve the purpose of test target simulator with capability to generate multiple targets with desired range, target spacing, radial velocity with Doppler incorporated to extensively validate the receiver chain processing.
[0012] It is another object of the present disclosure to provide a system capable to operate in target generation mode with target parameters controlled remotely by Radar controller over wired network.
[0013] These and other objects of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings.

SUMMARY
[0014] The present disclosure relates to the field of Radar (Radio Detection and Ranging)-based technology. In particular, the present disclosure provides an efficient contriving system for configurable Radar waveform and test target generation.
[0015] An aspect of the present disclosure pertains to a system comprising: a Field Programmable Gate Array (FPGA) in communication with a controller, the FPGA comprising one or more processors coupled with a memory storing instructions executable by the one or more processors to perform: receive a first set of data packets pertaining to a set of signals to be generated by the FPGA; extract a waveform coefficient from a dataset comprising waveform coefficients associated with pre-defined waveforms; and contrive a Radar waveform taking into consideration the extracted waveform coefficient, and correspondingly generate the set of signals.
[0016] In an aspect, the contriving of waveform comprises any or a combination of waveform synthesis, I/Q modulation, intermediate (I/F) frequency generation, linearization, filtering, timing and synchronization signals generation, and DC offset correction.
[0017] In another aspect, the system comprises a waveform generation interface configured to generate and transmit one or more Radar waveforms with provision of on-the-fly configuration through the controller over a network.
[0018] In an aspect, the system comprises a timing control generation interface configured to generate timing signals for one or more components of the system for providing health status of each of the one or more components to the controller.
[0019] In an aspect, the system comprises a test target simulator configured to generate test targets through the controller over the network, and thereby evaluate performance of a Radar receiver.
[0020] In an aspect, the system incorporates provision of real-time overlapping of the test targets, and wherein the system facilitates precise control of a target waveform phase and amplitude that is crucial in discriminating the closely spaced test targets in real time.
[0021] In an aspect, the system comprises a digital to analog convertor with LO reference generated directly by an on-chip numerically controlled oscillator.
[0022] In one aspect, the system employs a unique PCB design made from derivative of FR4 dielectric material, thereby reducing fabrication complexity and providing better thermal management and associated cooling mechanism.
[0023] In other aspect, single RF channel is used in time division multiplexing mode for transmitting the contrived waveform and the test waveform; wherein a switch control is configured to switch between contrived waveform generation mode and test waveform generation mode.
[0024] In another aspect, the system comprises a sensitivity timing control (STC) interface configured to control sensitivity timing by introducing a pre-defined range based attenuation, thereby avoiding saturation of a Radar receiver.
[0025] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0027] FIGs. 1A and 1B illustrate exemplary block diagrams associated with the proposed system to illustrate its overall working, in accordance with an embodiment of the present disclosure.
[0028] FIG. 2 illustrates an exemplary architecture of the proposed system, in accordance with an embodiment of the present disclosure.
[0029] FIG. 3 illustrates a flow diagram representing designing of the proposed system, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0030] In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
[0031] The present disclosure relates to the field of Radar (Radio Detection and Ranging)-based technology. In particular, the present disclosure provides an efficient contriving system for configurable Radar waveform and test target generation.
[0032] According to an aspect, the present disclosure pertains to a system including: a Field Programmable Gate Array (FPGA) in communication with a controller, the FPGA comprising one or more processors coupled with a memory storing instructions executable by the one or more processors to perform: receive a first set of data packets pertaining to a set of signals to be generated by the FPGA; extract a waveform coefficient from a dataset including waveform coefficients associated with pre-defined waveforms; and contrive a Radar waveform taking into consideration the extracted waveform coefficient, and correspondingly generate the set of signals.
[0033] In an embodiment, the contriving of waveform can include any or a combination of waveform synthesis, I/Q modulation, intermediate (I/F) frequency generation, linearization, filtering, timing and synchronization signals generation, and DC offset correction.
[0034] In another embodiment, the system can include a waveform generation interface configured to generate and transmit one or more Radar waveforms with provision of on-the-fly configuration through the controller over a network.
[0035] In an embodiment, the system can include a timing control generation interface configured to generate timing signals for one or more components of the system for providing health status of each of the one or more components to the controller.
[0036] In an embodiment, the system can include a test target simulator configured to generate test targets through the controller over the network, and thereby evaluate performance of a Radar receiver.
[0037] In one embodiment, the system can incorporate provision of real-time overlapping of the test targets, and wherein the system can facilitate precise control of a target waveform phase and amplitude that is crucial in discriminating the closely spaced test targets in real time.
[0038] In other embodiment, the system can include a digital to analog convertor with LO reference generated directly by an on-chip numerically controlled oscillator.
[0039] In another embodiment, the system can employ a unique PCB design made from derivative of FR4 dielectric material, thereby reducing fabrication complexity and providing better thermal management and associated cooling mechanism.
[0040] In an embodiment, single RF channel can be used in time division multiplexing mode for transmitting the contrived waveform and the test waveform; wherein a switch control can be configured to switch between contrived waveform generation mode and test waveform generation mode.
[0041] In another embodiment, the system can include a sensitivity timing control (STC) interface configured to control sensitivity timing by introducing a pre-defined range based attenuation, thereby avoiding saturation of a Radar receiver.
[0042] FIGs. 1A and 1B illustrate exemplary block diagrams associated with the proposed system to illustrate its overall working, in accordance with an embodiment of the present disclosure.
[0043] Referring to FIG. 1A, the proposed contriving system for configurable radar waveform and test target generation 100 (interchangeably referred to as contriving system 100 or system 100, hereinafter) can include a controller 102 (interchangeably referred to as Radar controller 102, hereinafter) that can be configured to generate a first set of data packets based on a set of instructions entered by a user. The first set of data packets can pertain to a set of signals to be generated by the system 100 in order to facilitate contriving of a Radar waveform. In an exemplary embodiment, the controller 102 can include one or more buttons that can be clicked by the user, and corresponding set of signals can be generated.
[0044] In an embodiment, the system 100 can include a Field Programmable Gate Array (FPGA) 104 that can be in communication with the controller 102, where the FPGA can include one or more processors and a memory both coupled to each other. In an embodiment, the generated first set of data packets can be transmitted from the controller 102 to the FPGA 104 through a network, where the network can be a wired or a wireless network.
[0045] In one embodiment, the FPGA 104 can receive the transmitted first set of data packets, and can correspondingly extract a waveform coefficient from a dataset comprising waveform coefficients associated with pre-defined waveforms. Further, the FPGA 104 can contrive a Radar waveform taking into consideration the extracted waveform coefficient, and correspondingly generate the set of signals. In an exemplary embodiment, the contriving of waveform can include any or a combination of waveform synthesis, I/Q modulation, intermediate (I/F) frequency generation, linearization, filtering, timing and synchronization signals generation, and DC offset correction. In an exemplary embodiment, the system 100 can include multiple modulation schemes including linear, no-linear, poly phase as required for specific requirement.
[0046] In an embodiment, referring to FIG. 1B, the system 100 can include a waveform generation logic 112 (interchangeably referred to as waveform generation interface 112, herein) configured to generate and transmit one or more Radar waveforms with provision of on-the-fly configuration through the controller 102 over the network. In other embodiment, the system 100 can include a timing control generation logic 114 (interchangeably referred to as timing/ sync control generation interface 114, herein) that can be configured to generate timing signals (also referred to as sync signals, hereinafter) for one or more components of the system 100 for providing health status of each of the one or more components to the controller 102. In an exemplary embodiment, the timing signals can aid in phase synchronization of the Radar waveforms, which plays a vital role in the overall operation of any Radar-based system.
[0047] In another embodiment, the system 100 can include a test target simulator 116 (also referred to as test target simulation logic 116, herein) that can be configured to generate test targets through the controller 102 over the network, and thereby can evaluate performance of a Radar receiver that can be configured to receive a Radar waveform when it gets reflected due to collision with any of the generated test targets. In an exemplary embodiment, the test target simulator 116 can generate a stationary test target as well as a moving test target having pre-defined parameters including, but not limited to, position, velocity, tilt, and acceleration of the moving test target, number of targets, and target range, where the parameters can be varied to facilitate controlled movement of the test target.
[0048] In an exemplary embodiment, the target simulator 116 can generate test targets at specified range, target spacing with provision of Doppler, radial velocity, Azimuth speed on-the-fly to evaluate the entire RADAR receiver chain performance.
[0049] In an implementation, the system 100 can incorporate provision of real-time overlapping of the test targets, and wherein the system can facilitate precise control of a target waveform phase and amplitude that is crucial in discriminating the closely spaced test targets in real time.
[0050] In an embodiment, the system 100 can include a synthesizer 108 that can be configured to generate a precise Radar reference clock and pre-defined local oscillator (LO) reference signals for facilitating up-conversion. In other embodiment, the system 100 can include an up conversion logic 118 (interchangeably referred to as up conversion interface 118, herein) that can be configured to up convert an I/F frequency Radar waveform to a frequency band of interest for transmission using the LO reference from the synthesizer 108, where the frequency band of interest can be of a higher frequency than the I/F frequency Radar. In an exemplary embodiment, direct up-conversion to RF frequency band of interest can be feasible with high speed DAC incorporated on the proposed system, which can go up-to L-band. This approach can reduce hardware complexity involved with RF portion, as well as significantly can improve reliability of the hardware. In another exemplary embodiment, Radars configured at the system 100 can incorporate digital domain processing right up to antenna with high speed DAC in built within FPGA to perform up-conversion. This approach significantly can reduce cost and complexity of the system and can improve the system reliability.
[0051] In another embodiment, the system 100 can include a down convertor 110 (also referred to as RF down convertor 110, herein) that can be configured to down convert a Radar waveform to intermediate radio frequency (RF) level for further down chain target signal processing.
[0052] In an embodiment, the system 100 can include a Local Oscillator-based distribution unit 106 (interchangeably referred to as LO distribution unit 106, hereinafter) that can be configured to distribute the LO reference signals to any or a combination of the up conversion interface 118 and the down convertor 110. In an exemplary embodiment, the system 100 can be equipped with a switch control for switching between operation mode (also referred to as contrived waveform generation mode, herein) and target simulation mode (also referred to as test waveform generation mode, herein), wherein during the operation mode, the system 100 can operate to contrive a Radar waveform, and during the target simulation mode, the system 100 can operate to simulate the test targets.
[0053] In an implementation, a single RF channel can used in time division multiplexing mode for transmitting the contrived waveform and the test waveform, and where the switch control is configured to switch between the contrived waveform generation mode and the test waveform generation mode.
[0054] In other embodiment, the system 100 can include a sensitivity timing control (STC) logic 120 (also referred to as STC interface 120, or STC module 120, herein) that can be configured to control sensitivity timing by introducing a pre-defined range based attenuation, thereby avoiding saturation of the Radar receiver.
[0055] In an embodiment, the one or more components of the proposed system 100 can include, but not limited to, the FPGA 104, the LO distribution unit 106, the synthesizer 108, the RF down convertor 110, the waveform generation interface 112, the timing control generation interface 114, the test target simulator 116, the up conversion interface 118, and the STC interface 120, where functionalities of the waveform generation interface 112, the timing control generation interface 114, the test target simulator 116, the up conversion interface 118, and the STC interface 120 can be incorporated in a single-FPGA based hardware. In addition to improving reliability by avoiding multiple hardware components and interconnectivity between them, the system 100 can be very flexible, minimal power consuming, and, low cost alternative to the conventional systems and methods.
[0056] In an embodiment, the system 100 can include a single processor for control component and signal processing components, and both types of components are merged and implemented within same chipset. In another embodiment, the system 100 alleviates phase offset errors resulting in the DC offset introduced in output waveform by facilitating tight phase synchronization control mechanism. Moreover, the system 100, in addition to waveform generation, is also capable of adding Doppler to the generated waveform thereby acting as real time test target simulator.
[0057] In another embodiment, in the system 100 targets are generated at I/F level with precise timing control and details of parameters like number of targets, target range, target velocity, and the like, can be configured at the system 100 as and when required. Moreover, instead of adding Doppler at RF level by using high cost fiber optic medium, the system 100 can effectively add Doppler at IF level, which is more precise and accurate method.
[0058] Conventional Radar systems include multiple RF channels with one channel for each target generated with specific range and Doppler. In real time, multiple antennas transmit different targets and hence such systems become cumbersome if targets increase in number. However, the proposed system 100 is flexible and cost effective in which multiple targets generation can be carried out with single RF channel and transmitter. In fact using the system 100, same transmitter can be used for waveform transmission as well as target generation in time-division multiplexing mode.
[0059] FIG. 2 illustrates an exemplary architecture of the proposed Radar system, in accordance with an embodiment of the present disclosure.
[0060] Referring to FIG. 2, the Radar controller 102 can communicate with other components of the system 100 remotely over a wired network, which can support both Ethernet and fiber network. All the corresponding network protocols can be implemented optionally within a FPGA fabric microprocessor protocol stack. Hence, there may be less dependency on type of network configuration and proven interface even for status and health monitoring of the one or more components of the system 100.
[0061] In an exemplary embodiment, different waveforms can be ported on the same FPGA stack based hardware with all the waveform coefficients stored in an external flash memory 202-1, and an external memory 202-2 can be configured to store data and clock related information. Based on the requirement, appropriate waveforms can be loaded from the memory 20201with I/Q modulation performed within the FPGA fabric logic containing abundant digital signal processing blocks (also, referred to as DSP specific blocks). Programmable DDS based NCO (numerically-controlled oscillator) can be available for configurable IF frequency generation and driving external DAC (digital-to-analog converter) on the hardware. Control logic generation for external up converter can also be supported and in case of direct up conversion, RF DAC can be available that can be provisioned and controlled from the FPGA 104.
[0062] In an embodiment, the system 100 can include a very high speed digital to analog convertor with LO reference generated directly by the on-chip numerically controlled oscillator. This method may greatly enhance the system’s reliability and maintainability that is achieved by replacing analog by digital circuitry.
[0063] In an exemplary embodiment, all industry standard interfaces, including, but not limited to, I2C, LVDS, MLVDS, and RS422/485 can be easily supported by the system 100 and can be activated for interfacing other sub-systems. Sync/trigger signals for the complete Radar systems can be generated with full coherency and phase synchronization with the inherent low clock skew clock routing resources within the FPGA 104.
[0064] In an embodiment, the system 100 can include a Printed-Circuit Board (PCB) that can be configured to accommodate circuits associated with components of the system, wherein the PCB design for the hardware can be based on stack-up with derivative of FR4 di-electric material compared to metal core PCB stack-up which is generally user for such applications. Metal core PCB's employ dedicated copper layer for thermal dissipation and normal through hole vias are not possible to route through all the PCB layers thereby complicating the routing of PCB traces. Present design uses thermally efficient derivative of FR4 with normal through hole vias for trace routing and for power dissipation all thermal vias are stitched to metal plating on edges of the PCB with mechanical enclosure abutting the PCB metal edges.
[0065] In another embodiment, the unique PCB design can aid in reducing fabrication complexity and providing better thermal management and associated cooling mechanism. It also results in lowering the cost. Careful selection of derivative of FR4 dielectric material for design may resulted in better thermal management and associated cooling mechanism required for such applications.
[0066] In an embodiment, mechanical enclosure associated with the system 100 can be designed for conduction cooled applications and it can easily be adaptable to various deployment environments with minimal changes.
[0067] FIG. 3 illustrates a flow diagram representing designing of the proposed system, in accordance with an embodiment of the present disclosure.
[0068] In an embodiment, the design philosophy followed in the present system 100 is based on hardware-software co-design. The complete design functionality can be partitioned into hardware and software, with embedded microprocessor within the FPGA fabric used for software and custom system specific hardware implemented in the FPGA fabric. The interface between hardware and software portions is very critical in such embedded system and the FPGA vendor driver/IP libraries may aid in verification process.
[0069] In an exemplary embodiment, hardware design of the system 100 can be based on RTL design flow with processing resources (on-chip block RAM memory, hardware multipliers, DDS based NCO's for clock generation) used for implementing custom logic. Functional and timing simulation can be used for verifying the custom hardware logic and processor bus interfaces. FPGA vendor specific tools can map the user logic and the pre-defined IP libraries from vendor and can aid in integration of the both hardware and software portions of the design. In an exemplary embodiment, on-chip NCO can be re-configurable and can be tuned to generate variable intermediate frequency of interest, depending on the exciter design and Radar frequency band of interest, the IF can be varied with modulation performed on baseband waveform. All the changes can be done in-system without having to go for hardware re-spin.
[0070] In another exemplary embodiment, software design of the system 100 can be based on 32-bit microprocessor embedded within FPGA vendor fabric. The 32-bit microprocessor can be fully configurable to include memory and other standard bus based interfaces required for the design. Unlike conventional off-the-chip microprocessor with fixed architecture, the embedded FPGA based microprocessor can be tailored to include only required functionality for the application as provides a re-configurable platform. Vendor specific tools can aid in compiling, simulating and de-bugging application code on industry standard software platform.
[0071] Finally, final design of the system 100 can be validated by merging of the hardware and software portions done with the vendor toolset and further, the finalized design can be ported on the FPGA chipset with JTAG based emulator. The system 100 can facilitate easy and effective programming and debugging wherein both the hardware and software portions can be tested in parallel in real time. Changes in the hardware/software can be done on the fly resulting in instant turn-around time for developing prototype.
[0072] Thus, it will be appreciated by those of ordinary skill in the art that the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this invention. The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named.
[0073] While embodiments of the present invention have been illustrated and described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the invention, as described in the claim.
[0074] In the foregoing description, numerous details are set forth. It will be apparent, however, to one of ordinary skill in the art having the benefit of this disclosure, that the present invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention.
[0075] As used herein, and unless the context dictates otherwise, the term "coupled to" is intended to include both direct coupling (in which two elements that are coupled to each other contact each other)and indirect coupling (in which at least one additional element is located between the two elements). Therefore, the terms "coupled to" and "coupled with" are used synonymously. Within the context of this document terms "coupled to" and "coupled with" are also used euphemistically to mean “communicatively coupled with” over a network, where two or more devices are able to exchange data with each other over the network, possibly via one or more intermediary device.
[0076] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refers to at least one of something selected from the group consisting of A, B, C …. and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc.
[0077] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.
ADVANTAGES OF THE PRESENT DISCLOSURE
[0078] The present disclosure provides a system for waveform, timing, and test target generation for radar exciter/receiver applications.
[0079] The present disclosure provides a system that can serve the purpose of test target simulator with capability to generate multiple targets with desired range, target spacing, radial velocity with Doppler incorporated to extensively validate the receiver chain processing.
[0080] The present disclosure provides a system capable to operate in target generation mode with target parameters controlled remotely by Radar controller over wired network.