We claim:
1. Control mechanism for Dual Lane Engine Control unit in Aircraft Turbofan Engine comprises of:
-a signal conditioning analog circuit (8a & 8b) with high precision, low noise, ripple rejection filters to smoothen the signal received from engine sensors.
-a redundant secure communication link (6) between
two Lane through CAN and EBI which is optically isolated
for interchange of sensor inputs and for onboard
continuous data sharing.
-a Built-in^self check circuit(4) to arrive at error code of
the both lanes.
-a lane Changeover Logic circuit (3) design with combinational logic gate that can automatically change to redundant lane, in case of failure of CPU.(2A& 2B).
-a priority hardware circuit(lA& IB) for manual control of the lane that overrides all the said functional configurations.
2. The analog signal conditioning analog circuit (8A& 8B) circuit as claimed in claim 1 is built on a FPGA parallel data (4A& 4B) to meet the lOmSec loop time, an Instrument amplifier is to achieve gain factor of 65db and active RC filters to achieve ripple reduction upto .80%.
3. The Built-in-self check circuit(4) as claimed in claim 1 is integrated with all the functional circuits for detecting abnormalities of Lane resources by means of said signal conditioning analog circuit (8A& 8B) analog circuit (1), Other lane Shared data analysis received by means of said redundant secure communication link (6) , Health check of processing circuit and accumulating level wise Error Code of both the lanes.
4. The Lane Change over Logic circuit(3) as claimed in claim 1 characterized for switching the Lane based on the data received from the said redundant secure communication link (6) and Two hardware watchdog timer (5A & 5B) which continually monitor the health of Processor and FP.GA.
5. The switching mechanism of the said Lane Change over Logic circuit(3) as claimed in claim 4 is inbuilt with SR Latch circuit for switching between active and standby lanes.
6. The priority hardware circuit(lA& IB) as claimed in claim 1 is built with switching circuit that bypasses the command logic generated by CPU (2A& 2B) &/or Lane changeover logic circuit (3).