FIELD OF THE INVENTION
The present invention is designed as universal IC tester and
programmer Socket/Interface. It can be used as an interface between
standard programming tools and CPLD ICs.
BACKGROUND OF THE INVENTION
A high failure rate of CPLD ICs has been observed during the
testing and diagnosis of the assembled electronic cards. The root cause
analysis of the failure is very difficult once the CPLD is assembled in the PCB.
The faulty CPLD can create following problems during assembly and testing
of electronic cards-
1. Generates complex multiple failures of the electronic cards.
2. Reduces the quality and reliability of the cards due to frequent
component changes.
3. Increases the overall cycle time of repair and testing.
4. Reduces the overall productivity.
To reduce the failure rate of electronic cards from faulty CPLD
components, “CPLD IC tester and programming PCB socket” has been
developed to diagnose, analyze and program the CPLD before the final
assembly in cards. This socket helps in segregating and timely disposition of
the faulty CPLDs before use.
SUMMARY OF PRESENT INVENTION
Present Invention can be used as standard interface socket between
the CPLD and the JTAG complaint serial interface CPLD programmer.
With the help of this tool, CPLD IC is checked and analyzed before
assembly in the final electronic board. If the CPLD is faulty, it rejects the faulty
CPLD before final assembly. This saves cycle time of the electronic boards
and increases the overall productivity of the workshop. Quality and reliability
of the product is also improved due to pre-check of CPLD.
Annexure‐II
The device is completely reconfigurable and can be customized with
the changes of the CPLD versions and the pin configuration. This device is
compatible with the PCI local bus specification, Therefore communicates
easily with the standard controllers (PC/PCI). Analysis and diagnosis of the
faulty CPLD can be customized as per the requirement.
The device operates with a 5V power supply and supports 5V or 3.3V
I/O levels, therefore both the TTL and JEDEC standard CMOS levels are
satisfied. Flexible clocking method is used with the help of synchronous
clocks. Quartz crystal are used for synchronization and timing
The device has feature of user programmable bus-hold capabilities on
all I/Os. Programmable slew rate control which sets the output slew rate to
fast or slow can also be extended in this device.
The device is compact, portable, easy to repair, simple and
reconfigurable. Concept can also be used in other programmable as well as
standard nonprogrammable ICs
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention will become
more apparent and descriptive in the description when considered together
with figures/flow charts presented:
Fig. 1 is a Block Diagram of “CPLD IC tester and programming PCB socket”
Fig. 2 is a Schematic (Abstract) Diagram of “CPLD IC tester and
programming PCB socket”
DETAILED DESCRIPTION
CPLDs are the basic building blocks of all the modern
embedded electronics circuitries. Proper functioning and performance
of the CPLD is very important for the accurate and well defined
operation of the electronic circuitry. Faulty CPLD can lead to variety of
problems, which are very difficult to diagnose and rectify.
Annexure‐II
The CPLDs are electrically erasable and In-System
reprogrammable (ISR), therefore programming of CPLD can also be
done without integration into the actual electronic card. With the help of
the controller (PC/IPC) interfaced with the JTAG complaint serial
interface CPLD programmer, functionality of the CPLD is directly
checked only by mounting the CPLD on the present invention.
Figure-1 shows the block diagram of the interface card “CPLD
IC Tester and programming PCB socket”, standard JTAG complaint
serial interface CPLD programmer and the controller (PC/IPC). Data is
shifted in and out TDI and TDO pins respectively. Because of the
superior routability and simple timing model of the device, ISR allows
user to change existing logic design while simultaneously fixing pinout
arrangements and maintaining system performance. The entire device
features JTAG compatibility for In-System reprogrammable (ISR) and
boundary scan, and is compatible with the PCI local bus specification.
The controller (PC/IPC) configured with all the necessary
application and software is used to analyze the CPLD. Failure
characteristics and the symptoms is easily monitored. Programming
and reprogramming is done to analyze the pattern. Boundary scan
facility helps in locating the exact fault of the IC.
Figure-2 shows the abstract schematic diagram of the “CPLD IC
Tester and programming PCB socket”. This includes mounting PCB,
JATAG serial interface connector, CPLD mounting base, crystal for
clock generation, Reset signaling button and power supply. The
construction is simple compact and portable.
The device operates with a 5V power supply and can support 5V
or 3.3V I/O levels. Vcc connections provide the capability of interfacing
to either a 5V or 3.3V bus. By connecting the Vcc pins to 5V the user
ensures 5V TTL levels on the outputs. If Vcc is connected to 3.3V the
output levels meet 3.3V JEDEC standard CMOS levels. Device
operating with a 3.3V supply require 3.3 V on all Vcc pins, reduces the
device power consumption. Therefore both the TTL and JEDEC
standard CMOS levels can be satisfied.
Flexible clocking method is used with the help of synchronous
clocks. Quartz crystal are used for synchronization and timing. Product
Term clocking can also be used. The input and output pins of CPLD
TDI and TDO are connected to the JTAG connector (provide the
reconfigurability). The device has feature of user programmable bushold
capabilities on all I/Os. Programmable slew rate control which sets
Annexure‐II
the output slew rate to fast or slow (designs concerned with meeting
FCC emission standards) can also be extended in this device.
The present invention can be customize and upgrade for the
fault finding and analysis of the higher versions and other packages of
CPLDs. The device is compact, portable, easy to repair, simple, works
with both TTL and JEDEC standard CMOS levels.
The CPLDs can be checked and program individually in large
quantity to detect the failure before the assembly stage. This device
can also be used in other programmable as well as standard
nonprogrammable ICs.

WE CLAIMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved. We Claim

1. The Complex Programmable Logic Device meaning CPLD IC tester and programming PCB socket, comprising
- An interface socket for mounting CPLD,
- Arrangement for connecting atleast one power supply,
- An external controller &
- A suitable crystal

2. The system as per claim 1, wherein the said device works with both TTL and JEDEC standard CMOS levels.

3. The system as per claim 1, wherein programmable slew rate control, which sets the output slew rate to fast or slow.

4. The system as per claim 1, wherein Flexible clocking method is used with the help of synchronous clocks.

5. The system as per claim 1, wherein failure characteristics and the symptoms are easily monitored using external controller. ,TagSPECI:
As per Annexure-II