FIELD OF THE INVENTION
The present invention relates generally to electrical
circuits and more particularly relates to a differential
current mode off-chip buffer unit comprising transmitter
(driver)-receiver circuit in high speed wired communication
system.
The invention is also important in semi-conductor industry
for increasing rate of data communication through wired
link.
BACKGROUND AND THE PRIOR ART
In high speed wired communication, when signal transition
time becomes comparable or less than the interconnect
delay, interconnect medium behaves as a transmission line
.A number of problem exist when high-speed communication is
desired. As for example, a mismatch of the characteristic
impedance of the transmission line may lead to signal
reflection in the terminal. To address the problem of
undesirable signal reflection use of a match terminator (a
resistor equal to characteristic impedance of the
transmission line) at the receiving end is a common
practice. This introduces an extra overhead for system
level designer and also increases power dissipation.
A state of the art high-speed off-chip interconnect
architecture is shown in Fig.l. In this architecture, the
transmitter in integrated circuit (IC1) send signal in
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current mode through a pair of interconnects (or
differential mode cable) to the receiving integrated
circuit IC2. Normally, one type of data the transmitter
sources a current through one connection (say Out) and
sinks equal amount of current through the other connection
(OutB). For complementary data, the transmitter sinks
current through Out and sources current through OutB. The
transmitter current flow through the terminator resistors
Rt (a pair of series connected Rt' s with their middle node
connected at a terminating voltage Vt) which develops a
voltage drop across the two input nodes of the receiver Rx
in IC2. The terminator (or pair of terminators) should be
matched with characteristic impedance of the transmission
line (i.e. interconnect or cable) to avoid signal
reflection at the receiving end of the interconnect that
behaves like a transmission line for high frequency
transmission. Terminator can be internal or external to the
IC2.
US6590422 describes a low voltage differential signaling
(LVDS) drivers and analog-to-digital (ADC) systems which
facilitate easy alteration (e.g., replacement of a
selectable resistor R.sub.sel) of differential current
levels and differential voltages in response to altered
loads. In addition, these drivers and systems maintain
common-mode levels in the loads which are unaffected by
alterations in the loads and their associated differential
current and voltage levels. These features are realized
with feedback signals from high-resistance feedback
resistors that are coupled across LVDS circuit bridges. It
was not known from this prior art that current mode
receiver can be used.
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US6836149 discloses an electronic circuit includes a
selectively configurable differential signal interface and
a selection control input for selecting one of a plurality
of standard differential signal interfaces for
configuration of the differential signal interface. It was
not known from this prior art that current mode receiver
can be used.
US20060234650 describes a LVDS transceiver. It includes a
transmitter and a receiver, the transmitter having a first
terminal in signal communication with a transmission line,
a source resistance in signal communication with the first
terminal, a switch in signal communication with the source
resistance and in switchable signal communication from
ground or an input voltage, a voltage regulator in
switchable signal communication with the switch for
providing the input voltage to the switch, and a voltage
controller in signal communication between the first
terminal and the voltage regulator for controlling the
input voltage to provide a controlled voltage to a
receiver; and the receiver having an amplifier having a
first input, a first pad in signal communication with the
first input, a load resistance, and a second pad in signal
communication with the load resistance, where the first and
second pads are both in signal communication with one end
of a first transmission line. It was not known from this
prior art that current mode receiver can be used.
US6639434 discloses a low voltage differential signaling
driver is disclosed that is capable of supporting many
different LVDS standards or signal level requirements. The
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low voltage differential signaling driver has a
programmable offset voltage and a programmable differential
output voltage, which may be programmed independently. It
was not known from this prior art that current mode
receiver can be used.
US6288575 discloses structures and methods for high speed
signaling over single sided/ended current sense amplifiers
are provided. The present invention introduces hysteresis
within a pseudo-differential current sense amplifier and
provides it with adjustable thresholds for the detection of
valid signals coupled with the rejection of small noise
current transients or reflections and ringing when using
low impedance interconnections and/or current signaling.
The circuit provides a fast response time in a low power
CMOS environment, and conserves circuit design space by
allowing for single sided/ended sensing. This prior art is
used for intra IC (or chip) and is not for off chip
communication in applications where reflection problem
exists.
US5811984 describes a system that allows relatively small
current mode signals to be transmitted through a
transmission line and converted to output voltages large
enough for digital communication. This prior art is based
on single ended communication and it was not know from this
priori art differential current mode signals can be used
for high speed wired communication.
US6307401 teaches data communications by means a
differential receiver of a bus line having in-built voltage
offset. It has terminator without biasing voltage. This is
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based on voltage mode signaling. No current mode
communication was disclosed.
US6348817 teaches a current-steering integrated circuit
driver adapted for high speed data communications. The
driver offers, among other things, a high data
communication speed, a large common mode output voltage
range, avoidance of spike through current that increases
power consumption, improved switching speed using current-
steering techniques, and improved matching of steady-state
output current in the high logic state to that of the low
logic state, even with large output common mode voltage
swing. This is based on complementary current mode. No
differential mode was found in the prior art.
Thus there is a need to provide for a differential I/O
buffer unit in high speed wired communication system
without use of any extra overhead/terminator for
communication systems.
The present inventors has surprisingly found that by
matching the input impedance of current mode receiver with
typical characteristic impedance of transmission line of
wired communication, use of terminators for preventing
reflection in transmission line can be avoided and data
rate could be increased 1.5 to 5 times compared to the
technology prevailing in the state of the art. It is also
found that the simulated speed performance is about 50 to
60% more compared to the state of the art architecture.
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OBJECTS OF THE INVENTION
Accordingly, one object of the present invention is to
provide a differential I/O buffer unit in high speed wired
communication system.
Another object of the present invention is to eliminate use
of overhead terminators in the communication system.
Yet another object of the present invention is to provide
50-60% more simulated speed performance in the
communication system.
Yet another object of the present invention is to minimize
power dissipation in the system.
Yet another object of the present, invention is to increase
flexibility of integrating IC at board level.
Another object of the present invention is to reduce the
level of transmitting current for better signal integrity.
SUMMARY OF THE INVENTION
According to one aspect of the present invention there is
provided a differential I/O buffer unit in high speed wired
communication system, said unit comprising
transmitter means;
receiver means wherein said receiver means being adapted to
sense current and
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wherein receiver means comprises small signal differential
mode input impedance such that it matches the
characteristic impedance of transmission line.
These and other features and advantages will be more
clearly understood from the following detailed description
taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
Figure 1 illustrates the LVDS architecture of the State of
the art.
Figure 2 illustrates improved high speed off-chip
interconnect architecture of the present invention.
Figure 3 illustrates block diagram of off-chip interconnect
scheme of the present invention.
Figure 4 illustrates schematic level diagram of off-chip
interconnect scheme of the present invention.
Figures 5(a), 5(b) and 5(c) illustrate various possible
schematics of current mode off-chip transmitter of the
present invention.
Figure 6 illustrates schematic diagram of off-chip receiver
of the present invention.
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DETAILED DESCRIPTION OF THE ACCOMPANYING DRAWINGS
Figure 2 reflects top level changes in the interconnect
scheme of the present invention (w.r.t. the existing state
of the art interconnect) . It does not require any
terminator. The transmitter (Tx) in the present scheme is
operatively connected with the receiver (Rx) with an
impedance (Zo) in between. Receiver (Rx) senses the currents
(rather than voltage), which are essentially coming from
transmitter (Tx). Receiver (Rx) has small signal
differential mode input impedance so as to match with
characteristic impedance of the transmission line. Because
of this property the resistive terminator is not required
here. Additionally, it helps to reduce magnitude of the
current sent by the transmitter and hence, reduces power
dissipation and signal interference. Further, speed of
communication in current mode is higher than that in
voltage mode.
Because of receiver can sink/source current, it introduces
versatility in transmitter mode of work. The current mode
transmitter can be "source and sink" type (as discussed for
transmitter in the state of the art); "source and zero" and
"sink and zero". In "source and zero" type transmitter,
based on transmitting data it sources current into one of
the two conductors while it does not pass any current into
the other conductor. Though in the present invention
transmitter (Tx) as "source and zero" type is shown, also
from signal integrity point of view, "source and sink" can
also be used.
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Block diagram and a schematic level implementation of the
current mode transmitter and receiver and their connection
through differential interconnect is shown in figures 3 and
4 respectively.
Detail Schematics of three possible transmitters are shown
in figure 5. The circuit in figure 5(a) is "source and
zero" type transmitter. Depending on the input data at In
node one of the two transistors (Ml) and (M2) gets ON and
full current (Io) is sourced into one of the output nodes
{OutB) and (Out) . The circuit shown in figure 5(b) is "sink
and zero" type transmitter. Depending on its input data one
of the two transistors (M3) and (M4) gets ON and the full
current (Io) is sunk from one of the output nodes (OutB)
and (Out). A "sink and source" type transmitter is shown in
figure 5.c. Depending on the data at node (In) either M1-M4
or M2-M3 get ON and then, either (la) is source into (OutB)
and (lb) is sunk from (Out) or (la) is source into (Out)
and (lb) is sunk from (OutB).
Schematic detail of the proposed receiver is shown in
Figure 6. In this circuit Transistors Mia - Mib (for i =
1,..,5) are various matched pairs. With a constant bias
voltage (Vbiasl) transistors (M2a &M2b) works as current
sources. Transistors (Mia & Mlb) are common gate amplifiers
(with their gates connected to a constant voltage (Vbias2).
Received current signals are fed into the nodes (Rxin) and
(RxinB). Because of common gate amplifiers individual small
signal input impedance at nodes (Rxin & RxinB) w.r.t.
ground are low. Also, small signal input impedance between
nodes (Rxin & RxinB) i.e., small signal differential mode
input impedance, is low. Hence, this impedance is easy to
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meet. Diode connected (gate and drain nodes shorted)
transistors (M3a & M3b) forms the active load. For equal
input current at nodes (Rxin & RxinB), due to circuit
symmetry, voltages at nodes A and B are equal. However, for
different input currents at (Rxin & RxinB), the currents
flow through transistors (Mia & Mlb) are different which
makes voltage at A and B are different. This voltage
difference is then sensed by a comparator to generate
voltage signal at {Rxout)
While the components mentioned so far are essential parts
of the receiver, the remaining transistors M4a-M5b helps to
enhance the circuit performance. For instance, back-to-back
connected transistors (M4a & M4b) decrease small signal
input impedance of the receiver further lower and makes it
easier to match it with a typical characteristic impedance
of a transmission line. Otherwise, matching of impedance
only by Mla-Mlb pair may not be area economic (i.e., with
large area of Mla-Mlb).
On the other hand, M5a and M5b, with appropriate bias
(Vbias3) work as current source and they supply significant
fraction of currents through Mia (and optional M4a) and Mlb
(and optional M4b) respectively. So, the presence of these
two transistors decreases the required current flow through
M3a and M3b. This makes it possible to decrease their sizes
(i.e. their width/length ratio) and hence, to increase
small signal output impedance at nodes A and B. Increase of
the small signal impedance increases the voltage signal
strength at node A and B which makes the voltage comparator
circuit simple.
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Input current at Rxin and RxinB are not equal (based on
transmitter data one of the will be higher than the other
one) . So, the current through Mia (plus that through the
optional M4a) and Mlb (plus that through the optional M4b)
are not equal. And hence, based on transmitted data small
signal input impedance at one of these input nodes will be
higher than that of the other one. Matching of these
impedances individually with characteristic impedance of a
targeted transmission line is due to total input impedance
between the two receiver input nodes not changing much and
hence it can be easily matched with characteristic
impedance of the transmission line. Therefore differential
configuration makes impedance matching simpler.
This receiver can work with any of the above mentioned
three transmitters.
Advantages :
1. Removal terminator in High speed off-chip
communication by matching small signal input impedance
of the receiver with characteristic impedance of the
transmission line.
2. Reduce level of transmitting current and continue with
differential mode communication for better signal
integrity.
3. Increase in speed of communication (data rate) by
making the entire off-chip driver-receiver pair
working in current mode.
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4. Increase in flexibility of integrating IC at board
level.
5. Improving data communication rate 1.5 to 5 times
compared to the state of the art.
6. Simulated speed performance : The simulated speed
performance is 5Giga bit per second (increased by 50-
60% compared to the prior art) . Whereas an existing
state of the art equivalent architecture in the same
process technology provides a data rate upto of 3 Giga
bit per second.
7. Finally, potential to evolve a new high speed off-chip
signaling standard.
The invention has been described in a preferred form only
and many variations may be made in the invention which will
still be comprised within its spirit. The invention is not
limited to the details cited above. The components herein
described may be replaced by its technical equivalence and
yet the invention can be performed. The structure thus
conceived is susceptible of numerous modifications and
variations, all the details may furthermore be replaced
with elements having technical equivalence. In practice the
materials and dimensions may be any according to the
requirements, which will still be comprised within its true
spirit.
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WE CLAIM
1. A differential I/O buffer unit in high speed wired
communication system, said unit comprising
transmitter means;
receiver means wherein said receiver means being
adapted to sense current and
wherein receiver means comprises small signal
differential mode input impedance such that it matches
the characteristic impedance of transmission line.
2. A differential I/O buffer unit as claimed in claim 1
wherein the receiver means comprises common gate
amplifiers adapted to maintain small signal impedance
between nodes Rxin and RxinB.
3. A differential I/O buffer unit as claimed in claim 1
wherein the common gate amplifier comprises at least
two transistors.
4. A differential I/O buffer unit as claimed in claims 1
to 3 wherein the receiver means comprises active load
having at least two diode connected transistors.
5. A differential I/O buffer unit as claimed in claims 1
to 4 wherein the receiver means comprises at least two
back-to-back connected transistors adapted to decrease
small signal input impedance of the receiver so as to
match it with typical characteristic impedance of
transmission line.
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6. A differential I/O buffer unit as claimed in claims 1
to 5 wherein the receiver means further comprises
appropriately biased transistors working as current
source adapted to supply significant portion of
current through common gate amplifiers, optionally
through back-to-back transistors.
7. A differential I/O buffer unit as claimed in claim 1
wherein the transmitter means is "source and sink"
transmitter.
8. A differential I/O buffer unit as claimed in claim 1
wherein the transmitter means is optionally "source
and zero" transmitter.
9. A differential I/O buffer unit as claimed in claim 1
wherein the transmitter means is optionally "sink and
zero" transmitter.
10. A differential I/O buffer unit as claimed in any
preceding claims further comprises a comparator.
11. A differential I/O buffer unit as herein described and
illustrated with reference to the accompanying
figures.

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The present invention relates to a differential I/O buffer
unit in high speed wired communication system. The I/O
buffer unit comprises transmitter means (Tx) and receiver
means (Rx) adapted to sense current. The receiver means
comprises small signal differential mode input impedance
(Z0) such that it matches the characteristic impedance of
transmission line.