Claims:1. A device (100) for data acquisition, said device comprising:
one or more analogue to digital converter (ADCs) (102-1, 102-2) that convert received analogue data to digital data and transmit the digital data through an interface (104-1, 104-2);
a clock divider (106) generates a reference clock signal, SYSREF signal and core clock signal required by the interface, and supplies the required reference clock signal, core clock signal and SYSREF clock signal to a processor coupled to the device through one or more connectors (112-1, 112-2); and
one or more radio frequency (RF) synthesizers (110-1, 110-2) adapted to receive input reference clock signal from said clock divider (106) to generate sampling clock signal and SYSREF clock signal required by the one or more ADCs (102-1, 102-2) such that said one or more ADCs are phase synchronized.
2. The device as claimed in claim 1, wherein the interface (104-1, 104-2) is JESD protocol, wherein the one or more ADCs (102-1, 102-2) transmit the digital data in JESD204C mode and JESD204B mode, wherein the device (100) offers instantaneous bandwidth of 1.5GHz in JESD204C mode and 2GHz in JESD204B mode.
3. The device as claimed in claim 1, wherein the device (100) performs high speed data processing with data rates up to 10.56Gbps per lane at 3.2Gsps sampling rate in JESD204C mode and 9.6Gbps per lane at 4.8Gsps sampling rate in JESD204B mode.
4. The device as claimed in claim 1, wherein the device (100) operable in a customized compact form factor using the one or connectors (112-1, 112-2) of size less than or equal to 140mm x 84mm, wherein the one or connectors are FMC+ connectors.
5. The device as claimed in claim 1, wherein the device (100) performs implementation of clock synchronization in real-time between the corresponding SYSREFs and sampling clocks with skew of less than 30ps generated from the one or more RF synthesizers (110-1, 110-2).
6. The device as claimed in claim 1, wherein the device (100) is a multi-channel data acquisition card, wherein the device reduces channel to channel mismatch among multiple channels and performs calibration feature for adoption of self-test.
7. The device as claimed in claim 6, wherein the device (100) accepts external wideband signal generated with the specified step size for self-test.
8. The device as claimed in claim 6, wherein the device (100) accepts external wideband signal generated with the distribution of signal through multi-channels for monitoring of health as a part of self-test.
, Description:TECHNICAL FIELD
[0001] The present disclosure relates, in general, to an electronic warfare system, and more specifically, relates to a data acquisition card for electronic warfare applications.

BACKGROUND
[0002] In electronic support/electronic signals intelligence (ELINT) systems of electronic warfare, measurement of the emitter parameters along with its direction is critical for the classification of emitters. Also, a higher probability of intercept in a dense electromagnetic (EM) environment gives an edge on the battlefield. Wider the bandwidth more the data to be processed hence faster is the processing required for real-time measurement.
[0003] A few existing technologies in the field of electronic warfare systems include dual-channel ADC/DAC board card based on FMC, four-channel FMC acquisition daughter card and multi-channel analogue-to-digital conversion system, these existing technologies used dual-channel ADCs for data conversion, however, the digital data transmission was through low-voltage differential signaling (LVDS) whose data rate is lower as compared to the JESD protocol. With the introduction of the JESD protocol faster rate of transmission can be made possible along with the reduction in the number of lines required for the transmission within the hardware of electronic support measures (ESM)/ELINT receivers. This reduced the routing space, however, led to a more complex clocking and data synchronization mechanism.
[0004] There is a therefore a need in the art to address the above-mentioned limitations and other disadvantages by providing a data acquisition card that operates at a high data rate employing an interface of high-speed data transmission standard in a compact form factor using dual FMC+ connectors for electronic warfare applications.

OBJECTS OF THE PRESENT DISCLOSURE
[0005] An object of the present disclosure relates, in general, to an electronic warfare system, and more specifically, relates to a data acquisition card for electronic warfare applications.
[0006] Another object of the present disclosure is to provide a device that provides ADCs operating in dual channel mode to receive clocks from two RF synthesizers having the corresponding sampling and SYSREF clocks length matched to achieve phase synchronization.
[0007] Another object of the present disclosure is to provide a device that is capable to operate at lane rates of 10.56Gbps with 3.2Gsps sampling rate employing JESD204C protocol and at 9.6Gbps with sampling rate of 4.8Gsps when employing JESD204B protocol catering in a compact form factor using dual FMC+ connectors.
[0008] Another object of the present disclosure is to provide a device that performs efficient clocking and data synchronization.
[0009] Another object of the present disclosure is to provide a device that reduces crosstalk and power consumption.
[0010] Yet another object of the present disclosure is to provide a device that enables IBW up to 2GHz when operated in JESD2004B mode and 1.5GHz when operated in JESD204C mode.

SUMMARY
[0011] The present disclosure relates, in general, to an electronic warfare system, and more specifically, relates to a data acquisition card for electronic warfare applications.
[0012] In an aspect, the present disclosure relates to a device for data acquisition, the device comprising one or more analogue to digital converter (ADCs) that convert received analogue data to digital data and transmit the digital data through an interface, a clock divider generates a reference clock signal, SYSREF signal and core clock signal required by the interface, and supplies the required reference clock signal, core clock signal and SYSREF clock signal to a processor coupled to the device through one or more connectors and one or more RF synthesizers adapted to receive input reference clock signal from the clock divider to generate sampling clock signal and SYSREF clock signal required by the one or more ADCs such that the one or more ADCs are phase synchronized.
[0013] According to an embodiment, the interface can be JESD protocol, where the one or more ADCs transmit the digital data in JESD204C mode and JESD204B mode, wherein the device can offer instantaneous bandwidth of 1.5GHz in JESD204C mode and 2GHz in JESD204B mode.
[0014] According to an embodiment, the device performs high speed data processing with data rates up to 10.56Gbps per lane at 3.2Gsps sampling rate in JESD204C mode and 9.6Gbps per lane at 4.8Gsps sampling rate in JESD204B mode.
[0015] According to an embodiment, the device operable in a customized compact form factor using one or connectors of size less than or equal to 140mm x 84mm, where the one or connectors are FMC+ connectors.
[0016] According to an embodiment, the device performs implementation of clock synchronization in real time between the corresponding SYSREFs and sampling clocks.
[0017] According to an embodiment, the device can be multi-channel data acquisition card, wherein the device reduces channel to channel mismatch among multiple channels and performs calibration feature for adoption of self-test.
[0018] According to an embodiment, the device accepts external wideband signal generated with the specified step size for self-test.
[0019] According to an embodiment, the device accepts external wideband signal generated with the distribution of signal through multi-channels for monitoring of health as a part of self-test.
[0020] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The following drawings form part of the present specification and are included to further illustrate aspects of the present disclosure. The disclosure may be better understood by reference to the drawings in combination with the detailed description of the specific embodiments presented herein.
[0022] FIG. 1 illustrates an exemplary functional component of 4-channel data acquisition card, in accordance with an embodiment of the present disclosure.
[0023] FIGs. 2A to 2C illustrate exemplary layout density and placement density of the 4-channel data acquisition card, in accordance with an embodiment of the present disclosure.
[0024] FIGs. 3A to 3B illustrate graphical view depicting the IBW =1.5GHz with a sampling rate of 3.2Gsps when operated in JESD204C format, in accordance with an embodiment of the present disclosure.
[0025] FIGs. 4A to 4B illustrate graphical view depicting the IBW = 2GHz with a sampling rate of 4.8Gsps when operated in JESD204B format, in accordance with an embodiment of the present disclosure.
[0026] FIGs. 5A to 5B illustrates graphical view of phase synchronized SYSREF outputs and phase synchronized sampling clocks generated by two RF synthesizers, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0027] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0028] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0029] The present disclosure relates, in general, to an electronic warfare system, and more specifically, relates to a data acquisition card for electronic warfare applications. The data acquisition card forms a critical aspect of electronic support (ES) and electronic intelligence (ELINT) systems of electronic warfare (EW) systems. The functions of the EW system are threat detection and area surveillance to determine the identity of surrounding emitters. The data acquisition card is used in the extraction of phase information of the emitter by employing the BaseLine Interferometry (BLI) technique.
[0030] The BLI as used herein refers to an interferometry technique that enhances angular resolution in the observation of radio signals from ground based or air-borne emitters. According to this technique, the direction of arrival is computed based on the difference in phase angles received among the 4 elements of the BLI array, which at separated by a known ratio. Therefore, it is of prime importance that the data acquisition card has phases among the clocks synchronized.
[0031] The device of the present disclosure enables to overcome the limitation of the prior art by handling data rates up to 10.56Gbps per lane at 3.2Gsps sampling rate by which instantaneous bandwidth (IBW) of 1.5GHz can be achieved when operated in JESD204C mode and data rates up to 9.6Gbps per lane at 4.8Gsps sampling rate giving 2GHz IBW when operated in JESD204B mode. The description of terms and features related to the present disclosure shall be clear from the embodiments that are illustrated and described; however, the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents of the embodiments are possible within the scope of the present disclosure. Additionally, the invention can include other embodiments that are within the scope of the claims but are not described in detail with respect to the following description.
[0032] FIG. 1 illustrates an exemplary functional component of 4-channel data acquisition card, in accordance with an embodiment of the present disclosure.
[0033] Referring to FIG. 1, data acquisition card 100 (also referred to as a device 100, herein) can be configured to acquire data for electronic warfare applications. The device 100 form a critical aspect of electronic support (ES) and electronic intelligence (ELINT) systems of electronic warfare (EW) systems. The device 100 can include one or more ADCs (102-1, 102-2) capable to transfer digital data through an interface (104-1, 104-2) of high-speed data transmission standards. In an exemplary embodiment, the interface (104-1, 104-2) can be JESD protocol, where the one or more ADCs (102-1, 102-2) transmit digital data in JESD204B mode or JESD204C mode. The device 100 can include a clock divider 106, programmable crystal oscillator 108, one or more RF synthesizers (110-1, 110-2), one or more connectors (112-1, 112-2) and buffer 114. The one or more connectors (112-1, 112-2) can be field-programmable gate array (FPGA) Mezzanine Card (FMC+) connectors.
[0034] The data acquisition card 100 as presented in the example can be multi-channel data acquisition card. In an exemplary embodiment, multi-channel data acquisition card can be 4-channel data acquisition card. As can be appreciated, the present disclosure may not be limited to this configuration but may be extended to other configurations. The 4-channel data acquisition card 100 is used in the extraction of phase information of emitter by employing BaseLine Interferometry (BLI) technique. According to this technique, the direction of arrival is computed based on the difference in phase angles received among the 4 elements of the BLI array, which at separated by a known ratio. Therefore, it is of prime importance that the data acquisition card 100 has phases among the clocks synchronized.
[0035] In an exemplary embodiment, wideband high-speed JESD204B and JESD204C compliant 4-channel data acquisition card 100 can include one or more 12-bit ADCs capable of operating in JESD204B and JESD204C mode, where the one or more ADCs (102-1, 102-2) can include a first ADC 102-1 and a second ADC 102-2. The device 100 can be in a customized compact form factor using dual FMC+ connectors (112-1, 112-2) of size less than or equal to 140mm x 84mm.
[0036] Realization of JESD204B and JESD204C in the compact form factor using dual FMC+ connectors supporting JESD lane speed up to 9.6Gbps and 10.56Gbps with a maximum sampling rate up to 4.8Gsps and 3.2Gsps for JESD204B and JESD204C respectively. The interconnection can be achieved through FMC+ connectors (112-1, 112-2) capable of handling 24 pairs of transceivers. Each ADC operates in dual channel mode and has 8 lanes associated with a single channel. Therefore, the two FMC+ connectors together handle up to 32 transceiver pairs.
[0037] In electronic warfare, it is necessary that the receivers can scan wider frequency bands with a higher sensitivity level. The device 100 can accept radio frequency (RF)/intermediate frequency (IF) input frequency up to 6 GHz. The four channels are phase and length matched in analogue and digital domains. The filtered analogue input is fed into the board through 4 micro-miniature coaxial (MMCX) connectors passing through a low attenuation wide range balun accepting frequency inputs from 500 kHz to 6 GHz
[0038] The first ADC 102-1 and the second ADC 102-2 can convert the analogue data to digital data and can transmit the digital data to the interface in JESD204B or JESD204C format. The high speed first ADC 102-1 and the second ADC 102-2 can be operated in dual channel mode. As per the JESD204B/C requirement, the clocks are to be source synchronous. A single ultra-low noise clock jitter cleaner with dual loop phase lock loop (PLLs) 106 (also referred to as clock divider, 106 herein) configured for the generation of source synchronous clocks as required by JESD protocol.
[0039] The clock divider 106 is used to generate a reference clock signal (REFCLK), SYSREF signal and core clock signal (CORECLK) required by the JESD standard for which the input reference is provided by the programmable crystal oscillator 108. The PLL supplies the required reference clock signal, core clock signal and SYSREF clock signal to a processor i.e., FPGA (not shown) coupled to the device 100 via FMC+ connectors (112-1, 112-2). The one or more wideband RF synthesizers (110-1, 110-2) can include a first RF synthesizer 110-1 and the second RF synthesizer 110-2 with phase synchronization are used in the generation of sampling clock signal and SYSREF clock signal required by the first ADC 102-1 and the second ADC 102-2.
[0040] The clock divider 106 provides the input reference clock signal required by the first RF synthesizer 110-1 and the second RF synthesizer 110-2 to generate the sampling clock signal and SYSREF signal required by the first ADC 102-1 and the second ADC 102-2. The first RF synthesizer 110-1 and the second RF synthesizer 110-2 output the sampling clock signal and SYSREF clock signal required by the first ADC 102-1 and the second ADC 102-2 such that the first ADC 102-1 and the second ADC 102-2 are phase synchronized.
[0041] The programmable clock divider 106 provides the flexibility of changing the output clock frequencies as well as their data formats like low-voltage differential signaling (LVDS), Low-voltage positive/pseudo emitter-coupled logic (LVPECL), complementary metal–oxide–semiconductor (CMOS) and the likes and gives the possibility to disable the unused clocks so that crosstalk and power consumption can be reduced. The first ADC 102-1 and the second ADC 102-2 are made phase synchronous by providing the reference clock signal to the first RF synthesizer 110-1 and the second RF synthesizer 110-2 by a common source through the buffer 114 and ensuring the length matching between the two sets of the clock. A maximum of 36W power to the module is supplied via the FMC+ connectors (112-1, 112-2). Three power rails 3.3V, 1.9V and 1.1V are generated from the main input source of +12V.
[0042] The device 100 capable of wideband, offering instantaneous bandwidth of 1.5GHz and 2GHz in JESD204C and JESD204B format respectively. The device 100 can be capable of high-speed data processing with lane rates up to 10.56Gbps with a 3.2Gsps sampling rate and 9.6Gbps with a 4.8Gsps sampling rate in JESD204C and JESD204B respectively.
[0043] The maximum lane rate that have achieved is 10.56Gbps with 3.2Gsps sampling rate by by-passing all the digital down conversion (DDCs) in JMODE = 31 (JESD204C) format.
Data rate =
= (3.2Gsps*12*(66/64)*(64/60)/4)
= 10.56Gbps
[0044] The maximum lane rate that have achieved is 9.6Gbps with 4.8Gsps sampling rate by by-passing all the DDCs in JMODE = 3 (JESD204B) format.
= (4.8Gsps*12*(10/8)*(64/60)/8)
= 9.6Gbps
[0045] The device 100 can perform the implementation of clock synchronization in real-time between the SYSREF signals with a skew of less than 30ps generated from the first RF synthesizer 110-1 and the second RF synthesizer 110-2. The device 100 can accept external wideband signal generated with the specified step size for self-test and accept external wideband signal generated with the distribution of signal through multi-channels for monitoring of health as a part of self-test.
[0046] The embodiments of the present disclosure described above provide several advantages. The device 100 can reduce channel to channel mismatch among multiple channels and corresponding digital hardware circuits. The device 100 can be capable of calibration feature for the adoption of self-test. The ADCs operate in dual channel mode to receive clocks from two RF synthesizers having sampling and SYSREF clocks length matched to achieve phase synchronization. The device 100 performs efficient clocking and data synchronization.
[0047] FIGs. 2A to 2C illustrate exemplary layout 200 density and placement density of the 4-channel data acquisition card, in accordance with an embodiment of the present disclosure. FIG. 2A depicts schematic view of the 4-channel data acquisition card, FIG. 2B depicts the top view of the 4-channel data acquisition card and FIG. 2C depicts the bottom view of the 4-channel data acquisition card.
[0048] FIGs. 3A to 3B illustrate graphical view 300 depicting the IBW =1.5GHz with a sampling rate of 3.2Gsps when operated in JESD204C format, in accordance with an embodiment of the present disclosure. FIG. 3A shows the data captured in JESD204C format at one channel at power level close to ADC full power at 3.15GHz. FIG. 3B shows data captured in JESD204C format at one channel at power level close to ADC full power at 1.65GHz.
[0049] FIGs. 4A to 4B illustrate graphical view 400 depicting the IBW = 2GHz with a sampling rate of 4.8Gsps when operated in JESD204B format, in accordance with an embodiment of the present disclosure. FIG. 4A shows data captured in JESD204B format at one channel at power level close to ADC full power at 2.5GHz. FIG. 4B shows data captured in JESD204B format at one channel at power level close to ADC full power at 4.5GHz.
[0050] FIG. 5A to 5B illustrates graphical view 500 of phase synchronized SYSREF outputs and phase synchronized sampling clocks generated by two RF synthesizers, in accordance with an embodiment of the present disclosure. FIG. 5A depicts graphical view of phase synchronized SYSREF outputs and FIG. 5B depicts graphical view of phase synchronized sampling clocks. As shown in FIG. 5A and 5B the ADCs (102-1, 102-2) are phase synchronized as they are receiving the phase synchronous SYSREF signals and sampling clock signal generated by the one or more RF synthesizers (110-1, 110-2).
[0051] It will be apparent to those skilled in the art that the device 100 of the disclosure may be provided using some or all of the mentioned features and components without departing from the scope of the present disclosure. While various embodiments of the present disclosure have been illustrated and described herein, it will be clear that the disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the disclosure, as described in the claims.

ADVANTAGES OF THE PRESENT DISCLOSURE
[0052] The present disclosure provides a device that provides ADCs operating in dual channel mode to receive clocks from two RF synthesizers having the corresponding sampling and SYSREF clocks length matched to achieve phase synchronization.
[0053] The present disclosure provides a device that is capable to operate at lane rates of 10.56Gbps with 3.2Gsps sampling rate employing JESD204C protocol and at 9.6Gbps with sampling rate of 4.8Gsps when employing JESD204B protocol catering in a compact form factor using dual FMC+ connectors.
[0054] The present disclosure provides a device that performs efficient clocking and data synchronization.
[0055] The present disclosure provides a device that reduces crosstalk and power consumption.
[0056] The present disclosure provides a device that enables IBW up to 2GHz when operated in JESD2004B mode and 1.5GHz when operated in JESD204C mode.