FIELD OF THE INVENTION
This invention relates to Data Acquisition Processor Module with multiple
Communication Interfaces for use in Flight Data Recorders and, more particularly, for receiving,
processing & communicating with other modues of flight data recorder signals in a variety of
signal forms like Analog, Synchro, Discrete, Frequency, RS422, Mil STD-1553B & Ratio metric
(OAT Signals) & Audio and sending to Protected Memory Module (PMM).
BACKGROUND OF THE INVENTION
Flight data recorders are monitoring and recording instruments, carried aboard an
aircraft, which systematically monitor and store the instantaneous values of various aircraft
parameters. Early recorders were analog electromechanical devices which periodically marked,
in analog form, the value of a given airplane parameter on a moving wire or other permanent
storage medium. The time of occurrence of the parameter was also suitably scribed into the
medium opposite the mark for the sensed parameter. Subsequently, digital flight data recorders
have been developed which operate by converting each analog aircraft parameter into a
corresponding digital signal, and storing the digital signals on a permanent storage medium
such as magnetic tape.
The mandated flight parameters, which must be continuously recorded during the
operational flight profile of the aircraft, include a minimum number of functional parameters
considered essential for reconstructing the aircraft flight profile in post accident investigation
proceedings. Present recording requirements specify a minimum 25 hour interval.
The data recording is made on a Flight Data Recorder (FDR) designed to withstand a
crash environment. These FDRs are either of two types: (i) electromechanical or (ii) solid-state
memory. At present the electromechanical recorders represent the majority used on both civil
and military aircraft. They include both analog signal, metal foil and digital signal, magnetic tape.
The digital signal recorders (solid-state or electromechanical) represent the contemporary
standard for all new aircraft. This result 20 from the development of high accuracy, fast
response engine digital signal sensors, which have stimulated requirements for improved flight
data monitoring systems. The digital recording system signal formats are defined by ARINC
717, which replaces the ARINC 573/717 definitions of analog signal formats for implementing
the performance specifications for historical recording of the flight parameters.
The recording system input data is, as is the remaining non recorded flight data, sensed
within the 25 various operating systems of the aircraft, acquired and conditioned in a flight data
acquisition unit (FDAU), and presented to the flight data recorder (FDR) for preserved recording.
The FDAU is the collecting source for the flight data recorder as well as the other utilization
equipment (e.g. airborne integrated data system, AIDS). The FDR cannot function without the
FDAU. The FDAU, in turn, receives the flight data from the multifarious sensor signal groups of
the aircraft, including the Air Data Computer, 30 Flight Management System, etc. As a
consequence overall recording system integrity is dependent on the data sensors and sensor
signal conditioning circuitry, the data acquisition unit, the flight data recorder, and the aircraft
interconnecting wiring.
The extended nature of the components involved make reliability of the system a major
concern. Prior art recording systems include built-in test equipment (BITE) for the FDAU and
FDR, but not the sensors. 35 The sensors are not subject to BITE testing due to practical
constraints, e.g. nature of the sensor and/or the BITE requirements, or the existence of different
manufacturer and suppliers of the equipment; manufacturers of the data acquisition and
recorder hardware are not those which provide the sensors. As a consequence the sensor
interface is untested during flight.
To assure recording system integrity the airlines are required by regulatory agency to
periodically certify operation of the flight data recording system on each aircraft. This requires
that the FDR be removed from the aircraft and tested on a scheduled basis; typically every
3,000 hours. The data stored in the FDR is read from the recorder and transcribed to determine
that all elements of the system are functional. The FDR must then be routed through the airline
maintenance cycle prior to being returned to service. This not only represents high cost, but the
method of test (off-line) still allows the risk of 45 overlooking overall system integrity, e.g.
underestimating the significance or lack of significance of any given units of recorded data.
The flight data recording system includes a data recording unit (DRU) and a flight data
acquisition unit (FDAU) having a signal processor and nonvolatile memory for storing signals
representative of a deterministic flight mode algorithm which defines a generic aircraft flight
profile by preselected modes, each mode defining a flight profile operating station, the
deterministic flight mode algorithm defining the nominal values of some number of sensed flight
data parameters in terms of the 60 sensed values of some number of the remaining other
sensed flight parameters. At each such station, the signal processor comparing the actual
sensed mandatory flight parameter value with the corresponding determined value to establish
sensor accuracy.
The flight data recording system of the present invention provides for use of a
deterministic flight mode algorithm to perform the integrity check on the mandatory recorded
parameters including 65 measuring the accuracy of the sensed parameters to be recorded, and
the actuality of the flight data the selected aircraft flight parameters. The recording system flight
mode algorithm provides ARINC 717 systems operational testing. As such, the need for periodic
transcription of the FDR data to verify recorded sensed data accuracy is dramatically reduced.
SUMMARY OF PRESENT INVENTION
FDR can operate in three modes – Record, Replay & Program. At FDR start-up (Power
‘ON’) time, software running on the CPU Module initialises – registers, memories and interfaces.
CPU Module senses the state of function mode pins which are available on aircraft interface
connector and decides in which mode FDR has to enter. Default mode for FDR is record mode.
Once the power is ‘ON’ and FDR is in record mode, it starts data acquisition from Analog
Modules, Discrete Module, Audio Module, Frequency Module, FCS data from RS422 at 19.2
kbps baud rate & MIL-1553B data, converts them into frames as per data frame format/layout
and transmits them on RS 422 for telemetry at 115.2 kbps baud rate, but these frames are not
written into PMM by CPU Module till recording condition is met.
The activities of CPU Module have been scheduled / configured such that it finishes all
its activities in one second which is accomplished by using QUICC’s internal RISC timer and
keep on repeating the same for ever till the system is ‘ON’. The CPU Module performs activities
like – updating NVRAM contents, performing CBIT, fault indication – if any, data acquisition from
all other modules, MIL-1553B and FCS data. Then, it makes direct parameter frame, Audio
frame, MIL-1553B data frame, FCS data frame, stores these frames into PMM, transmitting the
frame on RS422 for telemetry and transmitting message words on MIL-1553B bus to OAC.
CPU Module has also been facilitated with one more feature, which is FDR Fault
Indication - whenever any test fails during PBIT or CBIT, CPU module has capability to drive the
dolls eye in the aircraft’s maintenance panel (external to FDR) to indicate fault in FDR.
When ground equipment is connected to FDR for downloading sortie data, the interface
between ground support equipment & memory module is provided by the CPU Module through
10Base-T Ethernet.
The present invention helps the user to verify the health of the electronic modules by
conducting self testing and also test the health of the aircraft other sub systems by acquiring
real time data from aircraft sub systems and comparing with the predefined standard values.
These provide an edge to the user by providing instant feedback and live reporting of parameter
details and thereby reducing downtime of the aircraft.
Features of the Module:
• Motorola micro-controller @ 25 MHz
• Onboard Crystal Oscillators – 25MHz, 20MHz, 16MHz, 1.8432MHz
• Flash EPROM
• SRAM
• NVRAM
• One RS232 channel
• Four RS-422 channels
• One Ethernet interface to download sortie data
• MIL-STD-1553B interface (Dual Redundant Communication Bus)
• 16-bit Bus expansion to communicate with other modules
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention become more apparent and
descriptive in the description when considered together with figures/flow charts presented:
Figure 1: is a Block Diagram of Data Acquisition Processor Module with multiple
Communication Interfaces.
Figure 2: is a Block Diagram of Fail/Safe Biasing for UART(RS422) Interface
Figure 3: is a Block Diagram of Ethernet Interface with Processor
Figure 4: is a Block Diagram of ACE/Mini-ACE Interface to MIL-STD-1553B
Figure 5: is a Block Diagram of 16-Bit Address/Data Lines Bus Expansion
DETAILED DESCRIPTION
The Quad Integrated Communication Controller (QUICC) is a versatile one chip
integrated microprocessor and peripheral combination. It operates at 25 MHz clock frequency.
QUICC excels in communication activities. QUICC can be described as a next generation micro
controller, with high performance in all areas of device operation, increased flexibility and high
integration. The term ‘quad’ comes from the fact that there are four serial communication
controllers (SCCs) on the device. However, there are actually sever serial communication
channels - four serial communication controllers (SCCs), two serial management controllers
(SMCs) and one serial peripheral interface (SPI).
The followings are the key features of QUICC:
• CPU32+ Processor with 4.5 MIPS at 25MHz
• Up to 32-Bit Data Bus with Dynamic Bus Sizing for 8 and 16 Bits
• Up to 32 address Lines - At Least 28 Always Available
• Four 16-Bit or Two 32-Bit General-Purpose Timers
• System Integration Module
• Seven External Interrupt Lines, 12 Port Pins with Interrupt Capability, 16
Internal Interrupt Sources, Programmable Priority between SCCs,
Programmable Highest Priority Request
• Communication Processor Module (CPM)
• Four Baud Rate Generators – Can be Connected to any SCC or SMC, Allow
Changes during Operation, Auto-baud Support Option
• Four SCCs – Ethernet Option on SCC1 (Full 10-Mbps Support), UART
• Two SMCs – UART
• One SPI – Supports Master and Slave Modes
• Parallel Interface Ports (Port-A, Port-B & Port-C)
ASYNCHRONOUS SERIAL PORT:
The CPM (Communication Processor Module) contains features that allow the QUICC to
excel in communication and control applications. The communication Processor (CP) of QUICC
provides four SCCs and two SMCs having in-built UARTs to support asynchronous serial
communication. An external crystal oscillator of 1.8432 MHz has been used at CLK6 input of
QUIICC to set the required baud rates. However, internal system clock may also be used to set
the baud rates. The following communication ports have been configured for UART:
Resource
Name
Communication Port
Configured As Description
SCC2 UART RS232 Interface CH #1 (Software upload)
SCC3 UART RS422 Interface CH #3 (Spare)
SCC4 UART RS422 Interface CH #4 (Spare)
SMC1 UART RS422 Interface CH #1 (FCS)
SMC2 UART RS422 Interface CH #2 (Telemetry)
These serial communication channels have been interfaced to transmission line with
help of standard driver/receiver ICs, which takes care of physical layer signalling. The standard
driver/receiver IC for RS232 used for interface translation – converting simple TTL-NRZ signal
to RS232 signal specifications. Similarly, the standard driver IC for RS422– a quad high speed
differential line driver designed to provide uni polar differential drive to twisted-pair or parallelwire
transmission line and meeting RS422 standard requirements. This device has a power
up/down protection circuitry which keeps the output in Hi-Z state during power up or down
preventing erroneous glitches on the transmission lines. The standard receiver IC for RS422 – a
quad differential line receiver designed to meet the RS422 standard requirements for balanced
and unbalanced digital data transmission. At the input of UART, a failsafe biasing has been
used, where the presence of pull-up & pull-down resistors guarantees the receiver to switch to
logic high state regardless of whether the bus is open or idle.
10BASE-T ETEHRNET INTERFACE:
QUICC allows Ethernet operation on any of the four SCCs, but full 10 Mbps Ethernet
support is available only of SCC1. The QUICC Ethernet controller requires an external serial
interface adaptor (SIA) and transceiver function to complete the interface to the media. To full-fill
the requirement of an external serial interface adaptor (SIA) and transceiver, has been used,
which is designed for IEEE 802.3 physical layer applications. It provides all the active circuitry
for interfacing most standard 802.3 controllers. It requires a clock of 20 MHz for its operation.
The Ethernet device offers connectivity solution by driving 10Base-T twisted-pair cable, with
only a simple isolation transformer. The QUICC + Ethernet device + transformer solution
provides a direct connection to twisted-pair (10Base-T). Ethernet device provides a glue less
interface to the QUICC, Manchester encoding and decoding, reverse 10Base-T polarity
detection and correction, a low-power mode, transmit pulse shaping, receiver squelch, link
integrity test and jabber control. Although the QUICC contains DPLLs that allow Manchester
encoding and decoding, but these DPLLs are not designed for Ethernet rates. Once the MODE
bits of SCC1 GSMR select the Ethernet protocol, the QUICC bypasses the on-chip DPLLs and
uses the SIA on the Ethernet device. 10Base-T Ethernet interface is being used for high speed
data download form PMM. The Ethernet key features are listed below:
• Performs MAC Layer Functions of Ethernet and IEEE 802.3
• Performs Framing Functions
• Full Collision Support
• Receives Back-to-Back Frames
• Detection of Receive Frames That Are Too Long
• Internal and External Loop back Modes
• Error Counters – CRC Errors, Alignment Errors and Discarded Frames
The interfacing among QUICC, Ethernet Device, and Transformer is shown in Figure: 3.
MIL-1553B INTERFACE:
The CPU Module also has a MIL-STD-1553B bus interface, which has been provided by
DDC’s Mini-ACE Plus device. Mini-ACE Plus integrates dual 5V (low-power) transceivers,
encoder/decoders, BC/RT/MT multi-protocol logic, memory management and interrupt logic,
processor interface logic, 64K x 16-Bit of shared SRAM. It also contains internal address latches
and bidirectional buffers to provide a direct interface to QUICC bus. For FDR application, Mini-
ACE Plus device has been configured for RT mode. For each transmit, receive, or broadcast
sub-address, either a single-message data block, a double buffered data word blocks, or a
variable sized circular buffer may be allocated for data storage. The circular buffer feature can
greatly reduces the burden on QUICC for bulk data transfer. End-of-message interrupts may be
enabled either globally, following error message, on a transmit/receive/broadcast sub-address
or when any particular transmit/receive/broadcast sub-address circular buffer reaches its lower
boundary. An interrupt status register allows the host processor to determine the cause of all
interrupts by means of a single read operation. All address mapping of Mini-ACE Plus is word
oriented, rather than byte oriented. For interfacing QUICC to Mini-ACE Plus, the QUICC’s signal
should be connected to Mini-ACE Plus. Mini-ACE Plus requires 16 MHz clock for its operation.
The interface between Mini-ACE Plus and MIL-STD-1553 bus can be of two types depending on
stub length:
• Direct (Short Stub) Coupling – When stub length is up to 1 ft (max)
• Transformer (Long Stub) Coupling – When stub length is up to 20 ft (max)
Here, Transformer (Long Stub) Coupling has been used as stub length is exceeding 1
feet limit. For both types of coupling configuration, the transformer that interfaces directly to
Mini-ACE Plus is the isolation transformer. Whereas the transformer that interfaces the stub to
the MIL-STD-1553 bus is the coupling transformer. The turn’s ratio of the isolation transformer
varies depending upon the specified peak-to-peak output voltage at the output terminals of Mini-
ACE Plus. For transformer coupled applications with Mini-ACE Plus, isolation transformer has
been used having 1:1.79 turn’s ratio.
BUS EXPANSION:
The CPU Module uses 16-Bit data and 16-Bit address buses along with required control
signals to communicate with other modules. The data, address and control bus expansion to
other modules has been done using buffer – A fast CMOS 16-bit bidirectional transceiver. The
16-Bit data bus, 16-Bit address bus and control signals expansion is shown in figure: 5.

WE CLAIMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved. The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Data Acquisition Processor Module with multiple Communication Interfaces is for acquisition & processing the actual sensed values of flight parameters from a plurality of aircraft sensors at different flight modes of the aircraft flight profile, comprising:
Data acquisition means, having signal processing means for providing said signal representations to said flight data recording means, and including signal memory means for storing signals; said data acquisition means providing operational self testing of the flight data system and aircraft sensors using said signal processing means, and using test program means stored in said signal memory means and representing the deterministic flight mode algorithm indicative of optimum values of selected flight parameters at different flight modes of the aircraft flight profile, said processing means comparing the sensed signal value of each selected flight parameter with the related optimum signal value of said program means for the same flight mode and providing a test failure signal to said signal memory means in response to each difference signal magnitude there between.

2. The module of claim 1 wherein said signal memory means stores said test failure signals in a nonvolatile medium.

3. The module of claim 1 or 2, wherein said signal processing means in response to each test failure signal, compares the failed sensed flight parameter signal value of a present flight mode with the recorded sensed signal value of the same flight parameter in a preceding flight mode to provide a sensor test failure signal in response to the presence of substantially equal values for the same sensed parameter in succeeding flight modes.

4. The module of any one of claims 1 to 3 wherein said program means deterministic flight mode algorithm indicates said optimum values for each selected flight parameter in each flight mode of the aircraft in dependence on the relationship of the selected flight parameter to other flight parameters having known values in the same flight mode.

5. The module of claim 4, wherein said optimum values for each selected flight parameter are dependent on other flight parameters having known values which are independent of the related selected flight parameter in the same flight mode.

6. Data Acquisition Processor Module with multiple Communication Interfaces as claimed in any of the preceding claims wherein a dedicated watchdog is used and it has to be triggered periodically by software to avoid occurring of Watchdog Timeout event.

7. Data Acquisition Processor Module with multiple Communication Interfaces as claimed in any of the preceding claims wherein a standard driver/receiver IC for RS232 used for interface translation – converting simple TTL-NRZ signal to RS232 signal specifications. Similarly, the standard driver IC for RS422– a quad high speed differential line driver designed to provide uni polar differential drive to twisted-pair or parallel-wire transmission line and meeting RS422 standard requirements.

8. Data Acquisition Processor Module with multiple Communication Interfaces as claimed in any of the preceding claims wherein uses 16-Bit data and 16-Bit address buses along with required control signals to communicate with other modules. The data, address and control bus expansion to other modules has been done using buffer – A fast CMOS 16-bit bidirectional transceiver.

9. Data Acquisition Processor Module with multiple Communication Interfaces as claimed in any of the preceding claims wherein a mini ACE 1553-B RT device is used to support communication over the MIL-STD 1553-B data bus interconnects. The RT address lines are accessible externally, so that the address can be easily configured.

10. Data Acquisition Processor Module with multiple Communication Interfaces as claimed in any of the preceding claims wherein an Ethernet Interface is used to download recorded data. ,TagSPECI:As per Annexure-II