Claims
1. A data processing apparatus which interleaves data, comprising:

parity interleave means for carrying out parity interleave of interleaving parity bits of an LDPC code obtained by carrying out LDPC encoding in accordance with a parity check matrix in which a parity matrix which is a portion corresponding to parity bits of an LDPC (Low Density Parity Check) code has a staircase structure individually to positions of other ones of the parity bits.

2. The data processing apparatus according to claim 1, wherein:

the bit number M of the parity bits of the LDPC code is a value other than the prime numbers; and

where two ones of devisors of the bit number M of the parity bits other than 1 and M whose product is equal to the bit number M of the parity bits are represented by P and q,

the bit number of information bits of the LDPC code is represented by K,

an integer equal to or higher than 0 but lower than P is represented by x, and

another integer equal to or higher than 0 but lower
than q is represented by y,

said parity interleave means interleaves a K+qx+y+l th code bit from among the parity bits which are K+l th to K+M th code bits of the LDPC code to the position of the K+Py+x+l th code bit.

3. The data processing apparatus according to claim 2, further comprising

re-arrangement means for carrying out, where the LDPC code is transmitted such that two or more ones of the code bits of the LDPC code are transmitted as one symbol, a re-arrangement process for re-arranging the code bits of the LDPC code after the parity interleave such that a plurality of code bits corresponding to the value 1 included in one arbitrary row of the parity check matrix are not included in the same symbol.

4. The data processing apparatus according to claim 2, wherein:

the LDPC code is an LDPC code wherein an information matrix which is a portion of the parity check matrix of the LDPC code which corresponds to the information bits of the LDPC code has a cyclic structure; and

said data processing apparatus further comprises

re-arrangement means for carrying out column twist interleave for changing, where a symbol is formed from code bits of the LDPC code written in a column direction of storage means for .storing the code bits of the LDPC code in a row direction and the column direction and read out in the row direction, the writing starting position when the code bits of the LDPC code are written in the column direction of said storage means is changed for each of the columns of said storage means as a rearrangement process for re-arranging the code bits of the LDPC code.

5. The data processing apparatus according to claim 4, wherein the parity matrix in the parity check matrix of the LDPC code has a pseudo cyclic structure in which the parity matrix has a portion having a cyclic structure except part thereof, the structure being, obtained by applying row replacement corresponding to the parity interleave.

6. The data processing apparatus according to claim 5, wherein:

where one symbol is formed from m ones of the code bits of the LDPC code, and

where the code length of the LDPC code is N bits and a predetermined positive integer is represented by b,

said storage means stores mb bits in the row
direction and stores N/ (mb) bits in the column direction;

the code bits of the LDPC code being written in the column direction of said storage means, whereafter the code bits are read out in the row direction,
the mb code bits read out in the row direction of said storage means being converted into b symbols.

7. A data processing method for a data processing apparatus which interleaves data, comprising:

a step carried out by the data processing apparatus of carrying out parity interleave of interleaving parity bits of an LDPC code obtained by carrying out LDPC encoding in accordance with a parity check matrix in which a parity matrix which is a portion corresponding to parity bits of an LDPC (Low Density Parity Check) code has a- staircase structure individually to positions of other ones of the parity bits.