This invention relates to Data Processing & Recording Module (DPRM) for use in Data
Recording Unit (DRU) of Flight Data Recorders and, more particularly, for receiving, processing
& recording of fight data signals in a variety of signal forms like Analog, Synchro, Discrete,
Frequency & Ratio metric (OAT Signals) and sending to Protected Memory Module (PMM).
BACKGROUND OF THE INVENTION
Flight data recorders are monitoring and recording instruments, carried aboard an
aircraft, which systematically monitor and store the instantaneous values of various aircraft
parameters. Early recorders were analog electromechanical devices which periodically marked,
in analog form, the value of a given airplane parameter on a moving wire or other permanent
storage medium. The time of occurrence of the parameter was also suitably scribed into the
medium opposite the mark for the sensed parameter. Subsequently, digital flight data recorders
have been developed which operate by converting each analog aircraft parameter into a
corresponding digital signal, and storing the digital signals on a permanent storage medium
such as magnetic tape.
The mandated flight parameters, which must be continuously recorded during the
operational flight profile of the aircraft, include a minimum number of functional parameters
considered essential for reconstructing the aircraft flight profile in post accident investigation
proceedings. Present recording requirements specify a minimum 25 hour interval.
The data recording is made on a Flight Data Recorder (FDR) designed to withstand a
crash environment. These FDRs are either of two types: (i) electromechanical or (ii) solid-state
memory. At present the electromechanical recorders represent the majority used on both civil
and military aircraft. They include both analog signal, metal foil and digital signal, magnetic tape.
The digital signal recorders (solid-state or electromechanical) represent the contemporary
standard for all new aircraft. This result 20 from the development of high accuracy, fast
response engine digital signal sensors, which have stimulated requirements for improved flight
data monitoring systems. The digital recording system signal formats are defined by ARINC
717, which replaces the ARINC 573/717 definitions of analog signal formats for implementing
the performance specifications for historical recording of the flight parameters.
The recording system input data is, as is the remaining non recorded flight data, sensed
within the 25 various operating systems of the aircraft, acquired and conditioned in a flight data
acquisition unit (FDAU), and presented to the flight data recorder (FDR) for preserved recording.
The FDAU is the collecting source for the flight data recorder as well as the other utilization
equipment (e.g. airborne integrated data system, AIDS). The FDR cannot function without the
FDAU. The FDAU, in turn, receives the flight data from the multifarious sensor signal groups of
the aircraft, including the Air Data Computer, 30 Flight Management System, etc. As a
consequence overall recording system integrity is dependent on the data sensors and sensor
signal conditioning circuitry, the data acquisition unit, the flight data recorder, and the aircraft
interconnecting wiring.
The extended nature of the components involved make reliability of the system a major
concern. Prior art recording systems include built-in test equipment (BITE) for the FDAU and
FDR, but not the sensors. 35 The sensors are not subject to BITE testing due to practical
constraints, e.g. nature of the sensor and/or the BITE requirements, or the existence of different
manufacturer and suppliers of the equipment; manufacturers of the data acquisition and
recorder hardware are not those which provide the sensors. As a consequence the sensor
interface is untested during flight.
To assure recording system integrity the airlines are required by regulatory agency to
periodically certify operation of the flight data recording system on each aircraft. This requires
that the FDR be removed from the aircraft and tested on a scheduled basis; typically every
3,000 hours. The data stored in the FDR is read from the recorder and transcribed to determine
that all elements of the system are functional. The FDR must then be routed through the airline
maintenance cycle prior to being returned to service. This not only represents high cost, but the
method of test (off-line) still allows the risk of 45 overlooking overall system integrity, e.g.
underestimating the significance or lack of significance of any given units of recorded data.
The flight data recording system includes a data recording unit (DRU) and a flight data
acquisition unit (FDAU) having a signal processor and nonvolatile memory for storing signals
representative of a deterministic flight mode algorithm which defines a generic aircraft flight
profile by preselected modes, each mode defining a flight profile operating station, the
deterministic flight mode algorithm defining the nominal values of some number of sensed flight
data parameters in terms of the 60 sensed values of some number of the remaining other
sensed flight parameters. At each such station, the signal processor comparing the actual
sensed mandatory flight parameter value with the corresponding determined value to establish
sensor accuracy.
The flight data recording system of the present invention provides for use of a
deterministic flight mode algorithm to perform the integrity check on the mandatory recorded
parameters including 65 measuring the accuracy of the sensed parameters to be recorded, and
the actuality of the flight data the selected aircraft flight parameters. The recording system flight
mode algorithm provides ARINC 717 systems operational testing. As such, the need for periodic
transcription of the FDR data to verify recorded sensed data accuracy is dramatically reduced.
SUMMARY OF PRESENT INVENTION
The present invention, therefore, is directed to Data Processing and Recording Module
(DPRM) of Data Recording Unit (DRU) for use in a Flight data recorder.
An aspect of the present invention is the ability of the data recording system to process a
set of parameter sense signals in response to a single CPU request and recording in protected
memory module (PMM). In this way, integrity of multiple signal sensor data is assured and
overhead on CPU operation is reduced.
A further aspect of the invention is the universal application of the present data
acquisition system. All aircraft parameter signals may be assigned to any of the multiple data
acquisition system inputs under CPU control. DPRM records the frame containing the
information of direct parameters & MIL-STD-1553B data acquired by the FDAU, which is
digitized by the DPRM itself.
The Main functions of Data Recording System are:
• Reception of acquired data from FDAU through Arinc-573/717 Interface
• Controlling of data recording in PMM according to the recording condition defined.
• Built in self-test to verify correct operation of the DPRM.
• Generate telemetry data on RS422 channel
• During replay, it reads data from PMM
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention will become more apparent and
descriptive in the description when considered together with figures/flow charts presented:
Figure 1: is a Block Diagram of Flight Data Recorder (FDR)
Figure 2: is a Block Diagram of Data Recording Unit (DRU)
Figure 3: is a Block Diagram of Data Processing & Recording Module (DPRM)
DETAILED DESCRIPTION
The Data Acquisition and processing unit is designed based on Motorola Micro-controller
which will be the main processor on which the application shall run. It operates at 25 MHz. The
module consists of on board memory of 2MB FLASH EPROM (1M x 16bit) and 512KB Static
RAM (256K X 16-bit) for code and data respectively and 32KB NVRAM for storing Sorties
information.
The four asynchronous serial ports two with RS-232 and two with RS-422 are provided
using internal UART ports of the micro controller. One port of Ethernet is implemented using the
Intel Device for milking of data.
The Board will also interface to the external protected memory module, with custom bus
interface.
The module features a full-buffered system for external bus expansion for interfacing
other IO modules using 16-bit bi-directional buffers. The block diagram of DPR Module is placed
at Figure – 3.
FEATURES
􀂃 Motorola micro controller @ 25 MHz
􀂃 Onboard oscillators for micro controller, MIL-1553B and UART
􀂃 2MByte Flash EPROM and 512KByte SRAM
􀂃 16-bit memory access
􀂃 Four serial ports. One port with RS232 interface and Three ports with RS-422
interface
􀂃 One USB interface
􀂃 One Ethernet interface
􀂃 One Arinc 717 Receive Interface
􀂃 One MIL-STD-1553B interface
􀂃 16-bit Bus expansion
􀂃 PMM interface
CPU:
The CPU module is designed based on Motorola Micro controller, which operates at
25MHz. The MC68xxx series Quad Integrated Communication Controller is a versatile one chip
integrated microprocessor with peripheral combination. The device consists of four serial
communication controllers (SCCs), two serial management controllers (SMCs,) and one serial
peripheral interface (SPI), four general purpose timers/counters, seven external interrupt lines
and eight programmable Chips selects.
MEMORY:
Memory is provided using single 16-bit devices. 2MB (1M X 16-bit) FLASH EPROM is
provided for code memory for application program and constants. The device used for Code
memory is flash, which require 5V single supply. The device has access time as fast as 70ns.
The device features top boot and bottom configuration. The device can be in-circuit
programmable.
512KB Static RAM is provided for data memory using 256K X 16-bit devices. Data
memory is used for storage of dynamic data, during the execution of the application program. It
is also used for downloading test and debugging programs during development phase. The
memory is provided using cypress device with access time as 25ns or better (15ns).
The Non-volatile memory required for storing the sorties is provided using the Ramtron
device, which is organized with access time 70ns Speed.
SERIAL PORTS:
The Serial ports are provided using the internal communication ports of the processor,
as UART ports. SCC1 is used for Ethernet Interface. SCC2 is used for the RS-232 ports and
SMC1 and SMC2 are used for RS-422 ports.
ARINC 717 INTERFACES:
ARINC 717 is an interface standard used to record flight data. This interface is used for
receiving the ARINC 717 transmitted data from the FDAU Processor card. Device is a Dual line
receiver is used. It is a digital line receiver, intended to use with digital system connected by
twisted pair lines. There is a strobe input, which is connected to the digital port of the micro
controller through a pull up of +5V .The output is high whenever this strobe is low.
The Inputs to this chip is coming from the FDAU, which is the Harvard Bi Phase encoded
data, which are taken at the input pins of the chip, from the connector. The output of this chip is
given to Serial peripheral Interface (SPI) port of the micro controller.
DATA RETRIEVAL PORT:
The data retrieval port is provided for milking out the recorded data. This is provided
using the Ethernet interface. The Device used from Intel. The Intel® Universal 10BASE-T
Transceiver is designed for IEEE 802.3 physical layer applications. It provides, in a single
CMOS device, all of the active circuitry for interfacing most standard IEEE 802.3 controllers to
10BASE- T media.
Timers/Counters:
The timers /counters are provided using four identical, 16-bit, general-purpose timers of
CPU. They are configured to use as timer counters for counting the Frequency input pulses.
Each Timer counter is a 16-bit, memory mapped, read-write up counter.
INTERRUPTS:
The module provides seven interrupt inputs using the externally connected interrupts of
the CPU from IRQ1 to IRQ7. These pins are prioritized interrupt request lines. IRQ7, the highest
priority, is non-maskable and IRQ6–IRQ1 is internally maskable interrupts. These interrupts are
synchronized and de bounced by input circuitry on two consecutive rising edges of the
processor clock.
• One interrupt is from Dual port Ram of DSP module (IRQ1),
• One from 1553 device (IRQ6),
• One from USB (IRQ3)
• One from Ethernet (IRQ2)
PMM INTERFACE:
The Protected Memory Module (PMM) is interface by the CPU Address and Data bus
using bus buffer and the required control signals are implemented as I/O lines. The required
ports are implemented in the CPLD.
DECODING LOGIC:
Control logic, Memory decoding, on board I/O decoding are implemented using Cypress
CPLD’s. This controls the bus access cycle and read – write operations for memory and I/O
devices.
BUS EXPANSION:
The module provides 16-bit bus expansion with required control signals for interfacing
with other IO cards using buffer devices.
POWER SUPPLY:
The module required +5VDC power supply for operation. On-board bypass capacitors
are provided on each power supply line.

WE CLAIMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved. The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A flight Data Processing & Recording Module (DPRM) is for recording the actual sensed values of flight parameters from a plurality of aircraft sensors at different flight modes of the aircraft flight profile, comprising:
Data recording means for providing nonvolatile recording of signal representations of the sensed flight parameter values; and
Data acquisition means, having signal processing means for providing said signal representations to said flight data recording means, and including signal memory means for storing signals;
as characterized by: said data acquisition means providing operational self testing of the flight data system and aircraft sensors using said signal processing means, and using test program means stored in said signal memory means and representing the deterministic flight mode algorithm indicative of optimum values of selected flight parameters at different flight modes of the aircraft flight profile, said processing means comparing the sensed signal value of each selected flight parameter with the related optimum signal value of said program means for the same flight mode and providing a test failure signal to said signal memory means in response to each difference signal magnitude there between.

2. The system of claim 1 wherein said signal memory means stores said test failure signals in a nonvolatile medium.

3. The system of claim 1 or 2, wherein said signal processing means in response to each test failure signal, compares the failed sensed flight parameter signal value of a present flight mode with the recorded sensed signal value of the same flight parameter in a preceding flight mode to provide a sensor test failure signal in response to the presence of substantially equal values for the same sensed parameter in succeeding flight modes.

4. The system of any one of claims 1 to 3 wherein said program means deterministic flight mode algorithm indicates said optimum values for each selected flight parameter in each flight mode of the aircraft in dependence on the relationship of the selected flight parameter to other flight parameters having known values in the same flight mode.

5. The system of claim 4, wherein said optimum values for each selected flight parameter are dependent on other flight parameters having known values which are independent of the related selected flight parameter in the same flight mode.

6. A DPRM as claimed in any of the preceding claims wherein a dedicated watchdog is used and it has to be triggered periodically by software to avoid occurring of Watchdog Timeout event.

7. A DPRM as claimed in any of the preceding claims wherein an RS-232 serial asynchronous interface is provided to enable communication with a Host PC and a serial ARINC-717 interface, which can be programmed for various pre-determined data rates.

8. A DPRM as claimed in any of the preceding claims wherein a CPLD is used to provide glue logic and Harvard Bi-phase encoding.

9. A DPRM as claimed in any of the preceding claims wherein a mini ACE 1553-B RT device is used to support communication over the MIL-STD 1553-B data bus interconnects. The RT address lines are accessible externally, so that the address can be easily configured.

10. A DPRM as claimed in any of the preceding claims wherein an Ethernet Interface and USB interface is used to download recorded data. ,TagSPECI:As per Annexure-II