i COMPLETE SPECIFICATION ^ [See Section 10; rule 13] "DATA PROCESSING APPARATUS AND METHOD^ I SONY CORPORATION, a Japanese corporation, of of 1-7-1 Konan. Minato- ^ ku, 108-0075 Tokyo, Japan, The following specification particularly describes tiie invention and the manner in which it is to be performed: FORM 2 THE PATENTS ACT 1970 [39 OF 1970] & THE PATENTS (AMENDMENT) RULES, 2006 DATA PROCESSING APPARATUS AND METHOD Field of Invention The present invention relates to data processing apparatus operable to map input symbols onto sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols. The present invention also relates to data processing apparatus operable to map symbols received from a predetermined number of sub-carrier signals of an OFDM symbol into an output symbol stream. Embodiments of the present invention can provide an OFDM tran smitter/recei ver. Background of the Invention The Digital Video Broadcasting-Terrestrial standard (DVB-T) utilises Orthogonal Frequency Division Multiplexing (OFDM) to communicate data representing video images and sound to receivers via a broadcast radio communications signal. There are known to be two modes for the DVB-T standard which are known as the 2k and the 8k mode. The 2k mode provides 2048 sub-carriers whereas the 8k mode provides 8192 sub-carriers. Similarly for the Digital Video Broadcasting-Handheld standard (DVB-H) a 4k mode has been provided, in which the number of sub-carriers is 4096. In order to improve the integrity of data communicated using DVB-T or DVB-H a symbol interleaver is provided in order to interleave input data symbols as these symbols are mapped onto the sub-carrier signals of an OFDM symbol. Such a symbol interleaver comprises an interleaver memory in combination with an address generator. The address generator generates an address for each of the input symbols, each address indicating one of the sub-carrier signals of the OFDM symbol onto which the data symbol is to be mapped. For the 2k mode and the 8k mode an arrangement has been disclosed in the DVB-T standard for generating the addresses for the mapping. Likewise for the 4k mode of DVB-H standard, an arrangement for generating addresses for the mapping has been provided and an address generator for implementing this mapping is disclosed in European Patent application 04251667.4. The address generator comprises a Hnear feed back shift register which is operable to generate a pseudo random bit sequence and a permutation circuit. The permutation circuit permutes the order of the content of the Hnear feed back shift register in order to generate an address. The address provides an indication of one of the OFDM sub-carriers for carrying an input data symbol stored in the interleaver memory, in order to map the mput symbols onto the sub-carrier signals of the OFDM symbol. In accordance with a ftirther development of the Digital Video Broadcasting-Terrestrial broadcasting standard, known as DVB-T2 there has been proposed that ftirther modes for communicating data be provided. Summary of Invention According to an aspect of the present invention there is provided a data processing apparatus operable to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols, the predetermined number of sub-carrier signals being determined in accordance with one of a plurality of operating modes and the input data symbols including first sets of data symbols and second sets of input data symbols. The data processing apparatus comprises a controller, an address generator and an interleaver memory, the controller being operable, when operating in accordance with an even interleaving process to read out a first set of the input data symbols from the interleaver memory on to the sub-carrier signals of an even OFDM symbol using read addresses generated by the address generator, and to write in a second set of the input data symbols into the interleaver memory using the addresses generated by the address generator. The controller is operable in accordance with an odd interleaving process, to read out a first set of input data symbols from the interleaver memory on to the sub-carrier signals of an odd OFDM symbol using read addresses determined in accordance with a sequential order of the first set of input data symbols, and to write in a second set of the input data symbols into the interleaver memory at write addresses determined in accordance with the sequential order of the first group of input data symbols, such that while input data symbols from the first set are being read from locations in the interleaver memory, input data symbols from the second set can be written to the locations just read from. The number of the sub-carriers which are available from a current OFDM symbol is different from the number of the sub-carriers which are available from a previous OFDM symbol, and the controller is operable to determine before reading out the first input data symbols from the interleaver memory, whether the read address is valid for the previous OFDM symbol, and to determine before writing the second input data symbols into the interleaver memory, whether the write address is valid for the current OFDM symbol. In multi-carrier modulation systems such as OFDM as used for DVB-T/H [1] and DVB-T2 [2], frequency or symbol interleavers are used to provide frequency diversity especially in frequency selective channels. In both systems, the frequency interleaver works differently for odd and even OFDM symbols. As will be explained shortly, to minimise the amount of memory used for interleaving, the odd and even symbol interleavers operate in a complimentary manner, so that the amount of memory can be minimised. DVB-T/H has only one type of OFDM symbol whilst DVB-T2 has at least three types of OFDM symbol, as a result, whilst in DVB-T/H the length of the vector of data sub-carriers into the interleaver is fixed, in DVB-T2 the input vector length varies according to the type of OFDM symbol. Embodiments of the present invention provide an arrangement in which a frequency interleaver can be implemented to cope with a change in a number of sub-carriers for carrying input data symbols between successive OFMD symbols, whilst minimising an amount of interleaver memory required. The frequency interleaver can be used in different operating modes, which may be required to communicate in any one of a plurality of operating modes. For example, the operating modes according to the DVB-T2 standard include IK, 2K, 4K, 8K, 16K and 32K modes. By determining before reading out the first input data symbols from the interleaver memory, whether the read address is valid for a previous OFDM symbol, and determining before writing the second input data symbols into the interleaver memory, whether the write address is valid for a current OFDM symbol, the interleaver memory size can be minimised to an amount which corresponds to a maximum number of sub-carriers, which are available for an OFDM symbol for any of the operating modes. The mode with the maximum number of sub-carriers may correspond to an operation of the interleaver to interleave input data symbols in accordance with odd and even OFDM symbols. Therefore, for example, ttie memory size of the interleaver memory can be made equal to the number of symbols which can be carried by the sub-carriers of the OFDM symbols in the mode which has the largest number of sub-carriers. For the example of DVB-T2 this is the 32k mode. Various aspects and features of the present invention are defined in the appended claims. Further aspects of the present invention include a data processing apparatus operable to map symbols received from a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol into an output symbol stream, as well as a transmitter and a receiver. Brief Description of Drawings Embodiments of the present invention will now be described by way of example only with reference to the accompanying drawings, wherein like parts are provided with corresponding reference numerals, and in which: Figure 1 is a schematic block diagram of a Coded OFDM transmitter which may be used, for example, with the DVB-T2 standard; Figure 2 is a schematic block diagram of parts of the transmitter shown in Figure 1 in which a symbol mapper and a frame builder illustrate the operation of an interleaver; Figure 3 is a schematic block diagram of the symbol interleaver shown in Figure 2; Figure 4 is a schematic block diagram of an interleaver memory shown in Figure 3 and the corresponding symbol de-interleaver in the receiver; Figure 5 is a schematic block diagram of an address generator shown in Figure 3 for the 16k mode; Figure 6 is a schematic block diagram of an address generator shown in Figure 3 for the 32k mode; Figure 7 is a flow diagram illustrating the operation of the interleaver shovm in Figure 3 in odd-even mode, for example for the 32K model; Figure 8 is a flow diagram illustrating the operation of the interleaver shown in Figure 3 in odd only mode, for example for the 16K model; Figure 9 is a schematic block diagram of a Coded OFDM receiver which may be used, for example, with the DVB-T2 standard; and Figure 10 is a schematic block diagram of a symbol de-interleaver which appears in Figure 9. Description of Preferred Embodiments The following description is provided to illustrate the operation of a symbol interleaver in accordance with the present technique^ although it will be appreciated that the symbol interleaver can be used with other modes and other DVB standards. Figure 1 provides an example block diagram of a Coded OFDM transmitter which may be used for example to transmit video images and audio signals in accordance with the DVB-T2 standard. In Figure 1 a program source generates data to be transmitted by the COFDM transmitter. A video coder 2, and audio coder 4 and a data coder 6 generate video, audio and other data to be transmitted which are fed to a program multiplexer 10. The output of the program multiplexer 10 forms a multiplexed stream with other information required to communicate the video, audio and other data. The multiplexer 10 provides a stream on a connecting channel 12. There may be many such multiplexed streams which are fed into different branches A, B etc. For simplicity, only branch A will be described. As shown in Figure 1 a COFDM transmitter 20 receives the stream at a multiplexer adaptation and energy dispersal block 22. The multiplexer adaptation and energy dispersal block 22 randomises the data and feeds the appropriate data to a forward error correction encoder 24 which performs error correction encoding of the stream. A bit interleaver 26 is provided to interleave the encoded data bits which for the example of DVB-T2 is the LDCP/BCH encoder output. The output from the bit interleaver 26 is fed to a bit into constellation mapper 28, which maps groups of bits onto a constellation point, which is to be used for conveying the encoded data bits. The outputs from the bit into constellation mapper 28 are constellation point labels that represent real and imaginary components. The constellation point labels represent data symbols formed from two or more bits depending on the modulation scheme used. These will be referred to as data cells. These data cells are passed through a time-interleaver 30 whose effect is to interleaver data cells resulting from multiple LDPC code words. The data cells are received by a frame builder 32, with data cells produced by branch B etc in Figure 1, via other channels 31. The frame builder 32 then forms many data cells into sequences to be conveyed on COFDM symbols, where a COFDM Number of Sub-carriers Adapted from DVB-T/H Thus in one example, the number of sub-carriers for the 16k mode is twelve thousand and ninety six, and for the 32K mode the number of sub-carriers is twenty four thousand one hundred and ninety two. Each frame comprises many such COFDM symbols. The sequence of data cells to be carried in each COFDM symbol is then passed to the symbol interleaver 33. The COFDM symbol is then generated by a COFDM symbol builder block 37 which uses the constellation data labels to generate the real and imaginary parts of the constellation points and also introducing pilot and synchronising signals fed from a pilot and embedded signal former 36. An OFDM modulator 38 then forms the OFDM symbol in the time domain which is fed to a guard insertion processor 40 for generating a guard interval between symbols, and then to a digital to analogue convertor 42 and fmally to an RF amplifier within an RF front 44 for eventual broadcast by the COFDM transmitter from an antenna 46. Interleaver The bit to constellation mapper 28, symbol interleaver 33 and the frame builder 32 are shown in more detail in Figure 2. The symbol interleaver provides a quasi-optimal mapping of the data symbols onto the OFDM sub-carrier signals. According to the example technique the symbol interleaver is provided to effect the optimal mapping of input data symbols onto 8 COFDM sub-carrier signals in accordance with a permutation code and generator polynomial, which has been verified by simulation analysis. As shown in Figure 2 a more detailed example illustration of the bit to symbol constellation mapper 28 and the frame builder 32 is provided to illustrate an example embodiment of the present technique. Data bits received from the bit interleaver 26 via a channel 62 are grouped into sets of bits to be mapped onto a data cell, in accordance with a number of bits per symbol provided by the modulation scheme. The groups of bits, which forms a data word, are fed in parallel via data channels 64 the a mapping processor 66. The mapping processor 66 then selects one of the data symbols, in accordance with a pre-assigned mapping. The constellation point, is represented by a real and an imaginary component but only its label is provided to the output channel 29 as one of a set of inputs to the frame builder 32. The frame builder 32 receives the data cells from the bit to constellation mapper 28 through channel 29, together with data cells from the other channels 31. After building a frame of many COFDM cell sequences, the cells of each COFDM symbol are then written into an interleaver memory 100 and read out of the interleaver memory 100 in accordance with write addresses and read addresses generated by an address generator 102. According to the write-in and read-out order, interleaving of the data cells is achieved, by generating appropriate addresses. The operation of the address generator 102 and the interleaver memory 100 will be described in more detail shortly with reference to Figures 3, 4, 5 and 6. The interleaved data cells are then mapped to real and imaginary components of data symbols, which are combined with pilot and synchronisation symbols received from the pilot and embedded signalling former 36 into an OFDM symbol builder 37, to form the COFDM symbol, which is fed to the OFDM modulator 38 as explained above. Figure 3 provides an example of parts of the symbol interleaver 33, which illustrates the present technique for interleaving symbols. In Figure 3 the input data cells from the frame builder 32 are written into the interleaver memory 100. The data cells are written into the interleaver memory 100 according to a write address fed from the address generator 102 on channel 104, and read out from the interleaver memory 100 according to a read address fed from the address generator 102 on a channel 106. The address generator 102 generates the write address and the read address as explained below, depending on whether the COFDM symbol is odd or even, which is identified from a signal fed from a channel 108, and depending on a selected mode, which is identified from a signal fed from a channel 110. As explained, the mode can be one of a Ik mode, 2k mode, 4k mode, 8k mode, 16k mode or a 32k mode. As explained below, the write address and the read address are generated differently for odd and even symbols as explained with reference to Figure 4, which provides an example implementation of the interleaver memory 100. In the example shown in Figure 4, the interleaver memory is shown to comprise an upper part 100 illustrating the operation of the interleaver memory in the transmitter and a lower part 340, which illustrates the operation of the de-interleaver memory in the receiver. The interleaver 100 and the de-interleaver 340 are shown together in Figure 4 in order to facilitate understanding of their operation. As shown in Figure 4 a representation of the communication between the interleaver 100 and the de-interleaver 340 via other devices and via a transmission charmel has been simplified and represented as a section 140 between the interleaver 100 and the de-interleaver 340. The operation of the interleaver 100 is described in the following paragraphs; Although Figure 4 provides an illustration of only four input data cells onto an example of four sub-carrier signals of a COFDM symbol, it will be appreciated that the technique illustrated in Figure 4 can be extended to a larger number of sub-carriers such as 756 for the Ik mode 1512 for the 2k mode, 3024 for the 4k mode and 6048 for the 8k mode, 12096 for the 16k mode and 24192 for the 32k mode. The input and output addressing of the interleaver memory 100 shown in Figure 4 is shown for odd and even symbols. For an even COFDM symbol the data cells are taken from the input channel 77 and written into the interleaver memory 124.1 in accordance with a sequence of addresses 120 generated for each COFDM symbol by the address generator 102. The write addresses are applied for the even symbol so that as illustrated interleaving is effected by the shuffling of the write-in addresses. Therefore, for each interleaved symbol y(h(q)) = y'(q). For odd symbols the same interleaver memory 124.2 is used. However, as shown in Figure 4 for the odd symbol the write-in order 132 is in the same address sequence used to read out the previous even symbol 126. This feature allows the odd and even symbol interleaver implementations to only use one interleaver memory 100 10 provided the read-out operation for a given address is performed before the write-in operation. The data cells written into the interleaver memory 124 during odd symbols are then read out in a sequence 134 generated by the address generator 102 for the next even COFDM symbol and so on. Thus only one address is generated per symbol, with the read-in and write-out for the odd/even COFDM symbol being performed contemporaneously. In summary, as represented in Figure 4, once the set of addresses H(q) has been calculated for all active sub-carriers, the input vector Y' =(yo% y\% YZ'^—yNmax-V) is processed to produce the interleaved vector Y = (yo, y\, y25—YNmax-l) ^^^fin^^* by: yH(q) = y'q for even symbols for q = 0,...,Nniax-l yq = y'H(q) for odd symbols for q = 0,...,Nmax-l In other words, for even OFDM symbols the input words are written in a permutated way into a memory and read back in a sequential way, whereas for odd symbols, they are written sequentially and read back permutated. In the above case, the permutation H(q) is defined by the following table: a lo 1 2 3 H(q) I 1 3 0 2 Table 1: permutation for simple case where Nmax =4 As shown in Figure 4, the de-interleaver 340 operates to reverse the interleaving applied by the interleaver 100, by applying the same set of addresses as generated by an equivalent address generator, but applying the write-in and read-out addresses in reverse. As such, for even symbols, the write-in addresses 342 are in sequential order, whereas the read out address 344 are provided by the address generator. Correspondingly, for the odd symbols, the write-in order 346 is determined from the set of addresses generated by the address generator, whereas read out 348 is in sequential order. Address Generation for the 16k and 32K Modes A schematic block diagram of the algorithm used to generate the permutation fiinction H(q) is represented in Figure 5 for the I6K mode and Figure 6 for the 32K mode. n An implementation of the address generator 102 for the 16k mode is shown in Figure 5. In Figure 5 a linear feed back shift register is formed by thirteen register stages 200 and a xor-gate 202 which is connected to the stages of the shift register 200 in accordance with a generator polynomial. Therefore, in accordance with the content of the shift register 200 a next bit of the shift register is provided from the output of the xor-gate 202 by xoring the content of shift registers R[0], R[l], R[4], R[5], R[9], R[l 1] according to the generator polynomial: ;?:[i2]^i?;_,[o]©i?;_.[i]®i?;_,[4]©i?;_j5]e^,L,[9]i?;^,[n] According to the generator polynomial a pseudo random bit sequence is generated from the content of the shift register 200. However, in order to generate an address for the 16k mode as illustrated, a permutation circuit 210 is provided which effectively permutes the order of the bits within the shift register 200.1 from an order R'i[n] to an order Ri[n\ at the output of the permutation circuit 210. Thirteen bits from the output of the permutation circuit 210 are then fed on a connecting channel 212 to which is added a most significant bit via a channel 214 which is provided by a toggle circuit 218. A fourteen bit address is therefore generated on channel 212. However, in order to ensure the authenticity of an address, an address check circuit 216 analyses the generated address to determine whether it exceeds a predetermined maximum value. The predetermined maximum value may correspond to the maximum number of sub-carrier signals, which are available for data symbols within the COFDM symbol, available for the mode which is being used. However, the interleaver for the 16k mode may also be used for other modes, so that the address generator 102 may also be used for the 2k mode, 4k mode, 8k mode, 16k mode and the 32k mode, by adjusting accordingly the number of the maximum valid address. If the generated address exceeds the predetermined maximum value then a control signal is generated by the address check unit 216 and fed via a connecting channel 220 to a control unit 224. If the generated address exceeds the predetermined maximum value then this address is rejected and a new address regenerated for the particular symbol. For the 16k mode, an (Nr - 1) bit word R'j is defined, with Nf = log2 Mjjiax> where M^ax = 16384 using a LFSR (Linear Feedback Shift Register). Bit permutation for the 16K mode As an example, this means that for the mode 16K, the bit number 12 of R'j is sent in bit position number 8 of Rj. The address H(q) is then derived from Ri through the following equation: H(q) = (imod2)-2^'-^ + ^R.(j)-2^ j=0 The (i mod2) ■ 2"^'"' part of the above equation is represented in Figure 5 by the toggle block T 218. An address check is then performed on H(q) to verify that the generated address is within the range of acceptable addresses: if (H(q)