DESCRIPTION
DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
TECHNICAL FIELD
5 [00011
The present invention relates to data processing
devices and data processing methods, and more
particularly, to a data processing device and a data
processing method that can easily process control data
10 that is required for performing demodulation and has its
PAPR (Peak-to-Average Power Ratio) improved.
BACKGROUND ART
[0002]
15 In DVB (Digital Video Broadcasting)-T.2, which is
one set of digital broadcasting standards, OFDM
(Orthogonal Frequency Division Multiplexing) is used as
the data modulation method, and data transmission is
performed for each unit called T2 frame (Non-Patent
20 Document 1).
CITATION LIST
NON-PATENT DOCUMENT
[0003]
25 Non-Patent Document 1: "Frame structure channel coding
and modulation for a second generation digital
terrestrial television broadcasting system (DVB-T2)I1, DVB
Document A122 June 2008
30 SUMMARY OF THE INVENTION
PROBLEMS TO BE SOLVED BY THE INVENTION
[0004]
In new standards for digital broadcasting, T2
frames (or frames equivalent to T2 frames) specified in
existing standards such as DVB-T.2 can be used as new
5 frames serving as units for data transmission.
[0005]
As T2 frames are used as new frames in the new
standards, (OFDM signals of) the new frames can be
readily processed in a reception device compliant with
10 the new standards.
[0006]
That is, in a reception device compliant with the
new standards using T2 frames as new frames, the new
frames can be processed in the same manner as in a
15 reception device compliant with DVB-T.2.
[0007]
In T2 frames, preambles called P2 symbols
containing the control data called "Ll" necessary for
performing demodulation are provided. However, the PAPR
20 of an OFDM signal of a P2 symbol in each T2 frame might
be relatively high.
[0008]
In a case where the PAPR of an OFDM signal of a P2
symbol in a T2 frame is high, if the OFDM signal of the
25 P2 symbol has high power, the high-power OFDM signal
might be clipped in a reception device that receives the
OFDM signal.
[0009]
If an OFDM signal is clipped in a reception device,
30 OFDM signal quality is degraded, which might adversely
affect demodulation of the OFDM signal.
[OOlO]
In view of this, to improve the PAPR of (the OFDM
signal of) the control data necessary for demodulation
(or ideally, to adjust the PAPR to "1") , scrambling
5 (energy diffusion) (randomization) can be performed on
the control data in a transmission device that transmits
OFDM signals according to the new standards.
[ OOll]
However, where the control data scrambling is
10 performed to improve the PAPR, the reception device might
need to perform not only the descrambling to cancel the
scrambling performed on the control data, but also a
different operation from an operation performed in a case
where the control data scrambling is not performed. As a
15 result, it becomes difficult to facilitate processing
(demodulation) of (the OFDM signal of) the control data,
or to process the control data in (substantially) the
same manner as in a reception device compliant with DVBThe
present invention has been made in view of
those circumstances, and is to facilitate processing of
control data having its PAPR improved.
25 SOLUTIONS TO PROBLEMS
[0013]
A data processing device of a first aspect of the
present invention includes: a padding means that pads
control data with dummy data, the control data being
30 necessary for demodulation; a scrambling means that
scrambles post-padding control data, the post-padding
control data being the padded control data; a replacement
means that generates replacement data by replacing
scrambled dummy data in the scrambled post-padding
control data with the dummy data; and an error correction
5 encoding means that performs error correction encoding on
the replacement data.
[0014]
A data processing method of the first aspect of the
present invention includes the steps of: padding control
10 data with dummy data, the control data being necessary
for demodulation; scrambling post-padding control data,
the post-padding control data being the padded control
data; generating replacement data by replacing scrambled
dummy data in the scrambled post-padding control data
15 with the dummy data; and performing error correction
encoding on the replacement data.
[0015]
In the above described first aspect, the control
data necessary for demodulation is padded with dummy data,
20 and scrambling is performed on post-padding control data
that is the padded control data. Further, replacement
data is generated by replacing the scrambled dummy data
in the scrambled post-padding control data with the dummy
data, and error correction encoding is performed on the
25 replacement data.
[0016]
A data processing device of a second aspect of the
present invention includes: a scrambling means that
scrambles control data necessary for demodulation; a
30 padding means that pads the scrambled control data with
dummy data; and an error correction encoding means that
performs error correction encoding on post-padding
scrambled data formed by padding the scrambled control
data with the dummy data.
[0017]
5 A data processing method of the second aspect of
the present invention includes the steps of: scrambling
control data necessary for demodulation; padding the
scrambled control data with dummy data; and performing
error correction encoding on post-padding scrambled data
10 formed by padding the scrambled control data with the
dummy data.
[0018]
In the above described second aspect, scrambling is
performed on the control data necessary for demodulation,
15 and the scrambled control data is padded with dummy data.
Error correction encoding is then performed on the postpadding
scrambled data formed by padding the scrambled
control data with the dummy data.
[0019]
20 A data processing device of a third aspect of the
present invention includes: an error correction means
that performs error correction to decode an error
correcting code into replacement data, the error
correcting code being obtained by a transmission device;
25 and a descrambling means that descrambles the replacement
data, the transmission device padding control data
necessary for demodulation with dummy data, scrambling
post-padding control data that is the padded control data,
generating the replacement data by replacing scrambled
30 dummy data in the scrambled post-padding control data
with the dummy data, and performing error correction
encoding on the replacement data.
[0020]
A data processing method of the third aspect of the
present invention includes the steps of: performing error
5 correction to decode an error correcting code into
replacement data, the error correcting code being
obtained by a transmission device; and descrambling the
replacement data, the transmission device padding control
data necessary for demodulation with dummy data,
10 scrambling post-padding control data that is the padded
control data, generating the replacement data by
replacing scrambled dummy data in the scrambled postpadding
control data with the dummy data, and performing
error correction encoding on the replacement data.
15 [0021]
In the above described third aspect, error
correction is performed to decode an error correcting
code obtained by a transmission device into the
replacement data, and descrambling is performed on the
20 replacement data.
[0022]
A data processing device of a fourth aspect of the
present invention includes: an error correction means
that performs error correction to decode an error
25 correcting code into post-padding scrambled data, the
error correcting code being obtained by a transmission
device; a deletion means that deletes dummy data from the
post-padding scrambled data, and outputs scrambled
control data; and a descrambling means that descrambles
30 the scrambled control data, the transmission device
scrambling control data necessary for demodulation,
padding the scrambled control data with the dummy data,
and performing error correction encoding on the postpadding
scrambled data formed by padding the scrambled
control data with the dummy data.
5 [00231
A data processing method of the fourth aspect of
the present invention includes the steps of: performing
error correction to decode an error correcting code into
post-padding scrambled data, the error correcting code
10 being obtained by a transmission device; deleting dummy
data from the post-padding scrambled data, to output
scrambled control data; and descrambling the scrambled
control data, the transmission device scrambling control
data necessary for demodulation, padding the scrambled
15 control data with the dummy data, and performing error
correction encoding on the post-padding scrambled data
formed by padding the scrambled control data with the
dummy data.
[0024]
20 In the above described fourth aspect, error
correction is performed to decode an error correcting
code obtained by a transmission device into the postpadding
scrambled data, and the dummy data is deleted
from the post-padding scrambled data, to output the
25 scrambled control data. Descrambling is then performed
on the scrambled control data.
[0025]
A data processing device may be an independent
device, or may be an internal block in a single device.
30
EFFECTS OF THE INVENTION
[00261
According to the first through fourth aspects of
the present invention, control data having its PAPR
improved can be readily processed.
5
BRIEF DESCRIPTION OF DRAWINGS
COO271
Fig. 1 is a block diagram showing an example
structure of a transmission device that transmits data
10 without scrambling control data.
Fig. 2 is a diagram showing the format of a bit
stream of an OFDM signal to be transmitted by the
transmission device.
Fig. 3 is a diagram for explaining operations of
15 the padder 21, the BCH encoder 22, the LDPC encoder 23,
and the shortening unit 24.
Fig. 4 is a block diagram showing an example
structure of a reception device that receives data from
the transmission device that transmits data without
20 scrambling control data.
Fig. 5 is a block diagram showing a first example
structure of a transmission device that transmits data
after scrambling control data.
Fig. 6 is a diagram for explaining operations of
25 the padder 21, the scrambler 101, the BCH encoder 22, the
LDPC encoder 23, and the shortening unit 24.
Fig. 7 is a block diagram showing a first example
structure of a reception device that receives data from a
transmission device that transmits data after scrambling
30 control data.
Fig. 8 is a block diagram showing a second example
structure of a transmission device that transmits data
after scrambling control data.
Fig. 9 is a diagram for explaining operations of
the scrambler 101, the padder 21, the BCH encoder 22, the
5 LDPC encoder 23, and the shortening unit 24.
Fig. 10 is a block diagram showing a second example
structure of a reception device that receives data from a
transmission device that transmits data after scrambling
control data.
10 Fig. 11 is a block diagram showing a third example
structure of a transmission device that transmits data
after scrambling control data.
Fig. 12 is a diagram for explaining operations of
the padder 21, the scrambler 101, the replacement unit
15 121, the BCH encoder 22, the LDPC encoder 23, and the
shortening unit 24.
Fig. 13 is a block diagram showing a third example
structure of a reception device that receives data from a
transmission device that transmits data after scrambling
20 control data.
Fig. 14 is a block diagram showing an example
structure of the scrambler 101.
Fig. 15 is a diagram showing a first example format
of a bit stream of an OFDM signal to be transmitted by a
25 transmission device that scrambles control data and is
compliant with new standards.
Fig. 16 is a diagram showing a second example
format of a bit stream of an OFDM signal to be
transmitted by a transmission device that scrambles
30 control data and is compliant with the new standards.
Fig. 17 is a block diagram showing an example
structure of an embodiment of a computer to which the
present invention is applied.
MODE FOR CARRYING OUT THE INVENTION
5 [0028]
The following is a description of embodiments of
the present invention. As a preliminary step toward the
detailed description of the present invention, a
transmission device that transmits data without
10 scrambling control data and a reception device that
receives data from such a transmission device are
described.
[0029]
[Transmission Device Transmitting Data Without Scrambling
15 Control Data]
[0030]
Fig. 1 is a block diagram showing an example
structure of a transmission device that transmits data
without scrambling control data, such as a transmission
20 device compliant with DVB-T.2.
[0031]
The transmission device transmits transmission
target data, which is actual data such as image data and
audio data of a digital broadcasting show, by OFDM, for
25 example.
[0032]
Specifically, in the transmission device, one or
more streams as the target data are supplied to a mode
adaptation/multiplexer 11.
30 [0033]
The mode adaptation/multiplexer 11 selects a mode
such as a transmission mode, and multiplexes the one or
more streams supplied thereto. The resultant data is
supplied to a padder 12.
[0034]
5 The padder 12 pads the data supplied from the mode
adaptation/multiplexer 11 with a required number of zeros
as dummy data (or inserts Null to the data), for example,
and supplies the resultant data to a BB scrambler 13.
[0035]
10 The BB scrambler 13 performs scrambling (energy
diffusion) on the data supplied from the padder 12, and
supplies the resultant data to a BCH encoder 14.
[0036]
The BCH encoder 14 performs BCH encoding as error
15 correction encoding on the data supplied from the BB
scrambler 13, and supplies the resultant BCH code as LDPC
target data to be subjected to LDPC encoding, to an LDPC
encoder 15.
[0037]
20 The LDPC encoder 15 performs LDPC encoding as error
correction encoding on the LDPC target data supplied from
the BCH encoder 14, and supplies the resultant LDPC code
to a bit interleaver 16.
[0038]
25 The bit interleaver 16 performs bit interleaving to
interleave the LDPC code from the LDPC encoder 15 bit by
bit, and the LDPC code subjected to the bit interleaving
is supplied to a QAM encoder 17.
[0039]
30 The QAM encoder 17 performs orthogonal modulation
(multilevel modulation) on the LDPC code from the bit
interleaver 16 by mapping each unit (symbol unit) of one
or more bits of the LDPC code to a signal point
representing one symbol of orthogonal modulation.
[0040]
5 That is, the QAM encoder 17 performs orthogonal
modulation by mapping each symbol unit of one or more
bits of the LDPC code from the bit interleaver 16 to one
of the signal points that are determined by the
modulation method for the orthogonal modulation performed
10 on the LDPC code in the I-Q plane (I-Q constellation)
specified by the I-axis indicating the I-component of the
same phase as the carrier waves and the Q-axis indicating
the Q-component perpendicular to the carrier waves.
[0041]
15 Here, examples of modulation methods for orthogonal
modulation performed by the QAM encoder 17 include
modulation methods specified in the DVB-T standards, such
as QPSK (Quadrature Phase Shift Keying), 16QAM
(Quadrature Amplitude Modulation), 64QAM, 256QAM, 1024QAM,
20 and 4096QAM. At the QAM encoder 17, which modulation
method is used in the orthogonal modulation is set
beforehand in accordance with an operation by the
operator of the transmission device, for example. The
QAM encoder 17 can also perform other orthogonal
25 modulation such as 4PAM (Pulse Amplitude Modulation).
[0042]
The data obtained through the operation by the QAM
encoder 17 (the symbols mapped to signal points) is
supplied to a time interleaver 18.
30 [0043]
The time interleaver 18 performs time interleaving
(interleaving in the temporal direction) on each symbol
unit of the data (symbols) supplied from the QAM encoder
17, and supplies the resultant data to a SISO/MISO
encoder 19.
5 [0044]
The SISO/MISO encoder 19 performs space-time
encoding on the data (symbols) supplied from the time
interleaver 18, and supplies the resultant data to a
frequency interleaver 20.
10 [0045]
The frequency interleaver 20 performs frequency
interleaving (interleaving in the frequency direction) on
each symbol unit of the data (symbols) supplied from the
SISO/MISO encoder 19, and supplies the resultant data to
15 a frame builder/resource allocation unit 27.
[0046]
Control data (signaling) called L1 or the like for
transmission control required for performing demodulation
on data transmitted from the transmission device is
20 supplied to a padder 21, for example.
[0047]
The padder 21 pads the control data supplied
thereto with a required number of zeros as dummy data (or
inserts Null to the control data), for example, and
25 supplies the resultant data to a BCH encoder 22.
[0048]
Like the BCH encoder 14, the BCH encoder 22
performs BCH encoding on the data supplied from the
padder 21, and supplies the resultant BCH data to an LDPC
30 encoder 23.
[0049]
Like the LDPC encoder 15, the LDPC encoder 23
performs LDPC encoding on LDPC target data that is the
data supplied from the BCH encoder 22, and supplies the
resultant LDPC code to a shortening unit 24.
5 [00501
The shortening unit 24 performs shortening by
deleting the dummy data from the LDPC code supplied from
the LDPC encoder 23 and puncturing the parity bits of the
LDPC code, and supplies the shortened LDPC code to a QAM
10 encoder 25.
[0051]
Like the QAM encoder 17, the QAM encoder 25
performs orthogonal modulation on the LDPC code supplied
from the shortening unit 24 by mapping each unit (symbol
15 unit) of one or more bits of the LDPC code to a signal
point representing one symbol of orthogonal modulation,
and supplies the resultant data (symbols) to a frequency
interleaver 26.
[0052]
20 Like the frequency interleaver 20, the frequency
interleaver 26 performs frequency interleaving on each
symbol unit of the data (symbols) supplied from the QAM
encoder 25, and supplies the resultant data to the frame
builder/resource allocation unit 27.
25 [0053]
The frame builder/resource allocation unit 27
inserts a pilot symbol to each relevant location in the
data (symbols) supplied from the frequency interleavers
20 and 26, and creates a frame called a T2 frame that is
30 compliant with DVB-T.2 and is formed with a predetermined
number of symbols out of the resultant data (symbols).
The frame is supplied to an OFDM generation unit 28.
10054 1
The OFDM generation unit 28 performs necessary
signal processing such as an IFFT (Inverse Fast Fourier
5 Transform) on the frame supplied from the frame
builder/resource allocation unit 27, to generate an OFDM
signal corresponding to the frame. The OFDM signal is
then wirelessly transmitted.
[0055]
10 Fig. 2 is a diagram showing the format of a bit
stream of an OFDM signal to be transmitted by the
transmission device shown in Fig. 1.
[0056]
The bit stream of the OFDM signal to be transmitted
15 by the transmission device shown in Fig. 1 is formed with
T2 frames.
[0057]
As shown in Fig. 2, in each T2 frame, a P1 symbol
as a preamble, P2 symbols, and symbols called "Normal",
20 and a symbol called "FC" (Flame Closing) are placed in
this order.
[0058]
In Fig. 2 (as well as in Figs. 15 and 16), which
will be described later), each "GI" represents a guard
25 interval.
[0059]
The symbols (the P2 symbol and the data symbols)
existing between a guard interval and the next guard
interval are the OFDM symbols to be subjected to one IFFT
30 (and one FFT) in OFDM.
[0060]
The P1 symbol is the symbol for P1 signaling. The
P1 symbol contains transmission parameters called S1 and
S2. The S1 and S2 indicate by which method the OFDM
signal is transmitted, SISO (Single Input Single Output
5 (meaning one transmitting antenna and one receiving
antenna)) or MIS0 (Multiple Input, Single Output (meaning
multiple transmitting antennas but one receiving
antenna)), and indicates the FFT size used when a FFT is
performed on the P2 symbol (the number of samples
10 (symbols) to be processed in one FFT).
[0061]
The P1 symbol contains 1 K (= 1024) symbols as
valid symbols, and part of the valid symbols and the rest
of the valid symbols are subjected to frequency shifting.
15 Accordingly, duplicates of the part of the valid symbols
and the rest of the valid symbols are formed before and
after the valid symbols, and can be detected by
determining an OFDM signal correlation.
[0062]
20 If a frame containing a PI symbol is a T2 frame,
the S1 and S2 contained in the P1 symbol contain
information (frame identification information) indicating
that the frame is a T2 frame.
[0063]
25 Accordingly, a reception device can determine that
a frame is a T2 frame by referring to the S1 and S2
contained in the P1 symbol.
[0064]
The P2 symbols are symbols for transmitting control
30 data called L1, which is necessary for demodulating an
OFDM signal, and the L1 includes two types of data that
are first and second data: L1 post-signaling as the first
data and L1 pre-signaling as the second data).
[00651
The L1 pre-signaling contains the information
5 necessary for demodulating the L1 post-signaling, and the
L1 post-signaling contains the information necessary for
a reception device receiving the OFDM signal to access
(the layer pipes of) the physical layer, or the
information necessary for demodulating the data symbols.
10 [0066]
In the L1 pre-signaling, a guard interval length, a
pilot pattern (PP) showing a pilot signal layout
indicating which symbols (subcarriers) contain pilot
signals that are known signals, information (BWT - EXT)
15 indicating whether the transmission band for transmitting
OFDM signals is extended, the number (NDSYM) of OFDM
symbols contained in one T2 frame, and the like are
contained as the information necessary for demodulating
the data symbols.
20 [0067]
Fig. 3 is a diagram for explaining operations of
the padder 21, the BCH encoder 22, the LDPC encoder 23,
and the shortening unit 24 shown in Fig. 1.
[0068]
25 Control data KSi, of a predetermined length, which
is the L1 pre-signaling or the L1 post-signaling, or both
the L1 pre-signaling and the L1 post-signaling, is
supplied to the padder 21.
[0069]
30 The padder 21 pads the control data Ksig supplied
thereto with a required number of zeros as dummy data,
for example.
[0070]
Specifically, the data length (the number of bits)
of the control data KSi, is shorter than the length
5 (information bit length) of the data to be subjected to
the BCH encoding as the error correction encoding to be
performed at the BCH encoder 22 in a later stage.
Therefore, the padder 21 pads the control data with zeros
as the dummy data, so that the data length (the number of
10 bits) of the padded control data becomes equal to the
length of the data to be subjected to the BCH encoding as
the error correction encoding to be performed at the BCH
encoder 22 in a later stage.
[0071]
15 The post-padding control data Kbch that is the
padded control data is supplied from the padder 21 to the
BCH encoder 22.
[0072]
The BCH encoder 22 performs the BCH encoding as the
20 error correction encoding on the post-padding control
data Kbch supplied from the padder 21, and supplies the
resultant BCH code Kldpc to the LDPC encoder 23.
Here, the BCH encoder 22 determines the BCH code
25 parity (BCH Parity) bits for the post-padding control
data Kbch, and adds the parity bits to the post-padding
control data Kbchr to obtain the BCH code Kldpc of the
post-padding control data Kbch. In this manner, the BCH
encoding is performed.
30 [0074]
The LDPC encoder 23 performs the LDPC encoding as
the error correction encoding on the BCH code Kldpc of the
post-padding control data Kbch supplied from the BCH
encoder 22, and supplies the resultant LDPC code Nldpc to
the shortening unit 24.
5 [00751
The LDPC encoder 23 determines the LDPC code parity
(LDPC Parity) bits for the BCH code Kldpc of the postpadding
control data Kbch, and adds the parity bits to the
BCH code Kldpc, to obtain the LDPC code Nldpc of the BCH
10 code Kldpc. In this manner, the LDPC encoding is
performed.
[0076]
The shortening unit 24 performs shortening by
deleting the zeros as the dummy data from the LDPC code
15 Nldpc supplied from the LDPC encoder 23 and puncturing
(part of) the parity bits of the LDPC code Nldpc, and
supplies the post-shortening LDPC code Npost to the QAM
encoder 25.
[0077]
20 [Reception Device that Receives Data from the
Transmission Device that Transmits Data Without
Scrambling Control Data]
[0078]
Fig. 4 is a block diagram showing an example
25 structure of a reception device, such as a reception
device compliant with DVB-T.2, which receives data from
the transmission device that is shown in Fig. 1 and
transmits data without scrambling control data.
[0079]
30 The reception device shown in Fig. 4 receives OFDM
signals from the transmission device shown in Fig. 1, and
demodulates the OFDM signals.
[00801
Specifically, in the reception device, an OFDM
signal is received from the transmission device shown in
5 Fig. 1, and is supplied to an OFDM operation unit 31.
[0081]
The OFDM operation unit 31 performs signal
processing such as a FFT on the supplied OFDM signal, and
supplies the resultant data (symbols) to a frame
10 management unit 32.
[0082]
The frame management unit 32 performs processing
(frame interpretation) on a frame formed with the symbols
supplied from the OFDM operation unit 31, and supplies
15 the symbols of the target data contained in the data
symbols in the frame (T2 frame) to a frequency
deinterleaver 33, and the symbols of the control data
contained in the P2 symbols in the frame to a frequency
deinterleaver 43.
20 [0083]
The frequency deinterleaver 33 performs frequency
deinterleaving on each of the symbols supplied from the
frame management unit 32, and supplies the results to a
SISO/MISO decoder 34.
25 [0084]
The SISO/MISO decoder 34 performs space-time
decoding on the data (symbols) supplied from the
frequency deinterleaver 33, and supplies the results to a
time deinterleaver 35.
30 [0085]
The time deinterleaver 35 performs time
deinterleaving on each symbol of the data (symbols)
supplied from the SISO/MISO decoder 34, and supplies the
results to a QAM decoder 36.
[0086]
5 The QAM decoder 36 performs orthogonal demodulation
by demapping (signal point location decoding) the symbols
(the symbols located at signal points) supplied from the
time deinterleaver 35, and supplies the resultant data
(symbols) to a bit deinterleaver 37.
10 [0087]
The bit deinterleaver 37 performs bit
deinterleaving on the data (symbols) supplied from the
QAM decoder 36, to restore the bit sequence rearranged in
the bit interleaving performed by the bit interleaver 16
15 of Fig. 1 to the original sequence. The resultant LDPC
code is supplied to an LDPC decoder 38.
[0088]
The LDPC decoder 38 performs LDPC decoding on the
LDPC code supplied from the bit deinterleaver 37, and
20 supplies the resultant BCH code to a BCH decoder 39.
[0089]
The BCH decoder 39 performs BCH decoding on the BCH
code supplied from the LDPC decoder 38, and supplies the
resultant data to a BB descrambler 40.
25 [0090]
The BB descrambler 40 performs descrambling
(inverse energy diffusion) on the data supplied from the
BCH decoder 39, and supplies the resultant data to a null
deletion unit 41.
30 [0091]
The null deletion unit 41 deletes the nulls
inserted by the padder 12 of Fig. 1 from the data
supplied from the BB descrambler 40, and supplies the
results to a demultiplexer 42.
[0092]
5 The demultiplexer 42 separates each of the one or
more streams (target data) multiplexed on the data
supplied from the null deletion unit 41, and outputs each
of the separated streams.
[00931
10 Meanwhile, the frequency deinterleaver 43 performs
frequency deinterleaving on each of the symbols (the
symbols of the control data) supplied from the frame
management unit 32, and supplies the results to a QAM
decoder 44.
15 [0094]
The QAM decoder 44 performs orthogonal demodulation
by demapping (signal point location decoding) the symbols
(the symbols located at signal points) supplied from the
frequency deinterleaver 43, and supplies the post-
20 shortening LDPC code NpOst (Fig. 3) obtained as a result
to a restoration unit 45.
[0095]
The restoration unit 45 performs a restoration
operation by padding the post-shortening LDPC code NpOst
25 from the QAM decoder 44 with zeros as dummy data and
depuncturing parity bits of the LDPC code. In this
manner, the pre-shortening LDPC code Nldpc (Fig. 3) is
restored, and is supplied to an LDPC decoder 46.
[0096]
30 The LDPC decoder 46 performs LDPC decoding on the
LDPC code Nldpc supplied from the restoration unit 45, and
supplies the resultant BCH code Kldpc (Fig. 3) to a BCH
decoder 47.
[0097]
The BCH decoder 47 performs BCH decoding on the BCH
5 code Kldpc supplied from the LDPC decoder 46, and supplies
the resultant post-padding control data Kbch (Fig. 3) to a
deletion unit 48.
[0098]
The deletion unit 48 deletes the zeros as the dummy
10 data from the post-padding control data Kbch, and supplies
the resultant control data Ksig (Fig. 3) to a control unit
49.
[0099]
Based on the control data Ksig supplied from the
15 deletion unit 48, the control unit 49 controls the
respective blocks constituting the reception device.
[OlOO]
[First Example Structure of a Transmission Device That
Transmits Data After Scrambling Control Data]
20 [OlOl]
If T2 frames (or frames equivalent to T2 frames)
specified in existing standards such as DVB-T.2 are used
as new frames serving as units for data transmission in
new standards for digital broadcasting, (OFDM signals of)
25 the new frames can be readily processed in a reception
device compliant with the new standards.
[0102]
That is, in a reception device compliant with the
new standards using T2 frames as new frames, for example,
30 the new frames can be processed in the same manner as in
a reception device compliant with DVB-T.2.
[0103]
As described above, the PAPR of an OFDM signal of a
P2 symbol containing L1 as control data in a T2 frame
might have a relatively large value. Therefore, if T2
5 frames are used as the new frames in the new standards as
described above, a high-power OFDM signal of a P2 symbol
might be clipped in a reception device compliant with the
new standards.
[0104]
10 If an OFDM signal is clipped in a reception device,
OFDM signal quality is degraded, which might adversely
affect demodulation of the OFDM signal.
[0105]
In view of this, to improve the PAPR of (the OFDM
15 signal of) the control data necessary for demodulation
(or ideally, to adjust the PAPR to "1") , scrambling
(energy diffusion) is performed on the control data in a
transmission device that transmits OFDM signals according
to the new standards.
20 [0106]
Fig. 5 is a block diagram showing a first example
structure of a transmission device that transmits data
after scrambling control data.
[0107]
25 In the drawing, the components equivalent to those
of the transmission device of Fig. 1 are denoted by the
same reference numerals as those used in Fig. 1, and
explanation of them will not be repeated.
[0108]
30 The transmission device of Fig. 5 is the same as
the transmission device of Fig. 1 in including a mode
adaptation/multiplexer 11 through an OFDM generation unit
28.
[0109]
However, the transmission device of Fig. 5 differs
5 from the transmission device of Fig. 1 in further
including a scrambler 101 between the padder 21 and the
BCH encoder 22.
[ OllO]
The post-padding control data Kbch (Fig. 3) is
10 supplied from the padder 21 to the scrambler 101.
The scrambler 101 performs scrambling (energy
diffusion) on the post-padding control data Kbch supplied
from the padder 21, and outputs the scrambled post-
15 padding control data.
[0112]
The scrambled post-padding control data output from
the scrambler 101 is supplied to the BCH encoder 22, and
the same operations as those in the transmission device
20 of Fig. 1 are then performed at the BCH encoder 22, the
LDPC encoder 23, and the shortening unit 24.
[0113]
Fig. 6 is a diagram for explaining operations of
the padder 21, the scrambler 101, the BCH encoder 22, the
25 LDPC encoder 23, and the shortening unit 24 shown in Fig.
The control data Ksig of the predetermined length is
supplied to the padder 21.
30 [0115]
The padder 21 pads the control data Ksig supplied
thereto with a required number of zeros as dummy data,
and supplies the post-padding control data Kbch, which is
the padded control data, to the scrambler 101.
[0116]
5 The scrambler 101 performs scrambling on the postpadding
control data Kbch supplied from the padder 21, and
supplies the scrambled post-padding control data Kbch's' to
the BCH encoder 22.
[0117]
10 The BCH encoder 22 performs BCH encoding as error
correction encoding on the scrambled post-padding control
data ~ ~ , h ' ~s'u pplied from the padder 21, and supplies the
resultant BCH code Kldpc to the LDPC encoder 23.
[ 0 11 8 ]
15 Specifically, the BCH encoder 22 determines the BCH
code parity bits for the scrambled post-padding control
data Kbch's', and adds the parity bits to the scrambled
post-padding control data ~b~h'~t'o, obtain the BCH code
Kldpco f the scrambled post-padding control data Kbch's'fa s
20 in the case described with reference to Fig. 3.
[0119]
The LDPC encoder 23 performs LDPC encoding as error
correction encoding on the BCH code Kldpc of the scrambled
pos t-padding control data ~b,h'~' supplied from the BCH
25 encoder 22, and supplies the resultant LDPC code Nldpc to
the shortening unit 24.
[0120]
Specifically, the LDPC encoder 23 determines the
LDPC code parity bits for the BCH code Kldpc of the
30 scrambled post-padding control data Kbch's'la nd adds the
parity bits to the BCH code Kldpcr to obtain the LDPC code
Nldpc of the BCH code Kldpcr as in the case described with
reference to Fig. 3.
[0121]
The shortening unit 24 performs shortening by
5 deleting the scrambled dummy data from the LDPC code Nldpc
supplied from the LDPC encoder 23 and puncturing (part
of) the parity bits of the LDPC code Nldpc, and supplies
the post-shortening LDPC code Npost to the QAM encoder 25.
[0122]
10 [First Example Structure of a Reception Device That
Receives Data from a Transmission Device That Transmits
Data after Scrambling Control Data]
[0123]
Fig. 7 is a block diagram showing an example
15 structure of a reception device that receives data from
the transmission device that is shown in Fig. 5 and
transmits data after scrambling control data.
[01241
In the drawing, the components equivalent to those
20 of the reception device of Fig. 4 are denoted by the same
reference numerals as those used in Fig. 4, and
explanation of them will not be repeated.
[0125]
The reception device of Fig. 7 is the same as the
25 reception device of Fig. 4 in including an OFDM operation
unit 31 through a QAM decoder 44, and an LDPC decoder 46
through a control unit 49.
[0126]
However, the reception device of Fig. 7 differs
30 from the reception device of Fig. 4 in that the
restoration unit 45 is replaced with a restoration unit
111, and a descrambler 112 is newly provided between the
BCH decoder 47 and the deletion unit 48.
[0127]
In the reception device of Fig. 7, the QAM decoder
5 44 outputs the post-shortening LDPC code Npost (Fig. 6 ) ,
and the post-shortening LDPC code Npost is supplied to the
restoration unit 111, as in the reception device of Fig.
4.
[0128]
10 The restoration unit 111 restores the preshortening
LDPC code Nldpc (Fig. 6) from the postshortening
LDPC code Npost supplied from the QAM decoder
44, and supplies the restored LDPC code to the LDPC
decoder 46.
15 [0129]
In the transmission device of Fig. 5, the scrambler
101 (Fig. 5) scrambles the post-padding control data Kbch,
and the shortening unit 24 (Fig. 5) shortens the LDPC
code Nldpc to the LDPC code Npost by deleting the scrambled
20 dummy data from the LDPC code Nldpc of the BCH code Kldpc
of the scrambled post-padding control data ~ b ~ h (an~d)
puncturing the parity bits of the LDPC code Nldpc, as
described above with reference to Fig. 6.
[0130]
25 Therefore, to restore the original (pre-shortening)
LDPC code Nldpc from the LDPC code Npost shortened in the
above manner, the post-shortening LDPC code Npost needs to
be padded with scrambled dummy data, instead of dummy
data.
30 [0131]
Specifically, since the post-padding control data
Kbch is not scrambled in the transmission device of Fig. 1,
the pre-shortening LDPC code Nldpc (Fig. 3) is restored
from the post-shortening LDPC code Npost (Fig. 3) by
performing padding with zeros as dummy data in the
5 reception device (Fig. 4) that receives data from the
transmission device.
[0132]
In the transmission device of Fig. 5, on the other
hand, scrambling is performed on the post-padding control
10 data Kbch, SO as to improve the PAPR of the control data.
Therefore, when the pre-shortening LDPC code Nldpc (Fig.
6) is restored from the post-shortening LDPC code NpOst
(Fig. 6) in the reception device (Fig. 7) that receives
data from the transmission device, the scrambled dummy
15 data contained in the pre-shortening LDPC code Nldpc is
generated from the dummy data, and padding then needs to
be performed on the scrambled dummy data.
[0133]
In view of this, to restore the pre-shortening LDPC
20 code Nldpc (Fig. 6) from the post-shortening LDPC code
Npost (Fig. 6) in the reception device of Fig. 7, the
restoration unit 111 needs to additionally perform an
operation to generate the scrambled dummy data. This
operation is not performed by the restoration unit 45 of
25 the reception device of Fig. 4.
[0134]
The restoration unit 111 generates the scrambled
dummy data, and then restores the pre-shortening LDPC
code Nldpc (Fig. 6) by padding the post-shortening LDPC
30 code NpOst from the QAM decoder 44 with the scrambled
dummy data and depuncturing the parity bits of the LDPC
code. The restored LDPC code is supplied to the LDPC
decoder 46.
[0135]
The LDPC decoder 46 performs LDPC decoding on the
5 LDPC code Nldpc supplied from the restoration unit 111,
and supplies the resultant BCH code Kldpc (Fig. 6) to the
BCH decoder 47.
[0136]
The BCH decoder 47 performs BCH decoding on the BCH
10 code Kldpc supplied from the LDPC decoder 46, and supplies
the resultant scrambled post-padding control data Kbch(s)
(Fig. 6) to the descrambler 112.
[0137]
The descrambler 112 performs descrambling (inverse
15 energy diffusion) on the scrambled post-padding control
data ~ b ~ ~su'pp~li'ed from the BCH decoder 47, to obtain
the control data Kbch padded with zeros as dummy data (the
post-padding control data). The post-padding control
data Kbch is supplied to the deletion unit 48.
20 [0138]
The deletion unit 48 deletes the zeros as the dummy
data from the post-padding control data Kbch, and supplies
the resultant control data Ksig (Fig. 6) to a control unit
49.
25 [0139]
As described above, in a case where scrambling is
performed on the post-padding control data Kbch in the
transmission device of Fig. 5, the reception device (Fig.
7) that receives data from the transmission device needs
30 not only to perform descrambling to cancel the scrambling,
but also to generate the scrambled dummy data contained
in the pre-shortening LDPC code Nldpc from the dummy data,
to restore the pre-shortening LDPC code Nldpc (Fig. 6)
from the post-shortening LDPC code Npost (Fig. 6).
[0140]
5 Therefore, in the reception device of Fig. 7,
padding is performed with zeros as the dummy data, and
the restoration unit 45 (Fig. 4) that performs
depuncturing on the parity bits of the LDPC code needs to
be replaced with the restoration unit 111 that performs a
10 different operation from that of the restoration unit 45,
or with the restoration unit 111 that generates the
scrambled dummy data, performs padding with the scrambled
dummy data, and performs depuncturing on the parity bits
of the LDPC code.
15 [0141]
[Second Example Structure of a Transmission Device That
Transmits Data After Scrambling Control Data]
[0142]
Fig. 8 is a block diagram showing a second example
20 structure of a transmission device that transmits data
after scrambling control data.
[0143]
In the drawing, the components equivalent to those
of the transmission device of Fig. 1 or 5 are denoted by
25 the same reference numerals as those used in Fig. 1 or 5,
and explanation of them will not be repeated.
[0144]
The transmission device of Fig. 8 is the same as
the transmission device of Fig. 1 in including a mode
30 adaptation/multiplexer 11 through an OFDM generation unit
28.
[01451
However, the transmission device of Fig. 8 differs
from the transmission device of Fig. 1 in further
including the scrambler 101 described with reference to
5 Fig. 5 in a stage before the padder 21.
[0146]
The control data of the predetermined length is
supplied to the scrambler 101.
[0147]
10 The scrambler 101 performs scrambling on the
control data supplied thereto, and outputs the scrambled
control data.
[01481
The scrambled control data output from the
15 scrambler 101 is supplied to the padder 21, and the same
operations as those in the transmission device of Fig. 1
are then performed at the padder 21, the BCH encoder 22,
the LDPC encoder 23, and the shortening unit 24.
[0149]
20 Fig. 9 is a diagram for explaining operations of
the scrambler 101, the padder 21, the BCH encoder 22, the
LDPC encoder 23, and the shortening unit 24 shown in Fig.
8.
[ 0 15 0 1
25 The control data Ksig of the predetermined length is
supplied to the scrambler 101.
[0151]
The scrambler 101 performs scrambling on the
control data Kbch supplied thereto, and supplies the
30 scrambled control data KSig") to the padder 21.
[0152]
The padder 21 pads the scrambled control data K ~ ~ ~ ( ~ )
supplied from the scrambler 101 with a required number of
zeros as dummy data.
[0153]
5 Here, the data obtained by padding the scrambled
control data with zeros as the dummy data is also
called post-padding scrambled data.
[0154]
The post-padding scrambled data Kbch obtained by
10 padding the scrambled control data Ksiq'" with zeros as
the dummy data at the padder 21 is supplied to the BCH
encoder 22.
[0155]
The BCH encoder 22 performs BCH encoding as error
15 correction encoding on the post-padding scrambled data
Kbch supplied from the padder 21, and supplies the
resultant BCH code Kldpc to the LDPC encoder 23.
[0156]
Specifically, the BCH encoder 22 determines the BCH
20 code parity bits for the post-padding scrambled data Kbch,
and adds the parity bits to the post-padding scrambled
data Kbch, to obtain the BCH code Kldpc of the post-padding
scrambled data Kbch, as in the case described with
reference to Fig. 3.
25 [0157]
The LDPC encoder 23 performs LDPC encoding as error
correction encoding on the BCH code Kldpc of the postpadding
scrambled data Kbch supplied from the BCH encoder
22, and supplies the resultant LDPC code Nldpc to the
30 shortening unit 24.
[0158]
Specifically, the LDPC encoder 23 determines the
LDPC code parity bits for the BCH code Kldpc of the postpadding
scrambled data Kbch, and adds the parity bits to
the BCH code Kldpc, to obtain the LDPC code Nldpc of the
5 BCH code Kldpc, as in the case described with reference to
Fig. 3.
[01591
The shortening unit 24 performs shortening by
deleting the dummy data from the LDPC code Nldpc supplied
10 from the LDPC encoder 23 and puncturing the parity bits
of the LDPC code Nldpcr and supplies the post-shortening
LDPC code Npost to the QAM encoder 25.
[0160]
[Second Example Structure of a Reception Device That
15 Receives Data From a Transmission Device That Transmits
Data After Scrambling Control Data]
[0161]
Fig. 10 is a block diagram showing an example
structure of a reception device that receives data from
20 the transmission device that is shown in Fig. 8 and
transmits data after scrambling control data.
[0162]
In the drawing, the components equivalent to those
of the reception device of Fig. 4 or 7 are denoted by the
25 same reference numerals as those used in Fig. 4 or 7, and
explanation of them will not be repeated.
[0163]
The reception device of Fig. 10 is the same as the
reception device of Fig. 4 in including an OFDM operation
30 unit 31 through a control unit 49.
[0164]
However, the reception device of Fig. 10 differs
from the reception device of Fig. 4 in that the
descrambler 112 described with reference to Fig. 7 is
newly provided between the deletion unit 48 and the
5 control unit 49.
[0165]
In the reception device of Fig. 10, the QAM decoder
44 outputs the post-shortening LDPC code Npost (Fig. 9),
and the post-shortening LDPC code NpOst is supplied to the
10 restoration unit 45, as in the reception device of Fig. 4.
[0166]
The restoration unit 45 restores the pre-shortening
LDPC code Nldpc (Fig. 9) from the post-shortening LDPC
code Npost supplied from the QAM decoder 44, and supplies
15 the restored LDPC code to the LDPC decoder 46.
[0167]
In the transmission device of Fig. 8, the scrambler
101 (Fig. 8) scrambles the control data Ksigr and the
padder 21 (Fig. 8) pads the scrambled control data K ~ ~ ~ ( ~ )
20 with zeros as the dummy data, to obtain the post-padding
scrambled data Kbch, as described with reference to Fig. 9.
[0168]
The shortening unit 24 (Fig. 8) then shortens the
LDPC code Nldpc to the LDPC code NpOst by deleting the
25 durruny data from the LDPC code Nldpc of the BCH code Kldpc
of the post-padding scrambled data Kbch, and puncturing
the parity bits of the LDPC code Nldpc.
[0169]
Therefore, the original (pre-shortening) LDPC code
30 Nldpc can be restored from the LDPC code Npost shortened in
the above manner, by performing the same operation as
that in the reception device of Fig. 4, or padding the
post-shortening LDPC code Npost with the dummy data (and
depuncturing the parity bits of the LDPC code).
[0170]
5 The LDPC decoder 46 performs LDPC decoding on the
LDPC code Nldpc supplied from the restoration unit 45, and
supplies the resultant BCH code Kldpc (Fig. 9) to the BCH
decoder 47.
[0171]
10 The BCH decoder 47 performs BCH decoding on the BCH
code Kldpc supplied from the LDPC decoder 46, and supplies
the resultant post-padding scrambled data Kbch (Fig. 9) to
the deletion unit 48.
[0172]
15 The deletion unit 48 deletes the zeros as the dummy
data from the post-padding scrambled data Kbchr and
supplies the resultant scrambled control data K,~~"' (Fig.
9) to the descrambler 112.
[0173]
20 The descrambler 112 performs descrambling on the
scrambled control data K,~,"' supplied from the deletion
unit 48, and obtains the original control data Ksigf which
is then supplied to the control unit 49.
[0174]
25 As described above, in the transmission device of
Fig. 8, scrambling is performed on the control data Ksig
to improve the PAPR, the scrambled control data is
padded with the dummy data, BCH encoding and LDPC
encoding are performed as error correction encoding on
30 the post-padding scrambled data Kbch obtained by padding
the scrambled control data KSig"' with the dummy data, and
shortening is performed by deleting the dummy data from
the LDPC code obtained through the BCH encoding and the
LDPC encoding and puncturing the parity bits of the LDPC
code. In that case, the reception device (Fig. 10) that
5 receives data from the transmission device performs the
same operations as those of the reception device (Fig. 4)
that receives data from the transmission device (Fig. 1)
that transmits data without scrambling the control data.
Accordingly, the pre-shortening LDPC code Nldpc (Fig. 9)
10 can be restored from the post-shortening LDPC code NpOst.
Thus, by using the reception device of Fig. 4, which is
compliant with DVB-T.2, for example, the control data
having the improved PAPR can be readily processed
(demodulated) .
15 [0175]
[Third Example Structure of a Transmission Device That
Transmits Data After Scrambling Control Data]
[0176]
Fig. 11 is a block diagram showing a third example
20 structure of a transmission device that transmits data
after scrambling control data.
[0177]
In the drawing, the components equivalent to those
of the transmission device of Fig. 1, 5, or 8 are denoted
25 by the same reference numerals as those used in Fig. 1, 5,
or 8, and explanation of them will not be repeated.
101781
The transmission device of Fig. 11 is the same as
the transmission device of Fig. 1 in including a mode
30 adaptation/multiplexer 11 through an OFDM generation unit
28.
[0179]
However, the transmission device of Fig. 11 differs
from the transmission device of Fig. 1 in that the
scrambler 101 described with reference to Figs. 5 and 8
5 and a replacement unit 121 are newly provided between the
padder 21 and the BCH encoder 22.
[0180]
In Fig. 11, the padder 21 pads control data with
dummy data, and supplies the resultant post-padding
10 control data to the scrambler 101.
[0181]
The scrambler 101 performs scrambling on the postpadding
control data supplied from the padder 21, and
supplies the scrambled post-padding control data to the
15 replacement unit 121.
[0182]
The replacement unit 121 replaces the scrambled
dummy data in the scrambled post-padding control data
from the scrambler 101 with the dummy data, and supplies
20 the replacement data obtained through the replacement to
the BCH encoder 22.
[0183]
The same operations as those in the transmission
device of Fig. 1 are then performed at the BCH encoder 22,
25 the LDPC encoder 23, and the shortening unit 24.
[0184]
Fig. 12 is a diagram for explaining operations of
the padder 21, the scrambler 101, the replacement unit
121, the BCH encoder 22, the LDPC encoder 23, and the
30 shortening unit 24 shown in Fig. 11.
[0185]
The control data Ksi, of the predetermined length is
supplied to the padder 21.
[01861
The padder 21 pads the control data Ksig supplied
5 thereto with a required number of zeros as dummy data,
and supplies the post-padding control data Kbch, which is
the padded control data, to the scrambler 101.
[0187]
The scrambler 101 performs scrambling on the post-
10 padding control data Kbch supplied from the padder 21, and
supplies the scrambled post-padding control data ~ b ~ h (t~o )
the replacement unit 121.
[0188]
The replacement unit 121 replaces the scrambled
15 dummy data in the scrambled post-padding control data
K ~ ~ f~ro'm ~th'e scrambler 101 with zeros that are the
dummy data, and supplies the replacement data K ~ ~ ~ ( ~ )
obtained through the replacement to the BCH encoder 22.
[0189]
20 The BCH encoder 22 performs BCH encoding as error
correction encoding on the replacement data Kbch(*)
supplied from the replacement unit 121, and supplies the
resultant BCH code Kldpc to the LDPC encoder 23.
[0190]
25 Specifically, the BCH encoder 22 determines the BCH
code parity bits for the replacement data K ~ ~ ~a(nd~ )ad,ds
the parity bits to the replacement data to obtain
the BCH code Kldpc of the replacement data K ~ ~ a~s i(n ~ ' ~
the case described with reference to Fig. 3.
30 [0191]
The LDPC encoder 23 performs LDPC encoding as error
correction encoding on the BCH code Kldpc of the
replacement data K ~ ~ ~su'pp~li'ed from the BCH encoder 22,
and supplies the resultant LDPC code Nldpc to the
shortening unit 24.
5 [0192]
Specifically, the LDPC encoder 23 determines the
LDPC code parity bits for the BCH code Kldpc of the
replacement data ~b~h'~a)nd, adds the parity bits to the
BCH code Kldpc, to obtain the LDPC code Nldpc of the BCH
10 code Kldpcr as in the case described with reference to Fig.
3 .
[0193]
The shortening unit 24 performs shortening by
deleting the dummy data from the LDPC code Nldpc supplied
15 from the LDPC encoder 23 and puncturing the parity bits
of the LDPC code Nldpcra nd supplies the post-shortening
LDPC code N,,,, to the QAM encoder 25.
[0194]
[Third Example Structure of a Reception Device That
20 Receives Data From a Transmission Device That Transmits
Data After Scrambling Control Data]
[0195]
Fig. 13 is a block diagram showing an example
structure of a reception device that receives data from
25 the transmission device that is shown in Fig. 11 and
transmits data after scrambling control data.
[0196]
In the drawing, the components equivalent to those
of the reception device of Fig. 4, 7, or 10 are denoted
30 by the same reference numerals as those used in Fig. 4, 7,
or 10, and explanation of them will not be repeated.
[0197]
The reception device of Fig. 13 is the same as the
reception device of Fig. 4 in including an OFDM operation
unit 31 through a control unit 49.
5 [0198]
However, the reception device of Fig. 13 differs
from the reception device of Fig. 4 in that the
descrambler 112 described with reference to Figs. 7 and
10 is newly provided between the BCH decoder 47 and the
10 deletion unit 48.
[0199]
In the reception device of Fig. 13, the QAM decoder
44 outputs the post-shortening LDPC code Npost (Fig. 12),
and the post-shortening LDPC code Npost is supplied to the
15 restoration unit 45, as in the reception device of Fig. 4.
[0200]
The restoration unit 45 restores the pre-shortening
LDPC code Nldpc (Fig. 12) from the post-shortening LDPC
code NpOst supplied from the QAM decoder 44, and supplies
20 the restored LDPC code to the LDPC decoder 46.
[0201]
In the transmission device of ' ~ i1~1,. t he padder
21 (Fig. 11) pads the control data Ksig with the dummy
data, and the scrambler 101 (Fig. 11) scrambles the post-
25 padding control data Kbch obtained through the padding, as
described with reference to Fig. 12. As a result, the
scrambled post-padding control data K ~ , ~ " ' is obtained.
[0202]
In the replacement unit 121, the scrambled dummy
30 data contained in the scrambled post-padding control data
~ b , h ' ~ ' is replaced with the dummy data. Shortening is
then performed to shorten the LDPC code Nldpc to the LDPC
code NpOst by deleting the dummy data from the LDPC code
Nldpc of the BCH code Kldpc of the replacement data ~ b , h ( ~ )
obtained through the replacement, and puncturing the
5 parity bits of the LDPC code Nldpc.
[0203]
Therefore, the original (pre-shortening) LDPC code
Nldpc can be restored from the LDPC code Npost shortened in
the above manner, by performing the same operation as
10 that in the reception device of Fig. 4, or padding the
post-shortening LDPC code Npost with the dummy data.
[0204]
The LDPC decoder 46 performs LDPC decoding on the
LDPC code Nldpc supplied from the restoration unit 45, and
15 supplies the resultant BCH code Kldpc (Fig. 12) to the BCH
decoder 47.
[0205]
The BCH decoder 47 performs BCH decoding on the BCH
code Kldpc supplied from the LDPC decoder 46, and supplies
20 the resultant replacement data KbCh'=' (Fig. 12) to the
descrambler 112.
[0206]
The descrambler 112 performs descrambling on the
replacement data ~ ) , , h ( ~ ' supplied from the BCH decoder 47,
25 and supplies the resultant data, which is the control
data padded with the descrambled dummy data (hereinafter
also referred to as the post-padding control data), to
the deletion unit 48.
[0207]
30 The deletion unit 48 deletes the descrambled dummy
data from the post-padding control data supplied from the
descrambler 112, and supplies the resultant control data
Ksig (Fig. 12) to the control unit 49.
[0208]
Here, the replacement data Kbch(*' (Fig. 12) supplied
5 from the BCH decoder 47 to the descrambler 112 contains
the dummy data used in the padding at the restoration
unit 45, and the descrambler 112 descrambles the
replacement data ~ ~ , h ( ~A'S. a result, the dummy data
contained in the replacement data Kbch'r' turns into the
10 descrambled dummy data.
[0209]
Accordingly, the post-padding control data obtained
by descrambling the replacement data ~ b , h ' ~ ' at the
descrarnbler 112 contains the descrambled dummy data.
15 That is, the post-padding control data obtained by
descrambling the replacement data ~ b , h ( ~ 'i s data formed by
padding the control data with the descrambled dummy data.
[0210]
The location of the descrambled dummy data
20 contained in the post-padding control data obtained by
descrambling the replacement data KbCh'*' is the same as
the location of the dummy data contained in the postpadding
control data Kbch shown in Fig. 3. Accordingly,
the deletion unit 48 of the reception device of Fig. 13
25 can delete the descrambled dummy data from the postpadding
control data supplied from the descrambler 112,
by performing the same operation as that performed by the
deletion unit 48 of the reception device of Fig. 4.
[0211]
30 As described above, in the transmission device of
Fig. 11, the control data Ksig is padded with the dummy
data, scrambling to improve the PAPR is performed on the
post-padding control data Kbch that is the padded control
data, the scrambled dummy data in the scrambled postpadding
control data is replaced with the dummy
5 data, BCH encoding and LDPC encoding are performed as
error correction encoding on the replacement data ~b,h(=)
obtained through the replacement, and shortening is
performed by deleting the dummy data from the LDPC code
obtained through the BCH encoding and the LDPC encoding
10 and puncturing the parity bits of the LDPC code. In that
case, the reception device (Fig. 13) that receives data
from the transmission device performs the same operations
as those of the reception device (Fig. 4) that receives
data from the transmission device (Fig. 1) that transmits
15 data without scrambling the control data. Accordingly,
the pre-shortening LDPC code Nldpc (Fig. 9) can be
restored from the post-shortening LDPC code NpOst. Thus,
by using the reception device of Fig. 4, which is
compliant with DVB-T.2, for example, the control data
20 having the improved PAPR can be readily processed
(demodulated) .
[0212]
In the reception device of Fig. 13 (as well as in
the reception device of Fig. 4), the control unit 49
25 might include an interface that receives not mere control
data but control data padded with (descrambled) dummy
data (the post-padding control data). In that case,
there is no need to include the deletion unit 48, and the
reception device can be made smaller in size.
30 [0213]
[Example Structure of the Scrambler 1011
[0214]
Fig. 14 is a block diagram showing an example
structure of the scrambler 101 (Figs. 5, 8, and 11).
[0215]
5 The scrambler 101 includes a register group 201 and
EXOR circuits 202 and 203.
[0216]
The register group 201 includes fifteen registers
#1 through #IS, and each register #i is synchronized with
10 (the respective bits of) data to be scrambled, and
latches the bits latched by the register #i-1 of the
previous stage.
[0217]
An output of the EXOR circuit 202 is supplied to
15 the first (top) register #1 of the register group 201,
and the register #1 latches the output of the EXOR
circuit 202.
[0218]
The EXOR circuit 202 (the first EXOR circuit)
20 calculates the exclusive OR between the bits latched by
the fourteenth register #14 and the bits latched by the
fifteenth register #15 among the registers #1 through #15
of the register group 201, for example, and supplies the
calculation result to the first register #1 of the
25 register group 201 and the EXOR circuit 203.
[0219]
The data to be scrambled (the control data (Fig.
8)) or the post-padding control data (Fig. ll), as well
as the output of the EXOR circuit 202 (the result of the
30 exclusive OR operation performed on the bits latched by
the fourteenth register #14 and the bits latched by the
fifteenth register #15), is supplied to the EXOR circuit
203.
[0220]
The EXOR circuit 203 (the second EXOR circuit)
5 calculates the exclusive OR between the output of the
EXOR circuit 202 and the data to be scrambled, and
outputs the calculation result as the scrambled data.
[0221]
At the scrambler 101 having the above described
10 structure, the bits 1, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0,
0, and 0, for example, are set as the initial values in
the first through fifteenth registers #1 through #15 of
the register group 201, respectively.
[0222]
15 After that, each register #i of the register group
201, except for the first register #I, is synchronized
with the data to be scrambled, and latches the bits
latched by the register #i-1 of the previous stage.
[0223]
20 Meanwhile, the first register #1 of the register
group 201 latches the output of the EXOR circuit 202.
[0224]
The EXOR circuit 202 calculates the exclusive OR
between the bits latched by the fourteenth register #14
25 and the bits latched by the fifteenth register #15, and
supplies (the bits forming) the M-sequence obtained as a
result of the calculation to the first register #1 of the
register group 201 and the EXOR circuit 203.
[0225]
30 The EXOR circuit 203 calculates the exclusive OR
between the M-sequence supplied from the EXOR circuit 202
and the data to be scrambled. In this manner, the data
to be scrambled is scrambled, and the scrambled data is
output.
[0226]
5 It should be noted that the descrambler 112 of each
of the reception devices (Figs. 7, 10, and 13) has the
same structure as the scrambler 101.
[0227]
[Formats of Bit Streams According to the New Standards]
10 [0228]
Fig. 15 is a diagram showing a first example format
of a bit stream of an OFDM signal to be transmitted by a
transmission device that scrambles control data and is
compliant with the new standards, like the transmission
15 device shown in Fig. 5, 8, or 11.
[0229]
In Fig. 15, a bit stream of an OFDM signal to be
transmitted by the transmission device compliant with the
new standards is formed with new frames.
20 [0230]
In the new standards, a new frame is a frame as a
unit for data transmission. In Fig. 15, T2 frames
specified in existing standards such as DVB-T.2 are used
as the new frames.
25 [0231]
Accordingly, like the T2 frames described with
reference to Fig. 2, each new frame is formed with a PI
symbol, P2 symbols, and data symbols (symbols called
"Normal" and symbols called "FC") that are arranged in
30 this order.
[0232]
In this case, a reception device that processes
(OFDM signals of) the new frames and is compliant with
the new standards can be formed with a reception device
compliant with DVB-T.2 (simply by making small changes to
5 the specification of a reception device compliant with
DVB-T.2).
[0233]
As described with reference to Fig. 2, the S1 and
S2 contained in the P1 symbol that is the preamble placed
10 at the top of each T2 frame contain frame identification
information indicating that the frame is a T2 frame. On
the other hand, the S1 and S2 contained in the PI symbol
of each new frame contain frame identification
information indicating that the frame is a new frame.
15 [0234]
In this case, the reception device that receives
OFDM signals can determine whether each frame is a T2
frame or a new frame, from the frame identification
information contained in the S1 and S2 contained in the
20 PI symbol of each frame.
[0235]
Fig. 16 is a diagram showing a second example
format of a bit stream of an OFDM signal to be
transmitted by a transmission device that scrambles
25 control data and is compliant with the new standards,
like the transmission device shown in Fig. 5, 8, or 11.
[0236]
In Fig. 16, a bit stream of an OFDM signal to be
transmitted by the transmission device compliant with the
30 new standards is formed with T2 frames and new frames.
[0237]
Specifically, in Fig. 16, new frames are
multiplexed with T2 frames specified in DVB-T.2 in the
transmission device compliant with the new standards, and
are then transmitted.
5 [0238]
Here, the transmission device compliant with the
new standards, such as the transmission device shown in
Fig. 5, 8, or 11, includes the mode
adaptation/multiplexer 11 through the OFDM generation
10 unit 28 constituting the transmission device shown in Fig.
1, and therefore, T2 frames specified in DVB-T.2 can be
formed .
[0239]
In view of this, in the transmission device
15 compliant with the new standards, new frames and T2
frames are formed, and those new frames and T2 frames can
be (time-division) multiplexed and be transmitted.
[0240]
It should be noted that, in Fig. 16, T2 frames
20 specified in DVB-T.2 can be used as the new frames as in
the case illustrated in Fig. 15.
[0241]
As described with reference to Fig. 15, (the S1 and
S2 contained in) the PI symbol of each T2 frame contains
25 the frame identification information indicating that the
frame is a T2 frame, and the P1 symbol of each new symbol
contains the frame identification information indicating
that the frame is a new frame. Accordingly, the
reception device that receives OFDM signals can determine
30 whether each frame is a T2 frame or a new frame, from the
frame identification information contained in the PI
symbol of each frame.
[0242]
[Description of a Computer to Which the Present Invention
Is Applied]
5 [0243]
The above described series of operations can be
performed with hardware, and can also be performed with
software. Where the series of operations are performed
with software, a program that forms the software is
10 installed into a general-purpose computer or the like.
[0244]
Fig. 17 shows an example structure of an embodiment
of a computer into which the program for performing the
above described series of operations is installed.
15 [0245]
The program can be recorded beforehand in a hard
disk 305 or a ROM 303 provided as a recording medium in
the computer.
[0246]
20 Alternatively, the program can be stored (recorded)
in a removable recording medium 311. Such a removable
recording medium 311 can be provided as so-called
packaged software. Here, the removable recording medium
311 may be a flexible disk, a CD-ROM (Compact Disc Read
25 Only Memory), an MO (Magneto Optical) disk, a DVD
(Digital Versatile Disc), a magnetic disk, or a
semiconductor memory, for example.
[0247]
Instead of being installed from the above described
30 removable recording medium 311 into the computer, the
program can be downloaded into the computer via a
communication network or a broadcasting network, and be
installed into an internal hard disk 305. Specifically,
the program can be wirelessly transferred from a download
site to the computer via an artificial satellite for
5 digital satellite broadcasting, or be transferred through
a cable to the computer via a network such as a LAN
(Local Area Network) or the Internet, for example.
[0248]
The computer includes a CPU (Central Processing
10 Unit) 302, and an input/output interface 310 is connected
to the CPU 302 via a bus 301.
LO2491
When an instruction is input by a user operating an
input unit 307 via the input/output interface 310, the
15 CPU 302 executes a program stored in the ROM (Read Only
Memory) 303 in accordance with the instruction.
Alternatively, the CPU 302 loads a program stored in the
hard disk 305 into a RAM (Random Access Memory) 304, and
then executes the program.
20 [0250]
By doing so, the CPU 302 performs the operations
according to the above described flowcharts, or performs
the operations using the structures illustrated in the
above described block diagrams. Where necessary, the CPU
25 302 outputs the operation results from an output unit 306
or transmits the operation results from the communication
unit 308 via the input/output interface 310, for example,
and further stores the operation results into the hard
disk 305.
30 [0251]
The input unit 307 is formed with a keyboard, a
mouse, a microphone, and the like. The output unit 306
is formed with an LCD (Liquid Crystal Display), a speaker,
and the like.
[0252]
5 In this specification, the processing steps to be
carried out by a computer according to a program are not
necessarily carried out in chronological order in
accordance with the sequence described as the flowcharts.
That is, the processing steps to be carried out by a
10 computer according to a program include procedures to be
carried out in parallel or independently of one another
(such as parallel procedures or object-based procedures).
[0253]
The program may be executed by one computer
15 (processor), or may be executed in a distributive manner
by more than one computer. Further, the program may be
transferred to a remote computer, and be executed therein.
[0254]
It should be noted that embodiments of the present
20 invention are not limited to the above described
embodiments, and various modifications may be made to
them without departing from the scope of the invention.
[0255]
Specifically, the T2 frame format is used as the
25 new frame format in this embodiment, but a format other
than the T2 frame format may be used as a new frame
format.
REFERENCE SIGNS LIST
30 [0256]
11 Mode adaptation/multiplexer, 12 Padder, 13 BB
scrambler, 14 BCH encoder, 15 LDPC encoder, 16 Bit
interleaver, 17 QAM encoder, 18 Time interleaver, 19
SISO/MISO encoder, 20 Frequency interleaver, 21 Padder,
22 BCH encoder, 23 LDPC encoder, 24 Shortening unit, 25
5 QAM encoder, 26 Frequency interleaver, 27 Frame
builder/resource allocation unit, 28 OFDM generation unit,
31 OFDM operation unit, 32 Frame management unit, 33
Frequency deinterleaver, 34 SISO/MISO decoder, 35 Time
deinterleaver, 36 QAM decoder, 37 Bit deinterleaver, 38
10 LDPC decoder, 39 BCH decoder, 40 BB descrambler, 41 Null
deletion unit, 42 Demultiplexer, 43 Frequency
deinterleaver, 44 QAM decoder, 45 Restoration unit, 46
LDPC decoder, 47 BCH decoder, 48 Deletion unit, 49
Control unit, 101 Scrambler, 111 Restoration unit, 112
15 Descrambler, 121 Replacement unit, 201 register group,
202, 203 EXOR circuit, 301 Bus, 302 CPU, 303 ROM, 304 RAM,
305 Hard disk, 306 Output unit, 307 Input unit, 308
Communication unit, 309 Drive, 310 Input/output interface,
311 Removable recording medium
20

CLAIMS
1. A data processing device comprising:
a padding means that pads control data with dummy
5 data, the control data being necessary for demodulation;
a scrambling means that scrambles post-padding
control data, the post-padding control data being the
padded control data;
a replacement means that generates replacement data
10 by replacing scrambled dummy data in the scrambled postpadding
control data with the dummy data; and
an error correction encoding means that performs
error correction encoding on the replacement data.
2. A data processing device comprising:
a scrambling means that scrambles control data
necessary for demodulation;
a padding means that pads the scrambled control
data with dummy data; and
an error correction encoding means that performs
error correction encoding on post-padding scrambled data
formed by padding the scrambled control data with the
dummy data.
25 3. The data processing device according to claim 1 or
2, wherein the error correction encoding means determines
a parity bit for data to be subjected to the error
correction encoding, and adds the parity bit to the data
to be subjected to the error correction encoding, to
30 obtain an error correcting code,
the data processing device further comprising
a shortening means that performs shortening by
deleting the dummy data from the error correcting code
and puncturing a parity bit of the error correcting code.
5 4. The data processing device according to claim 1 or
2, wherein the padding means performs the padding with
the dummy data, to adjust a data length of padded data to
a target data length of the error correction encoding.
10 5. The data processing device according to claim 1 or
2, wherein
the scrambling means includes:
a register group formed with fifteen registers
connected in series, a register in a later stage latching
15 bits latched by a register in a previous stage;
a first EXOR circuit that calculates an exclusive
OR between bits latched by a fourteenth register and bits
latched by a fifteenth register; and
a second EXOR circuit that calculates an exclusive
20 OR between an output of the first EXOR circuit and data
to be scrambled, and outputs a result of the calculation
as scrambled data,
a first register of the register group latches the
output of the first EXOR circuit, and
25 b i t s 1 , 0 , 0 , 1 , 0 , 1 , 0 , 1 , 0 , 0 , 0 , 0 , 0 , 0 , a n d
0 are set as initial values in the first through
fifteenth registers of the register group, respectively.
6. The data processing device according to claim 1 or
30 2, wherein the control data is one of:
first data necessary for demodulating actual data;
second data necessary for demodulating the first
data; and
the first and second data.
5 7. The data processing device according to claim 1 or
2, wherein a new frame containing the error correcting
code obtained through the error correction encoding is
multiplexed with a T2 frame specified in DVB-T.2 and is
transmitted.
10
8. The data processing device according to claim 1 or
2, wherein
a preamble is placed at the top of each of the T2
frame and the new frame,
15 the preamble of the T2 frame contains information
identifying the T2 frame, and
the preamble of the new frame contains information
identifying the new frame.
20 9. A data processing method comprising the steps of:
padding control data with dummy data, the control
data being necessary for demodulation;
scrambling post-padding control data, the postpadding
control data being the padded control data;
25 generating replacement data by replacing scrambled
dummy data in the scrambled post-padding control data
with the dummy data;. and
performing error correction encoding on the
replacement data.
30
10. A data processing method comprising the steps of:
scrambling control data necessary for demodulation;
padding the scrambled control data with dummy data;
and
performing error correction encoding on post-
5 padding scrambled data formed by padding the scrambled
control data with the dummy data.
11. A data processing device comprising:
an error correction means that performs error
10 correction to decode an error correcting code into
replacement data, the error correcting code being
obtained by a transmission device; and
a descrambling means that descrambles the
replacement data,
15 the transmission device padding control data
necessary for demodulation with dummy data,
scrambling post-padding control data that is the
padded control data,
generating the replacement data by replacing
20 scrambled dummy data in the scrambled post-padding
control data with the dummy data, and
performing error correction encoding on the
replacement data.
25 12. A data processing device comprising:
an error correction means that performs error
correction to decode an error correcting code into postpadding
scrambled data, the error correcting code being
obtained by a transmission device;
30 a deletion means that deletes dummy data from the
post-padding scrambled data, and outputs scrambled
control data; and
a descrambling means that descrambles the scrambled
control data,
the transmission device scrambling control data
5 necessary for demodulation,
padding the scrambled control data with the dummy
data, and
performing error correction encoding on the postpadding
scrambled data formed by padding the scrambled
10 control data with the dummy data.
13. The data processing device according to claim 11 or
12, wherein
the transmission device performs shortening by
15 deleting the dummy data from the error correcting code
obtained through the error correction encoding and
puncturing a parity bit of the error correcting code,
the data processing device further comprising
a restoration means that restores a pre-shortening
20 error correcting code by padding the post-shortening
error correcting code obtained by the transmission device
with the dummy data, and depuncturing the parity bit.
14. The data processing device according to claim 11,
25 further comprising
a deletion means that deletes descrambled dummy
data from the descrambled replacement data.
15. The data processing device according to claim 13,
30 wherein the padding with the dummy data is performed to
adjust a data length of padded data to a target data
length of the error correction encoding.
16. The data processing device according to claim 13,
wherein the scrambling is performed by a scrambling means,
5 the scrambling means including:
a register group formed with fifteen registers
connected in series, a register in a later stage latching
bits latched by a register in a previous stage;
a first EXOR circuit that calculates an exclusive
10 OR between bits latched by a fourteenth register and bits
latched by a fifteenth register; and
a second EXOR circuit that calculates an exclusive
OR between an output of the first EXOR circuit and data
to be scrambled, and outputs a result of the calculation
15 as scrambled data,
a first register of the register group latching the
output of the first EXOR circuit,
b i t s 1 , 0 , 0 , 1 , 0 , 1 , 0 , 1 , 0 , 0 , 0 , 0 , 0 , 0 , a n d
0 being set as initial values in the first through
20 fifteenth registers of the register group, respectively.
17. The data processing device according to claim 13,
wherein the control data is one of:
first data necessary for demodulating actual data;
25 second data necessary for demodulating the first
data; and
the first and second data.
18. The data processing device according to claim 13,
30 wherein a new frame containing the error correcting code
obtained through the error correction encoding is
multiplexed with a T2 frame specified in DVB-T.2 and is
transmitted.
19. The data processing device according to claim 13,
5 wherein
a preamble is placed at the top of each of the T2
frame and the new frame,
the preamble of the T2 frame contains information
identifying the T2 frame, and
10 the preamble of the new frame contains information
identifying the new frame.
20. A data processing method comprising the steps of:
performing error correction to decode an error
15 correcting code into replacement data, the error
correcting code being obtained by a transmission device;
and
descrambling the replacement data,
the transmission device padding control data
20 necessary for demodulation with dummy data,
scrambling post-padding control data that is the
padded control data,
generating the replacement data by replacing
scrambled dummy data in the scrambled post-padding
25 control data with the dummy data, and
performing error correction encoding on the
replacement data.
21. A data processing method comprising the steps of:
performing error correction to decode an error
correcting code into post-padding scrambled data, the
a
SP315070W000
error correcting code being obtained by a transmission
device;
deleting dummy data from the post-padding scrambled
data, to output scrambled control data;-and
5 descrambling the scrambled control data,
the transmission device scrambling control data
necessary for demodulation,
padding the scrambled control data with the dummy
data, and
I 10 performing error correction encoding on the postpadding
scrambled data formed by padding the scrambled
control data with the dummy data.