Claims:1. An apparatus comprising:
protocol circuitry to implement a protocol stack of a particular interconnect protocol, wherein the protocol circuitry is to generate a set of ordered sets defined according to the particular interconnect protocol, the set of ordered sets is generated for a link to couple a first device to a second device, and the set of ordered sets comprises link information for the link; and
translation layer circuitry to:
generate, from the set of ordered sets, at least one data structure to comprise at least a portion of the link information; and
cause the data structure to be sent from the first device to the second device on the link in lieu of the set of ordered sets.
, Description:FIELD
[0001] This disclosure pertains to computing system, and in particular (but not exclusively) to training for point-to-point interconnects.

BACKGROUND
[0002] Advances in semi-conductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a corollary, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple cores, multiple hardware threads, and multiple logical processors present on individual integrated circuits, as well as other interfaces integrated within such processors. A processor or integrated circuit typically comprises a single physical processor die, where the processor die may include any number of cores, hardware threads, logical processors, interfaces, memory, controller hubs, etc.
[0003] As a result of the greater ability to fit more processing power in smaller packages, smaller computing devices have increased in popularity. Smartphones, tablets, ultrathin notebooks, and other user equipment have grown exponentially. However, these smaller devices are reliant on servers both for data storage and complex processing that exceeds the form factor. Consequently, the demand in the high-performance computing market (i.e. server space) has also increased. For instance, in modern servers, there is typically not only a single processor with multiple cores, but also multiple physical processors (also referred to as multiple sockets) to increase the computing power. Servers may also be implemented using distributed computing, in rack scale architectures, and other alternative implementations. As the processing power grows along with the number of devices in a computing system, the communication between sockets and other devices becomes more critical.
[0004] In fact, interconnects have grown from more traditional multi-drop buses that primarily handled electrical communications to full blown interconnect architectures that facilitate fast communication. Unfortunately, as the demand for future processors to consume at even higher-rates corresponding demand is placed on the capabilities of existing interconnect architectures.

BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1 illustrates an embodiment of a computing system including an interconnect architecture.
[0006] FIG. 2 illustrates an embodiment of a interconnect architecture including a layered stack.
[0007] FIG. 3 illustrates an embodiment of a request or packet to be generated or received within an interconnect architecture.
[0008] FIG. 4 illustrates an embodiment of a transmitter and receiver pair for an interconnect architecture.
[0009] FIGS. 5A-5C are simplified block diagrams of ports connected by example link topologies.
[0010] FIGS. 6A-6B are simplified block diagrams of example devices connected by links enabled by example translation layers.
[0011] FIGS. 7A-7B are simplified block diagrams illustrating operation of example translation layers.
[0012] FIGS. 8A-8C are simplified block diagrams illustrating communication of example data structures over the media of example physical connections.
[0013] FIG. 9 is a simplified block diagram of an example computing device connected to one or more different devices by respective example links.
[0014] FIG. 10 illustrates an embodiment of a block diagram for a computing system including a multicore processor.
[0015] FIG. 11 illustrates an embodiment of a block for a computing system including multiple processors.

DETAILED DESCRIPTION
[0016] In the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and micro architectural details, specific register configurations, specific instruction types, specific system components, specific measurements/heights, specific processor pipeline stages and operation etc. in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well known components or methods, such as specific and alternative processor architectures, specific logic circuits/code for described algorithms, specific firmware code, specific interconnect operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expression of algorithms in code, specific power down and gating techniques/logic and other specific operational details of computer system haven’t been described in detail in order to avoid unnecessarily obscuring the present invention.