Abstract: Systems, apparatuses and methods may provide for technology that in response to an identification that one or more hardware units are to execute on a first type of data format, decomposes a first original floating point number to a plurality of first segmented floating point numbers that are to be equivalent to the first original floating point number. The technology may further in response to the identification, decompose a second original floating point number to a plurality of second segmented floating point numbers that are to be equivalent to the second original floating point number. The technology may further execute a multiplication operation on the first and second segmented floating point numbers to multiply the first segmented floating point numbers with the second segmented floating point numbers.
Claims:1. A computing system comprising:
a host processor, the host processor including a plurality of accelerators that are to execute on a first data format; and
a memory coupled to the host processor, the memory including executable program instructions, which when executed by the host processor, cause the computing system to:
in response to an identification that the accelerators execute on the first type of data format, decompose a first original floating point number to a plurality of first segmented floating point numbers that are to be equivalent to the first original floating point number;
in response to the identification, decompose a second original floating point number to a plurality of second segmented floating point numbers that are to be equivalent to the second original floating point number; and
execute, by one or more of the plurality of accelerators, a multiplication operation on the first and second segmented floating point numbers to multiply the first segmented floating point numbers with the second segmented floating point numbers.
, Description:TECHNICAL FIELD
[0001] Embodiments generally relate to operations related to multiplication technology. More particularly, embodiments relate to decomposing floating point numbers to execute multiplication (e.g., matrix multiplication) on existing hardware.
BACKGROUND
[0002] Many compute cycles in certain workloads (e.g., deep learning workload and/or neural network learning) may be spent performing matrix multiplications that consume data in some input type and produce a result in a possibly different output type. For example, deep learning workload and/or neural network learning may execute matrix multiplication to determine weights.
[0003] Because of area constraints, some hardware multiplication units may consume only a first type of data (e.g., brain floating point 16 format) as an input, while producing an output that is either the first type of data or a second type of data (e.g., float 32 format). The second type of data may be more precise than the first type of data. In some cases, the input is insufficient to generate a useful output due to the lower precision of the first type of data. To increase precision, the matrix multiplication may need to be adjusted to consume the second type of data as an input instead of the first type of data.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] The various advantages of the embodiments will become apparent to one skilled in the art by reading the following specification and appended claims, and by referencing the following drawings, in which:
[0005] FIG. 1 is an example of a process to decompose numbers to a different data format according to an embodiment;
[0006] FIG. 2 is a flowchart of an example of a method of executing multiplication according to an embodiment;
[0007] FIGs. 3A-3C are an example of a process of executing matrix multiplication according to an embodiment;
[0008] FIG. 4 is a flowchart of an example of a method of adjusting a granularity of matrix multiplication operations according to an embodiment;
[0009] FIG. 5 is an example of a process of number decomposition according to an embodiment;
[0010] FIG. 6 is a block diagram of an example of a computing system according to an embodiment;
[0011] FIG. 7 is an illustration of an example of a semiconductor apparatus according to an embodiment;
[0012] FIG. 8 is a block diagram of an example of a processor according to an embodiment; and
[0013] FIG. 9 is a block diagram of an example of a multi-processor based computing system according to an embodiment.
DESCRIPTION OF EMBODIMENTS
[0014] FIG. 1 illustrates a process 10 to decompose first and second numbers 12, 26 to a different data format to execute multiplication. In detail, process 10 may utilize existing hardware, which executes on a first type of data format, to process first and second numbers 12, 26 that are in a second data format. For example, the first type of data format may be brain floating point 16 (bfloat16) format and the second type of data format may be in a single-precision floating-point format (float32). Process 10 may therefore utilize existing hardware (e.g., a bfloat-only pipeline) to process data (e.g., float32) that would otherwise be incompatible with the existing hardware. As discussed in further detail below, a granularity of the process 10 may also be adjusted to balance performance of the hardware against the accuracy of the output.
| # | Name | Date |
|---|---|---|
| 1 | 202044010107-ABSTRACT [29-03-2022(online)].pdf | 2022-03-29 |
| 1 | 202044010107-FORM 1 [09-03-2020(online)].pdf | 2020-03-09 |
| 2 | 202044010107-CLAIMS [29-03-2022(online)].pdf | 2022-03-29 |
| 2 | 202044010107-DRAWINGS [09-03-2020(online)].pdf | 2020-03-09 |
| 3 | 202044010107-FER_SER_REPLY [29-03-2022(online)].pdf | 2022-03-29 |
| 3 | 202044010107-DECLARATION OF INVENTORSHIP (FORM 5) [09-03-2020(online)].pdf | 2020-03-09 |
| 4 | 202044010107-OTHERS [29-03-2022(online)].pdf | 2022-03-29 |
| 4 | 202044010107-COMPLETE SPECIFICATION [09-03-2020(online)].pdf | 2020-03-09 |
| 5 | 202044010107-Proof of Right [23-03-2022(online)].pdf | 2022-03-23 |
| 5 | 202044010107-FORM 18 [06-05-2020(online)].pdf | 2020-05-06 |
| 6 | 202044010107-FORM-26 [05-06-2020(online)].pdf | 2020-06-05 |
| 6 | 202044010107-FORM 4(ii) [29-01-2022(online)].pdf | 2022-01-29 |
| 7 | 202044010107-FORM 3 [07-09-2020(online)].pdf | 2020-09-07 |
| 7 | 202044010107-Correspondence-Letter [07-01-2022(online)].pdf | 2022-01-07 |
| 8 | 202044010107-FORM 3 [08-03-2021(online)].pdf | 2021-03-08 |
| 8 | 202044010107-FORM 3 [07-12-2021(online)].pdf | 2021-12-07 |
| 9 | 202044010107-FER.pdf | 2021-10-18 |
| 9 | 202044010107-Information under section 8(2) [07-12-2021(online)].pdf | 2021-12-07 |
| 10 | 202044010107-FER.pdf | 2021-10-18 |
| 10 | 202044010107-Information under section 8(2) [07-12-2021(online)].pdf | 2021-12-07 |
| 11 | 202044010107-FORM 3 [07-12-2021(online)].pdf | 2021-12-07 |
| 11 | 202044010107-FORM 3 [08-03-2021(online)].pdf | 2021-03-08 |
| 12 | 202044010107-Correspondence-Letter [07-01-2022(online)].pdf | 2022-01-07 |
| 12 | 202044010107-FORM 3 [07-09-2020(online)].pdf | 2020-09-07 |
| 13 | 202044010107-FORM 4(ii) [29-01-2022(online)].pdf | 2022-01-29 |
| 13 | 202044010107-FORM-26 [05-06-2020(online)].pdf | 2020-06-05 |
| 14 | 202044010107-FORM 18 [06-05-2020(online)].pdf | 2020-05-06 |
| 14 | 202044010107-Proof of Right [23-03-2022(online)].pdf | 2022-03-23 |
| 15 | 202044010107-COMPLETE SPECIFICATION [09-03-2020(online)].pdf | 2020-03-09 |
| 15 | 202044010107-OTHERS [29-03-2022(online)].pdf | 2022-03-29 |
| 16 | 202044010107-DECLARATION OF INVENTORSHIP (FORM 5) [09-03-2020(online)].pdf | 2020-03-09 |
| 16 | 202044010107-FER_SER_REPLY [29-03-2022(online)].pdf | 2022-03-29 |
| 17 | 202044010107-CLAIMS [29-03-2022(online)].pdf | 2022-03-29 |
| 17 | 202044010107-DRAWINGS [09-03-2020(online)].pdf | 2020-03-09 |
| 18 | 202044010107-FORM 1 [09-03-2020(online)].pdf | 2020-03-09 |
| 18 | 202044010107-ABSTRACT [29-03-2022(online)].pdf | 2022-03-29 |
| 19 | 202044010107-US(14)-HearingNotice-(HearingDate-08-12-2025).pdf | 2025-11-19 |
| 20 | 202044010107-Correspondence to notify the Controller [19-11-2025(online)].pdf | 2025-11-19 |
| 1 | 2021-07-0812-52-25E_08-07-2021.pdf |