Claims:An apparatus comprising:
one or more processing elements to:
receive training data comprising input tiles and corresponding supersampling values for the input tiles, wherein each input tile comprises a plurality of pixels; and
train, based on the training data, a machine learning model to identify a level of supersampling for a rendered tile of pixels.
, Description:FIELD
[0002] This disclosure relates generally to data processing and more particularly to deep learning based selection of samples for adaptive supersampling.

BACKGROUND OF THE DISCLOSURE
[0003] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors used fixed function computational units to process graphics data; however, more recently, portions of graphics processors have been made programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.
[0004] To further increase performance, graphics processors typically implement processing techniques such as pipelining that attempt to process, in parallel, as much graphics data as possible throughout the different parts of the graphics pipeline. Parallel graphics processors with single instruction, multiple data (SIMD) or single instruction, multiple thread (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMD architecture, computers with multiple processing elements attempt to perform the same operation on multiple data points simultaneously. In a SIMT architecture, groups of parallel threads attempt to execute program instructions synchronously together as often as possible to increase processing efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS
[0005] So that the manner in which the above recited features of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate typical embodiments and are therefore not to be considered limiting of its scope.
[0006] Fig. 1 is a block diagram of a processing system;
[0007] Fig. 2A-2D illustrate computing systems and graphics processors;
[0008] Fig. 3A-3C illustrate block diagrams of additional graphics processor and compute accelerator architectures;
[0009] Fig. 4 is a block diagram of a graphics processing engine of a graphics processor;
[0010] Fig. 5A-5B illustrate thread execution logic including an array of processing elements employed in a graphics processor core;
[0011] Fig. 6 illustrates an additional execution unit;
[0012] Fig. 7 is a block diagram illustrating a graphics processor instruction formats;
[0013] Fig. 8 is a block diagram of an additional graphics processor architecture;
[0014] Fig. 9A-9B illustrate a graphics processor command format and command sequence;
[0015] Fig. 10 illustrates an example graphics software architecture for a data processing system;
[0016] Fig. 11A is a block diagram illustrating an IP core development system;
[0017] Fig. 11B illustrates a cross-section side view of an integrated circuit package assembly;
[0018] Fig. 11C illustrates a package assembly that includes multiple units of hardware logic chiplets connected to a substrate (e.g., base die);
[0019] Fig. 11D illustrates a package assembly including interchangeable chiplets;
[0020] Fig. 12 is a block diagram illustrating an example system on a chip integrated circuit;
[0021] Fig. 13A-13B are block diagrams illustrating example graphics processors for use within an SoC;
[0022] Fig. 14 illustrates a machine learning software stack, according to an embodiment.
[0023] Fig. 15A-15B illustrate layers of example deep neural networks.
[0024] Fig. 16 illustrates an example recurrent neural network.
[0025] Fig. 17 illustrates training and deployment of a deep neural network.
[0026] Fig. 18 is a block diagram illustrating distributed learning.
[0027] Fig. 19 a block diagram of an example computing system that may facilitate deep learning based selection of samples for adaptive supersampling, according to implementations of the disclosure.
[0028] Figs. 20A-20B illustrate example tiles of pixels that are part of an example rendered scene, according to implementations of the disclosure.
[0029] Fig. 21 illustrates a table depicting supersampling of plurality of tiles for training purposes of an AI network, according to implementations of the disclosure.
[0030] Fig. 22 illustrates an example model for training to select samples for adaptive supersampling of a tile of an image, according to implementations of the disclosure.
[0031] Fig. 23 is a flow diagram illustrating an embodiment of a method for model training for deep learning based selection of samples for adaptive supersampling.
[0032] Fig. 24 is a flow diagram illustrating an embodiment of a method for model inference for deep learning based selection of samples for adaptive supersampling.

DETAILED DESCRIPTION
[0033] A graphics processing unit (GPU) is communicatively coupled to host/processor cores to accelerate, for example, graphics operations, machine-learning operations, pattern analysis operations, and/or various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor/cores over a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). Alternatively, the GPU may be integrated on the same package or chip as the cores and communicatively coupled to the cores over an internal processor bus/interconnect (i.e., internal to the package or chip). Regardless of the manner in which the GPU is connected, the processor cores may allocate work to the GPU in the form of sequences of commands/instructions contained in a work descriptor. The GPU then uses dedicated circuitry/logic for efficiently processing these commands/instructions.
[0034] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one of skill in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of the present embodiments.