Claims:1. A process of designing a High Speed Brauns Multiplier, comprising:
translation, mapping and bit stream generation.
2. The process of designing a High Speed Brauns Multiplier as claimed in claim 1, in which multiplication of two binary numbers is performed using binary adders.
3. The process of designing a High Speed Brauns Multiplier as claimed in claim 1 is an Unsigned cluster multipliers.
, Description:FORM 2
THE PATENTS ACT 1970
(39 of 1970)
&
THE PATENTS (AMENDMENT) RULES, 2006
COMPLETE SPECIFICATION
(See section 10 and rule 13)
1. TITLE OF THE INVENTION

DESIGN AND IMPLEMENTATION OF HIGH SPEED BRAUNS MULTIPLIER FOR LOW POWER APPLICATIONS
2. APPLICANT (S)

The Principal
Amrita College of Engineering and Technology, Nagercoil

INVENTOR (S)
1. Dr. A. S. Radhamani, Associate Professor/Amrita College of Engineering
and Technology, Nagercoil
2. Dr. S. Saravana Veni, Assistant Professor/Amrita College of
Engineering and Technology, Nagercoil
3. Mrs.T. Jayachitra, Assistant Professor/School of Engineering and
Technology, Sharda University, Greater Noida
4. Mrs. V. Anusooya, Assistant Professor/Amrita College of Engineering
and Technology, Nagercoil
5. Mr. A. Rajendran, Assistant Professor/Amrita College of Engineering
and Technology, Nagercoil.

1. PREAMBLE TO THE DESCRIPTION

COMPLETE
The following specification particularly describes the invention and the manner in which it is to be performed.

DESIGN AND IMPLEMENTATION OF HIGH SPEED BRAUNS MULTIPLIER FOR LOW POWER APPLICATIONS

1. FIELD OF THE INVENTION
The proposed invention is about a binary multiplier circuit that can be used in digital electronics.

2. BACKGROUND OF THE INVENTION
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSIdevice.
Before the introduction of VLSI technology, most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into onechip.
Chaitanya kumarai et.al (2013) presented a design of 32 bit Parallel Prefix Adders In this paper, and used 32 bit Kogge-Stone, Brent-Kung, Ladner-Fischer parallel prefix adders [16]. In general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. Simulate and synthesis different types of 32-bit prefix adders using Xilinx ISE 10.1i tool. By using these synthesis results, the performance parameters like number of LUTs and delay are noted.
Murugeswari et.at (2014) proposed a modification of existing prominent multipliers like Wallace multiplier and Truncated Multiplier in order to improvise themintermsofpowerandarea.IntheexistingWallacemultiplierarchitecture,the

Carry Save Adder is replaced with Modified Carry Save Adder (MCSA) and further the full adder in the MCSA is implemented using Multiplexer. Similarly the regular full adder in the truncated multiplier has been replaced with mux based full adder to achieve low area and power. Simulation of 8 x 8 Multiplier has been carried out with Modelsim 6.3c and Synthesis is carried out by Xilinx10.1. Results obtained show that the proposed modified multipliers offer low power and reduced area than the existing Multipliers.
Dayadi Lakshmaiah et.al (2014) presented a design of Low Power 4-Bit CMOS Braun Multiplier based on Threshold Voltage Technique. A circuit design for a new Low Power 4-bit Braun Multiplier is presented. The multiplier is implemented by using different Threshold Voltage techniques. Power reduction techniques are proposed for 4-bit Braun Multiplier which is designed by Full Adders [4]. To get Optimum design low threshold voltages are used at critical paths similar way high threshold voltages are used at non critical paths. The design uses CMOS digital circuits in order to reduce the power dissipation while maintaining computational throughput.

3. OBJECTIVE OF THE INVENTION
The main scope of the project is to reduce the delay, low power consumption and the number of gates by designing a brauns multiplier using ladner fischer adder and ripple carry adder, carry look ahead adder proposed into the fast addition methods of carry save adder .This adder is used to reduce partial products efficiently.

4. SUMMARY
Brauns multiplier using low power application of Ladner- Fischer adder, carry-lookahead adder and Ripple carry adder is designed. This type of adder concentrates on gate levels to improve the speed and decreases the memory space. It looks like tree structure and it contains black and gray cells. These cells present in the carry generation stage are reduced to speed up the binary addition. The different types of adder using, the number of gates used in partial product stages are reduced in order to increase the speed of Brauns multiplier.The Brauns multiplier utilizing Parallel Prefix viper is planned. Parallel Prefix viper concentrates on entryway levels to move forward the speed and diminishes the memory space. It looks like tree structure and it contains dark and gray cells. The Dark cells comprise of two AND entryway and one OR entryway Gray cell comprises of as it were one AND entryway and one OR entryway. These cells show within the carry era organize are decreased to speed up the double expansion. For the most part, decrease in zone and change in speed of preparing is the prime concern of planning a multiplier. Here, utilizing Parallel Prefix snake, the number of doors utilized in halfway item stages are diminished in arrange to increase the speed of Brauns multiplier. The existing method had been used normal addition method compared to proposed fast addition method, the low power and reduction in area and improvement in speed of processing is the prime concern of designing a multiplier.

5. DETAILED DESCRIPTION OF THE INVENTION
BRAUNSMULTIPLIER
The simplest parallel multiplier is the Braun array. All the partial products are computed in parallel, then collected through a cascade of Carry Save Adders. The completion time is limited by the depth of the carry save array, and by the carry propagation in the adder. Note that this multiplier is only suited for positive operands.
The architecture of Braun multiplier mainly consists of some Carry Save Adders, array of AND gates and one Ripple Carry Adder. The architecture of standard Braun Multiplier is modified in this work for reducing the delay due to Ripple Carry Adder and performing faster multiplication of two binary numbers.

The shifting would carry out with the help of Carry Save Adder (CSA) and the Ripple carry adder should be used for the final stage of the output. Braun multiplier performs well for the unsigned operands that are less than 16 bits in terms of speed, power and area. But it is simple structure when compared to the other multipliers. The main drawback of this multiplier is that the potential susceptibility of glitching problem due to the Ripple Carry Adder in the last stage. The delay depends on the delay of the Full Adder and also a final adder in the last.
Each product can be generated in parallel with the AND gates. Each partial product can be added with the sum of partial product which has previously produced by using the

row of adders. The carry out will be shifted one bit to the left or right and then it will be added to the sum which is generated by the first adder and the newly generated partial product. The shifting would carry out with the help of Carry Save Adder (CSA) and the Ripple carry adder should be used for the final stage of the output.
Braun performs well for the unsigned operands that are less than 16 bits in terms of speed, power and area. But it is simple structure when compared to the other multipliers. The main drawback of this multiplier is that the potential susceptibility of glitching problem due to the Ripple Carry Adder in the last stage. The delay depends on the delay of the Full Adder and also a final adder in the last stage. Delay due to the final ripple adder can be minimized by using very fast one of a Parallel PrefixAdder. It is a simple parallel multiplier generally called as carry save array multiplier. It has been restricted to perform signed bits. The structure consists of array of AND gates and adders arranged in the iterative manner and no need of logic registers. This can be called as non addictivemultipliers.

Algorithm
An n*n bit Braun multiplier algorithm is constructed with n (n-1) adders, AND gates and (n-1) rows of Carry SaveAdder.

X: 8 bit Multiplicand Y: 8 bit Multiplier
P: 16 bit Product of X & Y Pn: Xi Yi is a Product bit

Each products can be generated in parallel with the AND gates. Each partial product can be added with the sum of partial product which has previously produced by using the row of adders. The carry out will be shifted one bit to the left or right and then it will be added to the sum which is generated by the first adder and the newly generated partial product.

METHODOLOGY
The main scope of the project is to reduce the delay, low power consumption and the number of gates by designing a brauns multiplier using ladner fischer adder and ripple carry adder, carry lookahead adder proposed into the fast addition methods of carry save adder .This adder is used to reduce partial products efficiently.

MULTIPLIER OPERATION

The performance of the system is determined by performance of Multiplier. Multiplication is most important among all arithmetic operation. Implementation of vlsi system depends majorly on the multiplication and Digital signal processing. In high performance system such as microprocessor, multiplier plays a major role. Multipliers consume most of the power in applications. In the low power VLSI design low power multiplier design is necessary. An nxn multiplication is conventionally composed of three operational phases: Partial product generation, Carry-free reduction of partial products and Carry propagating addition.
The partial product generation is usually a specific time of operation. The minimum delay in the partial product reduction (PPR) and in addition are both of order of log n, To add the partial products quickly high speed adders are needed. The problem occurrence in the speeding up of addition is carry propagation. This gives more interest in the designing of arithmetic circuits. Digital signal processing depends not only on the computational capacity also on the power consumption.Even though the area and performance are major considerations, power consumption has more preference than them. The need for low power system in VLSI is due to two reasons. First, with the steady growth of operating frequency and processing capacity per chip, large currents have to be delivered and the heat generated must be removed by proper cooling techniques. Second, battery life in portable electronic devices is limited and low power design directly leads to prolonged operation time.

ARCHITECTURE OF BRAUNS MULTIPLIER

The architecture of brauns multiplier is a parallel multiplier called as carry save array multiplier

Braun Multiplier Architecture

PROPOSED BRAUNMULTIPLIER

Block Diagram of the Proposed Braun Multiplier

It cannot be extended to perform signed bits. It consists of and gates and adders. It is also called as non addictive multiplier. It has simple structure comparing to other multipliers. Each product can be generated simultaneously by means of AND gates and each partial products can be added

with other partial products by means of adders the carry will be shifted to left or right and then can be added with next sum. The Braun’s Multiplier which uses the ripple carry adder that adds the partial product of last stages. In the proposed method the fast addition is used. Parallel prefix adder is used to reduce the delay due to carry propagation.

LADNER-FISCHERADDER

The Ladner-Fischer is the parallel prefix adder used to perform the addition operation. It looks like tree structure to perform the arithmetic operation .Ladner-Fischer adder is used for high performance addition operation. General block diagram of the Ladner-Fischer adder shown in figure3.3

General Block Diagram

The proposed Ladner-Fischer adder is flexible to speed up the binary addition and the structure looks like tree structure for the high performance arithmetic operations. In ripple carry adders each bit wait for the last bit operation. In parallel prefix adders instead of waiting for the carry propagation of the first addition, the idea here is to overlap the carry propagation of the first addition with the computation in the second addition, and so forth, since repetitive additions will be performed by a multi operand adder. Research on binary operation elements and motivation gives development of devices.
Pre-Processing Stage

In this stage we compute, the generate and propagate signals are used to generate carry input of each adder. A and B are inputs.
Pi=Ai +Bi Gi=Ai .Bi
Pi denotes propagate and it consists of only one AND gate

Gi denotes generate and it consists of one AND gate and OR gate

Carry GenerationStage
In this stage compute carries corresponding to each bit. Execution is done in parallel form After the computation of carries in parallel they are divided into smaller pieces. carry operator contain two AND gates , one OR gate. It uses propagate and generate as intermediate signals.

P(i:k) =P(i:j) . P(j-1:k)
G(i:k) =G(i:j) +(G(j-1:k) . P(i:j))
Post-Processing Stage
It is the final stage of an efficient Ladner-Fischer adder, the carry of a first bit is XORed with the next bit of propagates then the output is given as sum .It is used for two sixteen bit addition operations and each bit carry under goes post-processing stage with propagate, gives the final sum. The Efficient Ladner-Fischer adder structure is looking

like tree structure for the high performance of arithmetic operations and it is the fastest adder which focuses on gate level logic.
This is the final stage to compute the summation of input bits.It is same for all adders and sum bit.
Si= Pi Ci
Ci+1= (Pi .C0) + Gi
Block Diagram Of Lander FischerAdder

Basic cell diagram is shown in figure 3.4. Black cell operates three gates and gray cell operates two gates. Black cell consist of two AND gates and one OR gate Gray cell consists of only one AND gate and one OR gate enlarge it.The gray cell reduces the delay and memory because it operates only two gates. By using gray cell operations at the last stage of proposed adder gives a enormous dropping delay and memory used. The proposed adder improves the speed and decreases the memory for the operation of 8-bit addition. That carry is XOR with the propagate of next bit, that gives sum. Eight bit Ladner-Fischer adder eight bit block diagram is shown in figure 3.5

Cell Diagram

8-Bit Ladner-Fischer Adder

16-Bit Ladner-Fischer Adder

Tree Diagram Of Ladner- Fischer Adders
Ladner-Fischer adder can be represented as a parallel prefix graph consisting of carry operator nodes. The time required to generate carry signals in this prefix adder is o(log n). It is the fastest adder with focus on design time and is the common choice for high performance adders in industry.
The Ladner-Fischer adder concept was developed by R.Ladner and M. Fischer which was published in 1980. The better performance of Ladner-Fischer adder is because of its minimum logic depth and bounded fan-out. On the other side it occupies large silicon area.
The construction of 2, 3, 4, 5-bit Ladner- Fischer adders are shown below.

Tree Diagram of 2-bit Ladner- Fischer adders

Tree Diagram of 3-bit Ladner- Fischeradders

Tree Diagram of 4-bit Ladner- Fischeradders

Tree Diagram of 5-bit Ladner- Fischer adders

Gi indicates whether the Carry is generated. Pi indicates whether Carry is propagated. In carry generation stage of PPA, prefix graphs can be used to describe the tree structure.In the above figures the tree structure consists of grey cells, black cells, and buffers. In carry generation stage when two pairs of generate and propagate signals (Gm, Pm), (Gn, Pn)are given as inputs to the carry generation stage. It computes a pair of group generates and group propagate signals (Gm: n, Pm: n) The black cell computes both generate and propagate signals as output. It uses two AND gates and ORgate.
The grey cell computes the generate signal only. It uses only one AND gate and OR gate. Ladner-Fischer adder can be represented as a parallel prefix graph consisting of carry operator nodes. The time required to generate carry signals in this prefix adder. It is the fastest adder with focus on design time and is the common choice for high performance adders in industry. The better performance of Ladner-Fischer adderis

because of its minimum logic depth and bounded fan-out. On the other side it occupies large silicon area.
RIPPLE CARRYADDER
It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is called a ripple-carry adder (RCA), since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder (under the assumption that Cin =0)

.

Ripple Carry Adder
The layout of a figure 3.11 ripple-carry adder is simple, which allows fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit ripple-carry adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input to carry in first adder) + 31 × 2 (for carry propagation in latteradders)=65gatedelays.Thegeneralequationfortheworst-casedelayforan-bit

carry-ripple adder, accounting for both the sum and carry bits. A design with alternating carry polarities and optimized AND-OR-Invert gates can be about twice as fast.
CARRY LOOKAHEADADDER
To reduce the computation time, engineers devised faster ways to add two binary numbers by using carry-look ahead adders (CLA). They work by creating two signals (P and G) for each bit position, based on whether a carry is propagated through from a less significant bit position (at least one input is a 1), generated in that bit position (both inputs are 1), or killed in that bit position (both inputs are 0). In most cases, P is simply the sum output of a half adder and G is the carry output of the same adder. After P and G are generated, the carries for every bit position are created. Some advanced carry-look ahead architectures are the Manchester carry chain, Brent–Kung adder (BKA), and the Kogge–Stone adder (KSA).Some other multi-bit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time. These block based adders include the carry- skip (or carry-bypass) adder which will determine P and G values for each block rather than each bit, and the carry-select adder which pre-generates the sum and carry values for either possible carry input (0 or 1) to the block, using multiplexers to select the appropriate result when the carry bit is known.
Carry Lookahead Adder

A figure 3.12 carry lookahead adder by combining multiple carry-look ahead adders, even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64-bit adder that uses four 16- bit CLAs with two levels of LCUs. Other adder designs includes the carry-select adder, conditional sum adder, carry-skip adder, and carry-complete adder.
PROPOSED CARRY SAVE ADDER
If an adding circuit is to compute the sum of three or more numbers, it can be advantageous to not propagate the carry result. Instead, three-input adders are used, generating two results: a sum and a carry. Carry save adder sum and the carry may be fed into two inputs of the subsequent 3-number adder without having to wait for propagation of a carry signal. After all stages of addition, however, a conventional adder must be used to combine the final sum and carry results.

X0 x1 x2 x0 x1x2

Cout s c s

Proposed carry save adder

DESIGN IMPLEMENTATION
The following sub processes are contained in the design implementation process:

Translation: The all the input net lists are merging by translate process and outputs a Xilinx NGD (Native Generic Database) file and design constraints information’s.

Mapping: After the Translate process is complete then the Map process is run. The target device present Mappin4.1.5g maps the logical design described in the NGD file to the components/primitives (slices/CLBs An NCD file is created by the Map process.

Place and Route: After the design has been mapped then the place and route (PAR) process is run. To place and route the design on the target FPGA design PAR uses the NCD file created by the Map process.

Bit stream Generation: The process of “bi misleading because the data are no more bit oriented than that of an instruction set processor and there is generally” which is the collection of binary data used to program reconfigurable logic device is most commonly

Functional Simulation: Prior to mapping of the design post-Translate (functional) Simulation can be performed. The user to verify that the design has been synthesized Correctly and any differences due to the lower level of abstraction can be identified is allowed by this simulation process.
Static timing analysis: Three are types of static timing analysis can be performed:

Post-fit Static Timing Analysis: The timing Analyzer window open by the analyze Post- Fit Static timing process, which enables interactively to select timing paths in the specified design for tracing the timing results.

Post-Map Static Timing Analysis: The timing results of the Map process can be analyze. In evaluating timing performance (logic delay + route delay) Post-Map timing reports can be very useful.

Post Place and Route Static Timing Analysis: All delays to provide a comprehensive timing summary are incorporate by Post-PAR timing reports. You can proceed by creating configuration data and downloading a device if a placed and routed design has met all of your timing constraints.

Timing Simulation: A timing simulation net list can be created after your design has been placed and routed. It is possible to see how your design will behave in the circuit This is allowed by this simulation process.

Advantages of BraunMultiplier
1. High efficiency
2. Less delay
3. Low powerdissipation
4. Less area
5. High speed

Signature of the applicants/agent

ABSTRACT

A binary multiplier circuit which is used in digital electronics, such as a computer, to multiply two binary numbers is proposed using binary adders. A variety of computer arithmetic techniques can be used to implement a digital multiplier. A binary multiplier is a combinational logic circuit used in digital systems to perform the multiplication of two binary numbers. These are most commonly used in various applications especially in the field of digital signal processing to perform the various algorithms. Unsigned array multipliers are also known as Braun multipliers or Carry Save Array Multipliers. This multiplier is restricted to perform multiplication of two unsigned numbers. A double multiplier circuit which is utilized in advanced hardware, such as a computer, to increase two double numbers is built utilizing double adders. Unsigned cluster multipliers are moreover known as Braun multipliers or Carry Spare Cluster Multipliers.

CLAIMS
We Claim
1. A process of designing a High Speed Brauns Multiplier, comprising:
translation, mapping and bit stream generation.
2. The process of designing a High Speed Brauns Multiplier as claimed in claim 1, in which multiplication of two binary numbers is performed using binary adders.
3. The process of designing a High Speed Brauns Multiplier as claimed in claim 1 is an Unsigned cluster multipliers.