Abstract: This hardware invetion deals with power quality analyzer. Power Quality Analyzer (PQA) is essential in today’s world to give quality power uninterruptedly. We discussed about the hardware design of PQA and the software used. It is used to measure all the powers (P, Q and S) in three phases. Voltage profiles, %THD, power factor, harmonic profile and load curves can be obtained with this type analyzer at cheaper cost. This equipment can be used to analyze the output of any machine like alternators transformers etc. Through the harmonic profile we can measure which order of harmonic is more in the output of these machines. It uses Hall sensors (HE055T01) for current sensing and PT (230/9V) for voltage stepping down and 7840 IC voltage sensing. These sensed analog signals are converted to digital signals with help of ADC (AD7366). These digital signals are given to FPGA (Field Programmable Gate Array) – SPARTAN 6 model. FPGA processes these signals based on FIFO algorithm and through USB port it is connected to Personal Computer. “Key sight VEE pro” is the software used to analyze the power signals. We can measure Active, Reactive and Apparent powers, THD of all three phase and also ‘live load variation tracing’ through this software. This analyzer costs very less when compared to many other power quality analyzers available in the market analyzer. [To be published with Figure.2]
Claims:We claim:
1. A hardware design system for analzing the electric power signals given in (100) using FPGA, which comprises:
a) Power supply board (102);
b) Voltage sensing board (103);
c) Current sensing board (104);
d) Field Programmable Gate Array board (107);
e) Front panel (500); and
f) Back panel (600).
2. The hardware for analyzing the power signal (100) as claimed in claim 1, wherein said the power supply board (102) supplies required board power.
3. The hardware for analyzing the power signal (100) as claimed in claim 1, wherein said the voltage sensing board (103) sense the voltage of input and sensed analog voltage signal (105) is given to FPGA board (107).
4. The hardware for analyzing the power signal (100) as claimed in claim 1, wherein said the current sensing board (104) senses the current of input and sensed analog current signal (106) is given to FPGA board (107).
5. The hardware for analyzing the power signal (100) as claimed in claim 1, wherein said the FPGA board (107) converts the analog signal to digital signal through ADC and these digital signals are analysed as per the programme installed in the processor. This analysed data is displayed in multifunction meter as well as used in software (108) metioned above.
6. The hardware for analyzing the power signal (100) as claimed in claim 1, wherein said the front panel (500) is used for observing waveforms through test points (502) and to display various electrical parameters through MFM (503).
7. The hardware for analyzing the power signal (100) as claimed in claim 1, wherein said the back panel (600) have ports for taking the input signal (602) and also connecting the load through ports (603).
, Description:[0027]This present invention is about design of the power quality analyzer, the design parts and their description. Here, various embodiments have been discussed regarding the architecture. Some embodiments of this invention, illustrating its features, will now be discussed, and the disclosed embodiments merely exemplary of the invention that may embody in various forms.
[0028] The core of the hardware design which is FPGA which is field programmable gate array is semiconductor device which is based on CLB – configurable logic blocks connected via programmable interconnects. It can be reprogrammed to desired functionality even after completion of the design part. It takes the signal from the voltage and current sensing boards and gives the output as per designed program. It can be connected to the PC with USB port with which we can access sensed data and also we can rewrite the program to be installed in FPGA processor as per our requirement.
[0029]After that, the voltage sensing board consists of voltage sensors which will detect the voltage in each phase. The current sensing board also consists of current sensors which sense the current in each phase. These sensed data are in analog mode are given to FPGA board for further process. The input signal and loads are connected through these sensing boards.
[0030]The present invention shows the process of the three-phase PQA with FPGA (100), further detailed descriptions of the present invention are stated here about the attached drawings. Thus, the detailed embodiments of the present invention are disclosed here to describe the present invention.
[0031] The figure 2 shows the hardware structure (200). In this isolated power supply +5V (201) is connected to HV side of voltage sensing board (204). Power supplies +15V and -15V (203) are connected to voltage (204) and current sensing boards (205). Power supplies of +12V and -12V (202) are connected to FPGA board. Input signals Vin and Iin are connected to voltage and current sensing boards. FPGA board consists of analog to digital converter ADC 7366 (206), SPARTAN 6 processor (207) and USB port (208). Through USB port PC is connected.
[0032]In this embodiment of the present invention, as shown in figure 1, which refers to the block diagram for hardware design of power quality analyzer.
[0033] The input signal (101) may be a output of alternator, any power generating device, output of any power electronic device. In one word it is the signal to be analysed which must be an electrical and alternating one. This input signal is connected to the voltage sensing and current sensing ports of the hardware.
[0034] The power supply board(102) takes input as 230V from the power card. The internal circuits of power quality analyzer requires three types of DC supplies for board operations. So for that purpose the power card voltage of 230V will be divide as given below.
[0035] The first one is isolated power (300) of +5V to high voltage side of voltage sensing board. It is generated by first stepping down the power card (301) voltage of 230V to 9V with the help of transformers (302) placed in each phase. Then diode rectifier (303) is used to convert AC to DC followed by one ripple RC filter (304) to smoothen the voltage. Finally this is given to IC 7805 voltage regulator (305) to get required voltage of +5V. This is given to high voltage side of the voltage sensing board (306) in order with stand during high voltage applications.
[0036] The other power supplies (400) are +15V,-15V supplied to voltage sensing board low voltage side and current sensing board (410) and +12V,-12V and +5V are given to FPGA board (411). Here the 230 V from the power card (401) are step down to (18-0-9-0-18) V with the help of transformer (402). Then (0-18) V is rectified with diode rectifier (403) and filtered with ripple RC filter (404). The regulators used are IC 7812 (406) for +12V, IC 7912 (407) for -12V, IC 7815 (408) for +15V and IC 7915 (409) for -15V. Here another rectifier is used to rectify (0-9) V and filtered then IC 7805 regulator (405) is used to get +5V supply.
[0037] In another embodiment of the present invention, voltage sensing board (103) is used. As metioned above it requires to two power supplies for board operation +5V of isolating one and +15V and -15V. These are supplied from power supply board. To sense the input voltage signal we use IC 7840 here which senses the voltage signals given to the circuit. The input given to back panel S1 ports of each phase are connected internally to this board. A buffer IC TL084 is used. The sensed voltage signal (105) which is in analog mode and it may be sinusoidal, square and triangular etc, is given as one of the input to the FPGA board.
[0038] In another embodiment of the present invention, current sensing board (104) is used. It also requires two power +15V and -15V which are supplied from power supply board. Here hall sensors are used to sense the current. The model number of hall sensors used are HE055T01 and rating is 55A. This sensor signals from the back panel. The sensed analog current signal (106) is given to FPGA board.
[0039] Then, the Field Programmable Gate Array -FPGA board (107) is used which is the core part of the power quality analyzer. It requires power supply of +5V, +15V and -15V. It consists of ADC - AD7366 (206) which converts analog signal coming from voltage and current sensing boards to digital. Digital output of ADC is given to FPGA processor which is SPARTAN 6 (207). The processed signals are connected to PC to see the analysis of signal through USB port. FPGA uses FIFO algorithm for the internal process.
[0040] The internal hardware features are given as 16 digital inputs & 16 digital output (32 digital I/O) are used. Two 32-bit Timer/Counters are used. High speed connector to interface ADC/DAC piggy backboard.ADC/DAC signals and I/O lines are terminated at a screw type connector. Remote interface Hi-speed USB 2.0(480MbPS) USB TMC Class Device is used. The specifications are analog inputs are successive approximation type which 8, input resolution is 12 bit and input range is ±10V. Analog outputs are 4, output resolution is 12 bit and output range is ±5V. Digital I/O consists of 16 digital inputs and 16 digital outputs. Two counters are used having resolution of 32 bit and count upto maximum input frequency of 3MHz.
[0041] The SPARTAN 6 processor will process the data taken from voltage and current sensing boards and the results as per the program installed in the processor are displayed in multi function meter which is at front panel of the hardware. The processed data of FPGA board can be given to PC through USB port. This data can be used to get different parameters with the help of Key sight VEE pro software (108). It is the software used to analyze the power signals. We can measure Active, Reactive and Apparent powers, THD of all three phase and also ‘live load variation tracing’ through this software. Through VEE files we can see the V and I waveforms of each phase, individual harmonic data, THD, live load tracing etc. With this software we can make different apps for different power characteristics. By one click this app displays the required parameter assigned to it. As FPGA is reprogrammable, this software is used to make a number of apps.
[0042] The analyzer consists of front panel (500) where it contains a supply mains (501), test points (502) for connecting CRO to observe waveforms, MFM (503) is a multifunction meter which displays various electrical parameters. But it only measures up to 5A. and above 5 A and below 10A we should bypass the MFM and see in PC directly. USB ports (504) also located at front panel which is used to install programme in processor or to copy data analyzed from the FPGA.
[0043] The analyzer consists of back panel (600) where it contains power card pin (601), ports for connecting input (602) signal to be analyzed and load connecting ports (603). The sensing circuits are connected internally to these ports. CH 1, 2 and 3 consists of S1 and S2 which are current sensing terminals and P and N are voltage sensing terminals.
[0044] Subsequently, the utility/load (109) may be a three phase resistive load, incutive loads, motors, other machines used in industries etc. The load is connected to othe end of the voltage and current sensing boards as shown in figure 1. The load variations can be detected by measuring the current supplied to the load and load curves can be achieved accordingly. These curves can be displayed in the apps designed through the software (108) mentioned above.
[0045] Finally, the input signal is processed and analysed which makes the user to know about the various power quality issues, power characteristics, voltage profiles, load curves and all other electrical parameters
| # | Name | Date |
|---|---|---|
| 1 | 202241010487-IntimationOfGrant22-01-2025.pdf | 2025-01-22 |
| 1 | 202241010487-REQUEST FOR EARLY PUBLICATION(FORM-9) [26-02-2022(online)].pdf | 2022-02-26 |
| 2 | 202241010487-FORM-9 [26-02-2022(online)].pdf | 2022-02-26 |
| 2 | 202241010487-PatentCertificate22-01-2025.pdf | 2025-01-22 |
| 3 | 202241010487-Written submissions and relevant documents [28-09-2024(online)].pdf | 2024-09-28 |
| 3 | 202241010487-FORM 1 [26-02-2022(online)].pdf | 2022-02-26 |
| 4 | 202241010487-FIGURE OF ABSTRACT [26-02-2022(online)].jpg | 2022-02-26 |
| 4 | 202241010487-Correspondence to notify the Controller [24-09-2024(online)].pdf | 2024-09-24 |
| 5 | 202241010487-US(14)-ExtendedHearingNotice-(HearingDate-26-09-2024)-1200.pdf | 2024-08-27 |
| 5 | 202241010487-DRAWINGS [26-02-2022(online)].pdf | 2022-02-26 |
| 6 | 202241010487-REQUEST FOR ADJOURNMENT OF HEARING UNDER RULE 129A [23-08-2024(online)].pdf | 2024-08-23 |
| 6 | 202241010487-COMPLETE SPECIFICATION [26-02-2022(online)].pdf | 2022-02-26 |
| 7 | 202241010487-US(14)-HearingNotice-(HearingDate-27-08-2024).pdf | 2024-08-05 |
| 7 | 202241010487-FORM 3 [28-02-2022(online)].pdf | 2022-02-28 |
| 8 | 202241010487-Written submissions and relevant documents [19-06-2024(online)].pdf | 2024-06-19 |
| 8 | 202241010487-FORM 3 [28-02-2022(online)]-1.pdf | 2022-02-28 |
| 9 | 202241010487-Correspondence to notify the Controller [05-06-2024(online)].pdf | 2024-06-05 |
| 9 | 202241010487-FORM 18 [28-02-2022(online)].pdf | 2022-02-28 |
| 10 | 202241010487-ENDORSEMENT BY INVENTORS [28-02-2022(online)].pdf | 2022-02-28 |
| 10 | 202241010487-FORM-26 [05-06-2024(online)].pdf | 2024-06-05 |
| 11 | 202241010487-AMENDED DOCUMENTS [30-05-2024(online)].pdf | 2024-05-30 |
| 11 | 202241010487-FER.pdf | 2022-09-06 |
| 12 | 202241010487-EDUCATIONAL INSTITUTION(S) [30-05-2024(online)].pdf | 2024-05-30 |
| 12 | 202241010487-FORM 3 [23-02-2023(online)].pdf | 2023-02-23 |
| 13 | 202241010487-FER_SER_REPLY [23-02-2023(online)].pdf | 2023-02-23 |
| 13 | 202241010487-FORM 13 [30-05-2024(online)].pdf | 2024-05-30 |
| 14 | 202241010487-ENDORSEMENT BY INVENTORS [23-02-2023(online)].pdf | 2023-02-23 |
| 14 | 202241010487-FORM-26 [30-05-2024(online)].pdf | 2024-05-30 |
| 15 | 202241010487-DRAWING [23-02-2023(online)].pdf | 2023-02-23 |
| 15 | 202241010487-OTHERS [30-05-2024(online)].pdf | 2024-05-30 |
| 16 | 202241010487-COMPLETE SPECIFICATION [23-02-2023(online)].pdf | 2023-02-23 |
| 16 | 202241010487-POA [30-05-2024(online)].pdf | 2024-05-30 |
| 17 | 202241010487-US(14)-HearingNotice-(HearingDate-07-06-2024).pdf | 2024-05-13 |
| 17 | 202241010487-CLAIMS [23-02-2023(online)].pdf | 2023-02-23 |
| 18 | 202241010487-ABSTRACT [23-02-2023(online)].pdf | 2023-02-23 |
| 18 | 202241010487-Fer Reply_Supporting Documents_28-02-2023.pdf | 2023-02-28 |
| 19 | 202241010487-ABSTRACT [23-02-2023(online)].pdf | 2023-02-23 |
| 19 | 202241010487-Fer Reply_Supporting Documents_28-02-2023.pdf | 2023-02-28 |
| 20 | 202241010487-CLAIMS [23-02-2023(online)].pdf | 2023-02-23 |
| 20 | 202241010487-US(14)-HearingNotice-(HearingDate-07-06-2024).pdf | 2024-05-13 |
| 21 | 202241010487-COMPLETE SPECIFICATION [23-02-2023(online)].pdf | 2023-02-23 |
| 21 | 202241010487-POA [30-05-2024(online)].pdf | 2024-05-30 |
| 22 | 202241010487-DRAWING [23-02-2023(online)].pdf | 2023-02-23 |
| 22 | 202241010487-OTHERS [30-05-2024(online)].pdf | 2024-05-30 |
| 23 | 202241010487-FORM-26 [30-05-2024(online)].pdf | 2024-05-30 |
| 23 | 202241010487-ENDORSEMENT BY INVENTORS [23-02-2023(online)].pdf | 2023-02-23 |
| 24 | 202241010487-FER_SER_REPLY [23-02-2023(online)].pdf | 2023-02-23 |
| 24 | 202241010487-FORM 13 [30-05-2024(online)].pdf | 2024-05-30 |
| 25 | 202241010487-EDUCATIONAL INSTITUTION(S) [30-05-2024(online)].pdf | 2024-05-30 |
| 25 | 202241010487-FORM 3 [23-02-2023(online)].pdf | 2023-02-23 |
| 26 | 202241010487-AMENDED DOCUMENTS [30-05-2024(online)].pdf | 2024-05-30 |
| 26 | 202241010487-FER.pdf | 2022-09-06 |
| 27 | 202241010487-ENDORSEMENT BY INVENTORS [28-02-2022(online)].pdf | 2022-02-28 |
| 27 | 202241010487-FORM-26 [05-06-2024(online)].pdf | 2024-06-05 |
| 28 | 202241010487-Correspondence to notify the Controller [05-06-2024(online)].pdf | 2024-06-05 |
| 28 | 202241010487-FORM 18 [28-02-2022(online)].pdf | 2022-02-28 |
| 29 | 202241010487-FORM 3 [28-02-2022(online)]-1.pdf | 2022-02-28 |
| 29 | 202241010487-Written submissions and relevant documents [19-06-2024(online)].pdf | 2024-06-19 |
| 30 | 202241010487-US(14)-HearingNotice-(HearingDate-27-08-2024).pdf | 2024-08-05 |
| 30 | 202241010487-FORM 3 [28-02-2022(online)].pdf | 2022-02-28 |
| 31 | 202241010487-REQUEST FOR ADJOURNMENT OF HEARING UNDER RULE 129A [23-08-2024(online)].pdf | 2024-08-23 |
| 31 | 202241010487-COMPLETE SPECIFICATION [26-02-2022(online)].pdf | 2022-02-26 |
| 32 | 202241010487-US(14)-ExtendedHearingNotice-(HearingDate-26-09-2024)-1200.pdf | 2024-08-27 |
| 32 | 202241010487-DRAWINGS [26-02-2022(online)].pdf | 2022-02-26 |
| 33 | 202241010487-FIGURE OF ABSTRACT [26-02-2022(online)].jpg | 2022-02-26 |
| 33 | 202241010487-Correspondence to notify the Controller [24-09-2024(online)].pdf | 2024-09-24 |
| 34 | 202241010487-Written submissions and relevant documents [28-09-2024(online)].pdf | 2024-09-28 |
| 34 | 202241010487-FORM 1 [26-02-2022(online)].pdf | 2022-02-26 |
| 35 | 202241010487-PatentCertificate22-01-2025.pdf | 2025-01-22 |
| 35 | 202241010487-FORM-9 [26-02-2022(online)].pdf | 2022-02-26 |
| 36 | 202241010487-IntimationOfGrant22-01-2025.pdf | 2025-01-22 |
| 36 | 202241010487-REQUEST FOR EARLY PUBLICATION(FORM-9) [26-02-2022(online)].pdf | 2022-02-26 |
| 1 | 202241010487searchstrategyE_05-09-2022.pdf |