SPECIFICATION OF THE INVENTION

1. Title of the Invention:

Deterministic and Synchronised Data Transfer System and Method between two Processors for Real Time Applications

2. Field of invention:

This invention relates to data communication between two processors as and when required using a shared memory. This philosophy can be used at any time during the run time application without any data missing and it also leads to synchronization between the processors.
3. Prior art and drawback

In conventional method of data transfer between the processors only in the beginning of the cycle whole process will be done. Using this philosophy we can transfer the data reliably as and when required in multiple times within one cycle and it is possible to synchronize the two processors as and when required.

4. Aim of the invention:

The aim of the invention is to transfer the processor cardl data to the processor card2 and processor card2 data to the processor cardl as and when required by the processors in real time execution and also synchronizing the two processors in the process. This data transfer can be occurred multiple times during every cycle operation.

5. Summary of the invention:
In real time applications it is required to transfer the data between the processing modules. This data transfer can occur in many cases like in a complex system of Automatic Flight Control Computer .Each processor can acquire data from different sensors and LRU's and this data should be transferred to other processors for executing computations. During execution of some applications processors may generate output data which should be transferred to other processor for further checking and comparisons. So it is necessary to use an effective and optimized data transfer philosophy for mutual data transfer between the processors. For data transfer between the processors it is required to use a shared memory which can be accessed by both processors as and when required with mutual reading and writing permissions. A unique identifier is also required for each transaction to avoid mismatch of a writing with reading. So the method proposing here is explained in the following sequence of points:

• Copy the required data to be transferred to other processor in its own specific RAM location.
• Wait for the writing permission on shared memory from other processor.
• Copy the entire data from its RAM to shared memory.
• Give read permission to other processor for reading the copied data from the shared memory.

6. Detailed description of the invention:

Detailed explanation of the philosophy is given below , along with a block diagram. This philosophy is explained by considering that the DPRAM as the shared memory for data exchange interface between the processors. For avoiding data mismatch a unique TID (Transaction Identifier) for each transaction has been used and this also leads to synchronization between the processing modules. During every transaction, total length of data information is provided to avoid the data missing or wrong reading of data during the reading process. This philosophy is explained with different possible cases where data transfer is required. Below figure shows two processing modules Processor card-1 (P1) and Processor card-2 (P2) communicating with DPRAM. In DPRAM two dedicated locations Sync location-1 and Sync location-2 are assigned for storing read/write permission flags of both processors. P1 can only write at Sync location-1 and P2 can only read from Sync location-1. P1 can only read from Sync location-2 and P2 can only write at Sync location-2.

Block Diagram:

Procedure for communication:

• Transaction Identifier (TID): For every Write-Read operation unique TID should be used to avoid write-read mismatching

• Total Bytes Length:

> At every Write-Read operation total data to be communicated should be calculated in bytes. This information is required because data of varying length is exchanged.

• The initialization of DPRAM sync locations are done with Oxee by both P1 and P2

Casel: P1 Writing & P2 Reading
1. P1 has to copy the desired data to be sent to P2 in its own RAM and calls the writing process with one unique TID and total bytes of data length. P2 has to call the reading process with the same TID mentioned in P1 and then P2 will write 0x55 in sync location-2.
2. P1 will continuously read the sync location-2, if data in that location is 0x55 then P1 starts IPC writing process.

3. P1 writes OxCC in sync location-1 indicating P2 that it is going to start copying the required data to be sent to P2. So, P2 will be in wait state by continuously reading the sync location-1.

4. Now P1 will use the IPC area in DPRAM for copying the data from its SRAM. It will use first 2 locations for storing the TID information and next 2 locations for total bytes length information. After that it will copy the desired data in DPRAM based on the total bytes of length mentioned above.

5. After copying the desired data P1 will write OxAA in sync location-1 to indicate that it has completed copying the data in DPRAM and giving permission to P2 for reading the copied data.

6. P2 reads the OxAA from sync location-1 and writes OxDD in sync location-2 indicating that P2 started reading process so that P1 will be in continuous loop till P2 completes the full reading process.

7. P2 will extract the TID and total bytes of length information from DPRAM. If TID matches with the current Read function TID then it starts reading the desired data
from DPRAM to its own RAM as per the P1's writing sequence. If TID does not match then it has to declare the error corresponds to IPC.

8. Once reading / error generation process completes P2 will write 0x77 in sync location-2 indicating completion of read process to P1.

9. P1 reads the sync location-2 for 0x77, once it is 0x77 then P1 will write OxEE in sync location-1 indicating that whole Write-Read process is over in P1. After this P2 will also write OxEE in sync location-2 indicating that whole Write-Read process is over in P2.

Case2: P2 Writing & P1 Reading
1. P2 has to copy the desired data to be sent to P1 in its own RAM and calls the
writing process with one unique TID and total bytes of data length. At the same time P1 has to call the reading process with the same TID given by P2.

2. P2 continuously read the sync location-1, if data in that location is 0x55 then P2 starts IPC writing process.
3. P2 writes OxCC in sync location-2 indicating P1 that it is going to start copying the required data to be sent to PL So, P1 will be in wait state by continuously reading the sync location-2.

4. Now P2 will use the IPC area in DPRAM for copying the data. It will use first 2 locations for storing the TID information and next 2 locations for total bytes length information. After that it will copy the desired data in DPRAM based on the total bytes of length in above mentioned sequence.

5. After copying the desired data P2 will write OxAA in sync location-2 to indicate that it completed copying the data in DPRAM and giving permission to P1 for reading the copied data.

6. P1 reads the OxAA from sync location-2 and writes OxDD in sync location-1 indicating that P1 started reading process so that P2 will be in continuous loop till P1 completes the full reading process.

7. P1 will extract the TID and total bytes of length information from DPRAM. If TID matches with the current Read function TID then it starts reading the desired data from DPRAM to its own RAM as per the P2's writing sequence. If TID does not match then it has to declare the error corresponds to IPC.

8. Once reading process completes P1 will write 0x77 in sync location-1 indicating completion of read process to P2.

9. P2 reads the sync location-1 for 0x77, once it is 0x77 then P2 will write OxEE in sync location-2 indicating that whole Write-Read process is over in P2. After this P1 will also write OxEE in sync location-1 indicating that whole Write-Read process is over in P1.

Case3: P1 Writing & P2 Writing
Both processors writing at the same time should not happen, after every write operation ,a read operation should occur.This situation is not desirable as because the one processor is writing data for the other to read.So that's why if one processor is writing , the other processor should read after that.

Case4: P1 Reading & P2 reading
Both processors reading at the same time should not happen, after every write operation , a read operation should occur. This situation is not desirable as because the one processor should read data when the other has written. So that's why if one processor is reading , the other processor should have written before that.

CLAIMS

We claim

1. Using TID(Transaction Identifiers) , Length and sync Locations it is possible to exchange data as and when required between two processing modules in one software cycle time in the embedded systems. This guarantees that the data which is generated within the cycle at various steps can be made available to the other processor within a cycle. Hence this process also can decrease the load of the processor because the sharing of functionalities can be done in an efficient way.

2. Using this method, it leads to synchronization between the processors using the concept of unique TID (Transaction Identifier) for each transaction and it avoids the occurrence of data mismatch during the reading process.

3. By using the length information as zero this method can be used for synchronizing the processors for example starting two different timers by two processing modules at the same time.

4. In this data transfer method using length of the data information at each transaction avoids data missing or reading wrong data.