Title of invention: device and method for preventing overcharge of secondary battery
Technical field
[One]
This application is a priority claim application for Korean Patent Application No. 10-2018-0114989 filed on September 27, 2018, and all contents disclosed in the specification and drawings of the application are incorporated herein by reference.
[2]
The present invention relates to an apparatus and method for preventing overcharging of a secondary battery, and more particularly, to an apparatus and method for preventing overcharging of a secondary battery for preventing overcharging of an SLI (Starting Lighting Ignition) battery having at least one secondary battery. .
Background
[3]
In recent years, as the demand for portable electronic products such as notebook computers, video cameras, and portable telephones is rapidly increasing, and the development of energy storage batteries, robots, satellites, etc. is in earnest, it is suitable for high-performance secondary batteries that can be repeatedly charged and discharged. There is an active research on the Korean market.
[4]
Currently commercialized secondary batteries include nickel cadmium batteries, nickel hydride batteries, nickel zinc batteries, and lithium secondary batteries, among which lithium secondary batteries have little memory effect compared to nickel-based secondary batteries, so charging and discharging are free. The self-discharge rate is very low and the energy density is high.
[5]
Meanwhile, SLI (Starting Lighting Ignition) batteries mounted in electric devices such as scooters or tractors in the related art have used lead acid batteries for reasons of price advantage. However, when a lead acid battery is installed in a motorized device that is not equipped with a voltage regulator, the lifespan of the lead acid battery is significantly reduced due to overcharging, and thus there is a hassle of frequent replacement of the battery.
[6]
Accordingly, it is applicable to both a system equipped with a voltage regulator and a system without a voltage regulator (unregulated system), and it is necessary to apply an SLI battery capable of preventing a reduction in lifespan due to overcharging.
Detailed description of the invention
Technical challenge
[7]
The present invention has been invented to solve the above problems, and an object of the present invention is to provide an improved overcharging prevention apparatus and method for preventing overcharging of a SLI (Starting Lighting Ignition) battery having at least one secondary battery.
[8]
Other objects and advantages of the present invention can be understood by the following description, and will be more clearly understood by examples of the present invention. In addition, it will be easily understood that the objects and advantages of the present invention can be realized by the means and combinations thereof shown in the claims.
Means of solving the task
[9]
An overcharge prevention device according to an embodiment of the present invention for achieving the above object is a device provided in a battery pack to prevent overcharging of a cell assembly including at least one secondary battery, the voltage across the cell assembly A voltage measuring unit configured to measure the voltage; A charging FET provided on a charge/discharge line electrically connecting one end of the cell assembly and a pack terminal of the battery pack, and configured to control conduction of a charge current flowing through the charge/discharge line; It is provided on a bypass line configured electrically parallel with the charging/discharging line by electrically connecting both ends of the charging FET and connected in parallel with the charging FET, and the charging current flows according to the opening/closing operation of the charging FET. A bypass resistor configured to be; And a processor configured to receive a voltage value at both ends of the cell assembly from the voltage measuring unit, and control an open/close operation of the charging FET based on the received voltage value at both ends.
[10]
In addition, the processor is configured to turn off the charging FET when the charging current for charging the cell assembly flows on the charge/discharge line, and voltage values ​​at both ends of the cell assembly reach a predetermined upper limit value. I can.
[11]
In addition, the processor may be configured to turn on the charging FET when the charging current for charging the cell assembly flows on the charge/discharge line, and voltage values ​​at both ends of the cell assembly reach a predetermined lower limit value. have.
[12]
Further, the processor may repeatedly turn off and on the charging FET several times when the voltage values ​​at both ends of the cell assembly reach predetermined upper and lower limits respectively while the cell assembly is being charged by the charging current. Can be configured.
[13]
In addition, the voltage measuring unit may be configured to further measure a voltage across the battery pack and a voltage across the bypass resistor.
[14]
In addition, the processor further receives at least one of a voltage value of both ends of the battery pack and a voltage value of both ends of the bypass resistor from the voltage measuring unit, and the received voltage value of both ends of the battery pack and the bypass resistance It may be configured to control the opening and closing operation of the charging FET based on at least one of the voltage values ​​of both ends.
[15]
In addition, the processor, when the charging FET is turned off, a voltage corresponding to the sum of a voltage value corresponding to the difference between the voltage value of both ends of the battery pack and the predetermined upper limit value and the voltage drop value of the cell assembly It may be configured to control the opening and closing operation of the charging FET to be applied to the bypass resistor.
[16]
In addition, the processor is configured to control the opening and closing operation of the charging FET so that the voltage value at both ends of the battery pack is kept constant during a turn-off period in which the charging current flows through the bypass resistor and the charging FET is turned off. Can be.
[17]
In addition, the charging FET has a gate terminal, a drain terminal, and a source terminal, the gate terminal is electrically connected to the processor, the drain terminal is electrically connected to the negative terminal of the cell assembly, the The source terminal may be configured to be electrically connected to the negative terminal of the battery pack.
[18]
In addition, the bypass resistor has one end connected on a charge/discharge line connecting between the negative terminal of the cell assembly and the drain terminal of the charging FET, and the other end of the negative terminal of the battery pack and the source terminal of the charging FET. It may be configured to be connected on a charge/discharge line that connects therebetween.
[19]
In addition, the BMS according to an embodiment of the present invention for achieving the above object includes an overcharge prevention device according to the present invention.
[20]
In addition, the battery pack according to an embodiment of the present invention for achieving the above object includes an overcharge prevention device according to the present invention.
[21]
In addition, the transmission device according to an embodiment of the present invention for achieving the above object includes an overcharge prevention device according to the present invention.
[22]
In addition, an overcharge prevention method according to an embodiment of the present invention for achieving the above object is a method of preventing overcharging of a cell assembly provided in a battery pack and including at least one secondary battery, Measuring a voltage across both ends; On a charge/discharge line that receives the voltage value of both ends of the cell assembly measured by the voltage measuring step, and electrically connects one end of the cell assembly and the pack terminal of the battery pack based on the received voltage value of both ends. Controlling an opening/closing operation of a charging FET provided in the charging/discharging line and configured to control conduction of a charging current flowing through the charging/discharging line; And a bypass resistor electrically connected between both ends of the charging FET so as to be electrically connected in parallel with the charging/discharging line and connected in parallel with the charging FET, according to the opening/closing operation of the charging FET. And controlling the charging current to flow.
[23]
In addition, in the step of controlling the opening and closing operation of the charging FET, when the voltage values ​​at both ends of the cell assembly reach predetermined upper and lower limits, respectively, while the cell assembly is being charged by the charging current, the charging is repeated several times. The FET can be turned off and on.
[24]
Further, in the step of controlling the charging current to flow, the charging FET so that the voltage value at both ends of the battery pack is kept constant during a turn-off period in which the charging current flows through the bypass resistor and the charging FET is turned off. The opening and closing operation of the can be controlled.
Effects of the Invention
[25]
According to an aspect of the present invention, by adjusting the voltage applied to the cell assembly, there is an advantage that can be applied to both a system equipped with a voltage regulator and a system without a voltage regulator (Unregulated System).
[26]
According to another aspect of the present invention, it is possible to maintain a constant output voltage of the battery pack in a state in which the cell assembly does not correspond to an overcharge state, thereby maintaining the output efficiency of the battery pack and extending the life of the secondary battery. There is an advantage.
[27]
According to another aspect of the present invention, since it can be applied to a system without a voltage regulator (Unregulated System), there is an advantage in that the efficiency of manufacturing the battery pack can be improved and the manufacturing cost can be reduced.
[28]
In addition to the present invention may have a variety of other effects, these other effects of the present invention can be understood by the following description, can be seen more clearly by the embodiments of the present invention.
Brief description of the drawing
[29]
The following drawings attached to the present specification illustrate preferred embodiments of the present invention, and serve to further understand the technical idea of ​​the present invention together with the detailed description of the present invention to be described later, so the present invention is described in such drawings. It is limited to and should not be interpreted.
[30]
1 is a diagram schematically illustrating a process in which a conventional SLI battery is charged.
[31]
2 is a diagram schematically illustrating a process of charging an SLI battery according to an embodiment of the present invention.
[32]
3 is a diagram schematically showing the configuration of an overcharge prevention apparatus according to an embodiment of the present invention.
[33]
4 is a diagram illustrating a voltage profile of a battery pack and a cell assembly referred to by an overcharge prevention apparatus according to an embodiment of the present invention.
[34]
5 is a flowchart schematically illustrating a method for preventing overcharging according to an embodiment of the present invention.
Mode for carrying out the invention
[35]
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as being limited to their usual or dictionary meanings, and the inventors appropriately explain the concept of terms in order to explain their own invention in the best way. Based on the principle that it can be defined, it should be interpreted as a meaning and concept consistent with the technical idea of ​​the present invention.
[36]
Therefore, the embodiments described in the present specification and the configurations shown in the drawings are only the most preferred embodiment of the present invention, and do not represent all the technical spirit of the present invention. It should be understood that there may be equivalents and variations.
[37]
In addition, in describing the present invention, when it is determined that a detailed description of a related known configuration or function may obscure the subject matter of the present invention, the detailed description thereof will be omitted.
[38]
Throughout the specification, when a certain part "includes" a certain component, it means that other components may be further included, rather than excluding other components unless specifically stated to the contrary. In addition, a term such as'processor' described in the specification means a unit that processes at least one function or operation, which may be implemented by hardware or software, or a combination of hardware and software.
[39]
In addition, throughout the specification, when a part is said to be "connected" with another part, it is not only "directly connected", but also "indirectly connected" with another element interposed therebetween. Includes.
[40]
In the present specification, a secondary battery includes a negative terminal and a positive terminal, and refers to one independent cell that can be physically separated. For example, one pouch-type lithium polymer cell may be regarded as a secondary battery.
[41]
[42]
The overcharge prevention device according to an embodiment of the present invention may be a device provided in a battery pack to prevent overcharge of the cell assembly 10 including at least one secondary battery. For example, the battery pack may be a starting lighting ignition (SLI) battery. In addition, the cell assembly 10 may include at least one or more secondary batteries connected in series and/or in parallel.
[43]
1 is a diagram schematically illustrating a process of charging a conventional SLI battery, and FIG. 2 is a diagram schematically illustrating a process of charging an SLI battery according to an embodiment of the present invention.
[44]
Referring to FIGS. 1 and 2, the SLI battery 1 may transmit power for starting to a starting motor 2. Subsequently, the starting motor 2 may transmit the starting power to the engine 3 based on the starting power supplied from the SLI battery 1. Subsequently, the engine 3 may start the operation based on the starting power supplied from the starting motor 2. In addition, the engine 3 can transmit the drive power according to the driving of the engine 3 to the alternator 4 (alternator). Subsequently, the alternator 4 may transmit the driving power supplied from the engine 3 to the rectifier 5. Subsequently, the rectifier 5 can rectify the drive power supplied from the alternator 4.
[45]
As shown in FIG. 1, the conventional SLI battery 1 may be charged by receiving adjusted driving power from a voltage regulator 6 that adjusts the driving power rectified by the rectifier 5.
[46]
The SLI battery 1 according to an embodiment of the present invention may be charged by receiving driving power directly from the rectifier 5 without going through the voltage regulator 6, as shown in FIG. 2.
[47]
Through such a configuration, the SLI battery 1 according to an embodiment of the present invention is provided in an unregulated system in which the voltage regulator 6 is not mounted, as shown in FIG. 2, so that the voltage regulator 6 There is an effect of preventing overcharging of the battery by adjusting the driving power without adjusting the voltage by ).
[48]
Of course, the SLI battery 1 according to an embodiment of the present invention may also be provided in a system in which the voltage regulator 6 is mounted (Regulated system).
[49]
[50]
3 is a diagram schematically showing the configuration of an overcharge prevention apparatus according to an embodiment of the present invention.
[51]
3, the SLI battery 1 according to an embodiment of the present invention includes an overcharge prevention device. In addition, the overcharge prevention apparatus according to an embodiment of the present invention may include a voltage measurement unit 100, a charging FET 200, a bypass resistor 300, and a processor 400.
[52]
The voltage measuring unit 100 may measure the voltage at both ends of the cell assembly 10. For example, as shown in the configuration of FIG. 3, the voltage measurement unit 100 may be electrically connected to both ends of the cell assembly 10 so as to transmit and receive electrical signals. In addition, the voltage measurement unit 100 may measure the voltage at both ends of the cell assembly 10 based on electrical signals received from both ends of the cell assembly 10.
[53]
Preferably, the voltage measurement unit 100 may be electrically connected to the processor 400 so as to transmit and receive electrical signals. In addition, the voltage measurement unit 100 may measure the voltage across the cell assembly 10 at time intervals under the control of the processor 400 and output a signal indicating the magnitude of the measured voltage to the processor 400. . For example, the voltage measurement unit 100 may be implemented using a voltage measurement circuit commonly used in the art.
[54]
The charging FET 200 may be provided on a charge/discharge line L1 electrically connecting one end of the cell assembly 10 and a pack terminal of the battery pack. For example, as shown in the configuration of FIG. 3, the charging FET 200 is on a charge/discharge line L1 that electrically connects the negative terminal of the cell assembly 10 and the negative pack terminal of the battery pack. It can be provided.
[55]
Further, the charging FET 200 can control conduction of the charging current flowing through the charging/discharging line L1. For example, as shown in the configuration of FIG. 3, the charging FET 200 may control conduction of a charging current flowing from the negative terminal of the cell assembly 10 to the negative pack terminal of the battery pack.
[56]
For example, the charging FET 200 is a field effect transistor (FET) device having a gate (G), a drain (D), and a source terminal (S), and between the gate terminal (G) and the source terminal (S). It may be turned on or turned off depending on whether a channel is formed according to the voltage applied to the device. For example, the FET device may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
[57]
In addition, a parasitic diode may be provided in the charging FET 200. As shown in the configuration of FIG. 3, when a parasitic diode is provided in the charging FET 200, the charging FET 200 may be divided into a FET main body and a parasitic diode. Here, the parasitic diode is a diode connected in parallel with the FET body, and can perform a rectification function of conducting rectification in one direction. Meanwhile, in the embodiment of FIG. 3, the charging FET 200 is implemented as an N-type MOSFET, but the charging FET 200 is not limited to the N-type MOSFET.
[58]
Preferably, the gate terminal G of the charging FET 200 according to an embodiment of the present invention may be electrically connected to the processor 400. For example, as shown in the configuration of FIG. 3, the gate terminal G may be electrically connected to the processor 400 to exchange electrical signals. In addition, the drain terminal D of the charging FET 200 may be electrically connected to the negative terminal of the cell assembly 10. In addition, the source terminal S of the charging FET 200 may be electrically connected to the negative terminal of the battery pack.
[59]
The bypass resistor 300 may be provided on a bypass line L2 electrically connected in parallel with the charge/discharge line L1 by electrically connecting both ends of the charging FET 200. For example, as shown in the configuration of FIG. 3, the bypass resistor 300 may be provided on the bypass line L2. Here, the bypass line L2 may be a line having one end connected to the drain terminal D of the charging FET 200 and the other end connected to the source terminal S of the charging FET 200. In addition, the bypass line (L2), as shown in the configuration of Figure 3, to be configured in electrical parallel with the charge/discharge line (L1) connecting between the first node (n1) and the second node (n2). I can.
[60]
In addition, the bypass resistor 300 may be connected in parallel with the charging FET 200. For example, as shown in the configuration of FIG. 3, the bypass resistor 300 may be electrically connected in parallel with the charging FET 200 between the first node n1 and the second node n2. .
[61]
In addition, a charging current may flow through the bypass resistor 300 according to an opening/closing operation of the charging FET 200. For example, as shown in the configuration of FIG. 3, when a charging current flows from the negative terminal of the cell assembly 10 to the negative terminal of the battery pack, and the charging FET 200 is turned on, the charge/discharge line ( A charging current may flow on L1) and a charging current may not flow on the bypass line L2 provided with the bypass resistor 300.
[62]
In addition, when a charging current flows from the negative terminal of the cell assembly 10 to the negative terminal of the battery pack and the charging FET 200 is turned off, the charging current does not flow on the charge/discharge line L1 and the bypass resistance A charging current may flow on the bypass line L2 provided with the 300.
[63]
Preferably, the bypass resistor 300 according to an embodiment of the present invention has one end of the negative terminal of the cell assembly 10 and the drain terminal of the charging FET 200 as shown in the configuration of FIG. D) A charge/discharge line connected to the first node n1 on the charge/discharge line L1, and the other end connects the negative terminal of the battery pack and the source terminal S of the charging FET 200 ( It may be connected to the second node n2 on L1).
[64]
The processor 400 may receive a voltage value at both ends of the cell assembly 10 from the voltage measurement unit 100 and control an open/close operation of the charging FET 200 based on the received voltage value at both ends. For example, the processor 400 may control turn-on and turn-off operations of the charging FET 200 based on voltage values ​​of both ends of the cell assembly 10.
[65]
Preferably, in the processor 400 according to an embodiment of the present invention, a charging current for charging the cell assembly 10 flows on the charge/discharge line L1, and the voltage values ​​at both ends of the cell assembly 10 are previously When the determined upper limit value is reached, the charging FET 200 may be turned off. For example, the processor 400 may turn off the charging FET 200 when the voltage value of both ends of the cell assembly 10 reaches 14.8V.
[66]
Preferably, in the processor 400 according to an embodiment of the present invention, a charging current for charging the cell assembly 10 flows on the charge/discharge line L1, and the voltage values ​​at both ends of the cell assembly 10 are previously When the determined lower limit value is reached, the charging FET 200 may be turned on. For example, the processor 400 may turn on the charging FET 200 when the voltage value of both ends of the cell assembly 10 reaches 14.3V.
[67]
Preferably, the processor 400 according to the embodiment of the present invention, while the cell assembly 10 is charged by the charging current, the voltage values ​​at both ends of the cell assembly 10 reaching predetermined upper and lower limits, respectively. In this case, the charging FET 200 may be repeatedly turned off and turned on several times. For example, when the voltage values ​​of both ends of the cell assembly 10 reach 14.8V and 14.3V, respectively, the processor 400 may repeatedly turn off and turn on the charging FET 200 several times.
[68]
Preferably, the processor 400 may be electrically connected to the external device 50 so as to transmit and receive electrical signals. For example, the processor 400 may receive an ignition signal from the external device 50. For example, the external device 50 may be an Electronic Control Unit (ECU).
[69]
Preferably, referring to FIGS. 2 and 3, the battery pack according to an embodiment of the present invention may be connected to the starting motor 2. In addition, the battery pack according to an embodiment of the present invention may be connected to the rectifier 5. Through such a configuration, the battery pack according to an embodiment of the present invention may transfer power supplied from the rectifier 5 to the starting motor 2. In addition, the battery pack may be charged through power supplied from the rectifier 5.
[70]
Preferably, the overcharge prevention apparatus according to an embodiment of the present invention may further include a memory device 500 as shown in the configuration of FIG. 3.
[71]
The memory device 500 may be electrically connected to the processor 400 to transmit and receive electrical signals. The memory device 500 may store information necessary for the operation of the overcharge prevention apparatus in advance. For example, the memory device 500 may pre-store a predetermined upper limit value and a lower limit value for the voltage values ​​of both ends of the cell assembly 10.
[72]
On the other hand, the processor 400, in order to perform the above-described operation, a processor 400 known in the art, an application-specific integrated circuit (ASIC), another chipset, a logic circuit, a register, a communication modem and/or data It may be implemented in a form that selectively includes a processing device or the like.
[73]
Meanwhile, there is no particular limitation on the type of the memory device 500 as long as it is a storage medium capable of recording and erasing information. For example, the memory device 500 may be a RAM, a ROM, a register, a hard disk, an optical recording medium, or a magnetic recording medium. The memory device 500 may also be electrically connected to the processor 400 through, for example, a data bus, so that each can be accessed by the processor 400. The memory device 500 may also store and/or update and/or erase and/or transmit a program including various control logics each performed by the processor 400 and/or data generated when the control logic is executed. have.
[74]
[75]
4 is a diagram illustrating a voltage profile of a battery pack and a cell assembly referred to by an overcharge prevention apparatus according to an embodiment of the present invention.
[76]
3 and 4, the voltage measurement unit 100 according to an embodiment of the present invention may further measure a voltage across the battery pack and a voltage across the bypass resistor 300. For example, as shown in the configuration of FIG. 3, the voltage measurement unit 100 may be electrically connected to both ends of the battery pack and both ends of the bypass resistor 300 so as to transmit and receive electrical signals. In addition, the voltage measurement unit 100 may measure the voltage across the battery pack and the voltage across the bypass resistor 300 based on the electrical signals received from both ends of the battery pack and the bypass resistor 300. have.
[77]
Preferably, the processor 400 according to an embodiment of the present invention further receives at least one of a voltage value at both ends of the battery pack and a voltage value at both ends of the bypass resistor 300 from the voltage measurement unit 100, The opening/closing operation of the charging FET 200 may be controlled based on at least one of the received voltage value of both ends of the battery pack and the voltage value of both ends of the bypass resistor 300.
[78]
For example, in the embodiments of FIGS. 3 and 4, the processor 400 may turn on the charging FET 200 when receiving a start signal. In this case, a charging current flows on the charge/discharge line L1 during the charge FET turn-on period (①), and the cell assembly 10 is charged by the charging current, so that the voltage value at both ends of the cell assembly 10 is up to 14.8V It can rise. Subsequently, the processor 400 calculates that the voltage value at both ends of the cell assembly 10 is 14.8V, and when the charging FET 200 is turned off, the voltage value at both ends of the battery pack will rise to 22V, and the charging FET 200 ) Can be turned off. In this case, the processor 400 turns off the charging FET 200 based on the combined resistance value of the internal resistance of the cell assembly 10 and the bypass resistance 300 and the driving power supplied from the rectifier 5. In this case, it is possible to turn off the charging FET 200 by calculating that the voltage value at both ends of the battery pack will rise to 22V. Alternatively, the processor 400 calculates that the voltage value of both ends of the cell assembly 10 is 14.8V, and when the charging FET 200 is turned off, the voltage value of both ends of the bypass resistor 300 is 7.2V. Thus, the charging FET 200 can be turned off. In this case, the processor 400 turns off the charging FET 200 based on the combined resistance value of the internal resistance of the cell assembly 10 and the bypass resistance 300 and the driving power supplied from the rectifier 5. In this case, it is possible to turn off the charging FET 200 by calculating that the voltage value at both ends of the bypass resistor 300 will be applied to 7.2V. For example, in the embodiment of Figure 4, During the charge FET turn-on period (1), a charging current of 2A may flow on the charge/discharge line L1, and during the charge FET turn-off period (2), a charge current of 0.15A may flow on the bypass line L2. In this case, the resistance value of the bypass resistance may be 48Ω.
[79]
Preferably, the processor 400 according to an embodiment of the present invention includes a voltage value corresponding to a difference between a voltage value at both ends of a battery pack and a predetermined upper limit value and a cell assembly when the charging FET 200 is turned off. The opening/closing operation of the charging FET 200 may be controlled so that a voltage corresponding to the sum of the voltage drop values ​​of (10) is applied to the bypass resistor 300.
[80]
For example, in the embodiment of FIG. 4, the processor 400 includes a voltage value a corresponding to a difference between a voltage value V P at both ends of the battery pack and a predetermined upper limit value 14.8V, and a predetermined upper limit value. The voltage (a+b) corresponding to the sum of the voltage drop (b) of the cell assembly 10 corresponding to the difference between (14.8V) and the voltage value (V C ) at both ends of the cell assembly 10 is bypassed. The charging FET 200 may be turned off so as to be applied to the resistor 300. Here, the voltage drop value b of the cell assembly 10 may be a voltage drop component generated due to a decrease in the size of the charging current flowing through the cell assembly 10.
[81]
Preferably, the processor 400 according to an embodiment of the present invention has a voltage value at both ends of the battery pack during a turn-off period in which a charging current flows through the bypass resistor 300 and the charging FET 200 is turned off. The opening/closing operation of the charging FET 200 may be controlled to be kept constant.
[82]
For example, referring to FIGS. 2 to 4, the processor 400 opens and closes the charging FET 200 so that the voltage values ​​at both ends of the battery pack are kept constant based on the driving power supplied from the rectifier 5. Can be controlled. In addition, the processor 400 may control the opening and closing operation of the charging FET 200 so that the voltage value of both ends of the battery pack is kept constant at 22V during the charging FET turn-off period (②). For example, the processor 400 may repeatedly charge the FET several times when the voltage values ​​at both ends of the cell assembly 10 reach predetermined upper and lower limits, respectively, while the cell assembly 10 is being charged by the charging current. 200) can be turned off and on. For example, when the voltage values ​​of both ends of the cell assembly 10 reach 14.8V and 14.3V, respectively, the processor 400 may repeatedly turn off and turn on the charging FET 200 several times.
[83]
Through this configuration, the overcharge prevention device according to an embodiment of the present invention adjusts the charging voltage so that the battery is not overcharged without voltage adjustment by the voltage regulator, and the output voltage of the battery pack can be used as a starting battery. There is an advantage that can be kept constant above a certain voltage.
[84]
The overcharge prevention device according to the present invention can be applied to BMS. That is, the BMS according to the present invention may include the overcharge prevention device according to the present invention described above. In this configuration, at least some of the components of the device for preventing overcharge according to the present invention may be implemented by supplementing or adding functions of the configuration included in the conventional BMS. For example, the processor 400 and the memory device 500 of the overcharge prevention apparatus according to the present invention may be implemented as components of a battery management system (BMS).
[85]
In addition, the overcharge prevention device according to the present invention may be provided in the battery pack. That is, the battery pack according to the present invention may include the overcharge prevention device according to the present invention described above. Here, the battery pack may include one or more secondary batteries, the overcharge prevention device, electrical equipment (including BMS, relays, fuses, etc.), and a case.
[86]
In addition, the overcharge prevention device according to the present invention may be provided in the transmission device. For example, the transmission device may be a scooter, a tractor, or a vehicle including a battery pack equipped with an overcharge prevention device according to the present invention.
[87]
[88]
5 is a flowchart schematically illustrating a method for preventing overcharging according to an embodiment of the present invention.
[89]
In step S100, the processor may receive an ignition signal. For example, the ignition signal may be a starting signal received from an external device.
[90]
Subsequently, in step S110, the processor may turn on the charging FET. In this case, the cell assembly may be charged by charging current flowing on the charging/discharging line.
[91]
Subsequently, in step S120, the processor may measure the voltage across the cell assembly. In addition, the processor may determine whether the voltage value V C at both ends of the cell assembly is equal to or greater than 14.8V, which is a predetermined upper limit value. If the result of step S120 is "YES", the method proceeds to the next step S130, otherwise it may return to step S110.
[92]
Subsequently, in step S130, the processor calculates a difference between the voltage value at both ends of the battery pack and a predetermined upper limit value, and the sum of the calculated value and the voltage drop value V IR of the cell assembly is the voltage value at both ends of the bypass resistor. It can be determined whether it corresponds to (V R ). For example, a voltage value at both ends of the battery pack may be 22V, and a predetermined upper limit value may be 14.8V. If the result of step S130 is "YES", the method proceeds to the next step S140, otherwise it may return to step S110.
[93]
Subsequently, in step S140, the processor may turn off the charging FET.
[94]
Subsequently, in step S150, the processor may measure the voltage across the cell assembly. In addition, the processor may determine whether the voltage value V C at both ends of the cell assembly is less than or equal to 14.3V, which is a predetermined lower limit value. If the result of step S150 is "YES", the method returns to step S110, otherwise it may return to step S140.
[95]
An overcharge prevention method according to an embodiment of the present invention includes a voltage measurement step, a step of controlling an opening/closing operation of a charging FET, and a step of controlling a charging current.
[96]
First, in the voltage measurement step, voltages at both ends of the cell assembly may be measured. Subsequently, the step of controlling the opening/closing operation of the charging FET includes receiving a voltage value at both ends of the cell assembly measured by the voltage measuring step, and based on the received voltage value at one end of the cell assembly and the pack of the battery pack. It is provided on a charge/discharge line electrically connecting between terminals, and an open/close operation of a charge FET configured to control conduction of a charge current flowing through the charge/discharge line may be controlled. Subsequently, in the charging current control step, the charging current may be controlled to flow through a bypass resistor connected in parallel with the charging FET according to an opening/closing operation of the charging FET. Here, the bypass resistor may be provided on a bypass line electrically connected between both ends of the charging FET and electrically parallel to the charging/discharging line.
[97]
Preferably, the step of controlling the opening and closing operation of the charging FET may be repeated several times when the voltage values ​​at both ends of the cell assembly reach a predetermined upper and lower limit values, respectively, while the cell assembly is being charged by the charging current. The charging FET may be turned off and on.
[98]
Preferably, the step of controlling the charging current to flow includes the charging current flowing through the bypass resistor and the voltage values ​​at both ends of the battery pack are kept constant during a turn-off period in which the charging FET is turned off. It is possible to control the opening and closing operation of the charging FET.
[99]
In addition, when the control logic is implemented in software, the processor may be implemented as a set of program modules. In this case, the program module may be stored in a memory device and executed by a processor.
[100]
In addition, at least one or more of the various control logics of the processor are combined, and the combined control logics are written in a computer-readable code system, and there is no particular limitation on the type of the combined control logics as long as the computer-readable access is possible. As an example, the recording medium includes at least one selected from the group including ROM, RAM, register, CD-ROM, magnetic tape, hard disk, floppy disk, and optical data recording device. In addition, the code system can be distributed, stored and executed on computers connected via a network. In addition, functional programs, codes, and segments for implementing the combined control logic can be easily inferred by programmers in the art to which the present invention pertains.
[101]
As described above, although the present invention has been described by the limited embodiments and drawings, the present invention is not limited thereto, and the technical idea of ​​the present invention and the following by those of ordinary skill in the art to which the present invention pertains. It goes without saying that various modifications and variations are possible within the equivalent range of the claims to be described.
[102]
[103]
(Explanation of code)
[104]
1: SLI battery
[105]
10: cell assembly
[106]
50: external device
[107]
100: voltage measurement unit
[108]
200: charging FET
[109]
300: bypass resistance
[110]
400: processor
[111]
500: memory device
[112]
L1: charge/discharge line
[113]
L2: bypass line
Claims
[Claim 1]
An apparatus for preventing overcharging of a cell assembly provided in a battery pack and including at least one secondary battery, the apparatus comprising: a voltage measuring unit configured to measure a voltage across the cell assembly; A charging FET provided on a charge/discharge line electrically connecting one end of the cell assembly and a pack terminal of the battery pack, and configured to control conduction of a charge current flowing through the charge/discharge line; It is provided on a bypass line configured electrically parallel with the charging/discharging line by electrically connecting both ends of the charging FET and connected in parallel with the charging FET, and the charging current flows according to the opening/closing operation of the charging FET. A bypass resistor configured to be; And a processor configured to receive a voltage value at both ends of the cell assembly from the voltage measuring unit and control an opening/closing operation of the charging FET based on the received voltage value at both ends.
[Claim 2]
The method of claim 1, wherein the processor turns off the charging FET when the charging current for charging the cell assembly flows on the charge/discharge line and a voltage value at both ends of the cell assembly reaches a predetermined upper limit value. Overcharge prevention device, characterized in that configured to let.
[Claim 3]
The method of claim 1, wherein the processor turns on the charging FET when the charging current for charging the cell assembly flows on the charge/discharge line and a voltage value at both ends of the cell assembly reaches a predetermined lower limit value. Overcharge prevention device, characterized in that configured to be.
[Claim 4]
The method of claim 1, wherein the processor repeatedly turns off the charging FET several times when the voltage values ​​at both ends of the cell assembly reach predetermined upper and lower limits, respectively, while the cell assembly is being charged by the charging current. And an overcharge prevention device configured to turn on.
[Claim 5]
The apparatus of claim 4, wherein the voltage measuring unit is configured to further measure a voltage across the battery pack and a voltage across the bypass resistor.
[Claim 6]
The method of claim 5, wherein the processor further receives at least one of a voltage value of both ends of the battery pack and a voltage value of both ends of the bypass resistor from the voltage measurement unit, and the received voltage value of both ends of the battery pack and the The overcharge prevention device, characterized in that configured to control the opening and closing operation of the charging FET based on at least one of the voltage values ​​of both ends of the bypass resistor.
[Claim 7]
The method of claim 6, wherein when the charging FET is turned off, the processor comprises a voltage value corresponding to a difference between the voltage value of both ends of the battery pack and the predetermined upper limit value and a sum of the voltage drop value of the cell assembly The overcharge prevention device, characterized in that configured to control the opening and closing operation of the charging FET so that a corresponding voltage is applied to the bypass resistor.
[Claim 8]
The opening/closing operation of the charging FET of claim 7, wherein the processor is configured to maintain a constant voltage value at both ends of the battery pack during a turn-off period in which the charging current flows through the bypass resistor and the charging FET is turned off. Overcharge prevention device, characterized in that configured to control.
[Claim 9]
The method of claim 1, wherein the charging FET includes a gate terminal, a drain terminal, and a source terminal, the gate terminal is electrically connected to the processor, and the drain terminal is electrically connected to a negative terminal of the cell assembly. And the source terminal is configured to be electrically connected to a negative terminal of the battery pack.
[Claim 10]
The method of claim 9, wherein the bypass resistor has one end connected on a charge/discharge line connecting a negative terminal of the cell assembly and a drain terminal of the charging FET, and the other end of the negative terminal and the charging An overcharge prevention device, characterized in that configured to be connected on a charge/discharge line connecting between source terminals of the FET.
[Claim 11]
A BMS comprising an overcharge prevention device according to any one of claims 1 to 10.
[Claim 12]
A battery pack comprising the overcharge prevention device according to any one of claims 1 to 10.
[Claim 13]
A method for preventing overcharging of a cell assembly provided in a battery pack and including at least one secondary battery, the method comprising: measuring a voltage across the cell assembly; Charging/discharging which receives the voltage value of both ends of the cell assembly measured by measuring the voltage, and electrically connects one end of the cell assembly and the pack terminal of the battery pack based on the received voltage value of both ends Controlling an open/close operation of a charging FET provided on a line and configured to control conduction of a charging current flowing through the charging/discharging line; And a bypass resistor electrically connected between both ends of the charging FET to be electrically connected in parallel with the charging/discharging line and connected in parallel with the charging FET. And controlling the charging current to flow.
[Claim 14]
The method of claim 13, wherein the controlling the opening/closing operation of the charging FET is repeated when the voltage values ​​at both ends of the cell assembly reach predetermined upper and lower limits, respectively, while the cell assembly is being charged by the charging current. Overcharge prevention method, characterized in that turning off and on the charging FET several times.
[Claim 15]
The method of claim 13, wherein the controlling of the charging current to flow comprises maintaining a constant voltage value at both ends of the battery pack during a turn-off period in which the charging current flows through the bypass resistor and the charging FET is turned off. Overcharge prevention method, characterized in that controlling the opening and closing operation of the charging FET as possible.