The present invention relates to a device for controlling a transistor. The present invention also relates to a converter comprising a transistor and a transistor as the control device. The present invention also relates to an embedded system comprising such a converter.

In the development of current converters, the use of MOSFET transistors (English acronym of Metal Oxide Semiconductor Field Effect Transistor translated into French as transistor structure field effect transistor metal-oxide-semiconductor) silicon carbide allows improve the performance of such converters. In particular, silicon carbide MOSFETs possible to obtain converters completing multiple conversion functions in a single card. Further, such transistors are used to obtain a better yield compared to MOSFETs in silicon.

However, current driver circuits are found unsuitable for the control of silicon carbide transistors. In particular, such driver circuits typically have a symmetrical drive voltage which may damage the silicon carbide transistors.

There is therefore a need for a control device adapted to control all types of transistors, in particular silicon carbide transistors, without risk of damaging the transistor controlled by said device.

To this end, the invention relates to a control device of a transistor, the device comprising:

- a set of clean cutting generating a first voltage from a DC input voltage, a first control signal and a second control signal, the first control signal and the second control signal being each formed by pulses without temporal overlap between the pulses of said control signals, the first voltage being formed:

• amplitude pulses equal to the input voltage and in phase with the pulses of the first control signal and,

· Pulse amplitude equal to the opposite of the input voltage and in phase with the pulses of the second control signal,

- a transformer connected to the cutting assembly, the transformer comprising two secondary windings, the two secondary windings being connected to one another in a middle point, the first secondary winding being adapted to convert the first voltage to obtain a first converted voltage, the second secondary winding being adapted to convert the first voltage to

obtaining a second converted voltage (V E ), each of the first and second converted voltage being formed:

• of the same sign-amplitude pulses than the first voltage and in phase with the pulses of the first voltage having an amplitude equal to the input voltage, and

• sign amplitude pulses opposite to the first voltage and in phase with the pulses of the first voltage having an amplitude equal to the opposite of the input voltage.

- a clean recovery circuit to extract parts of the same sign of the first converted voltage and opposite the second converted voltage and generating a third voltage from the portions of the same sign extracted,

- a clean flip-flop to generate a fourth voltage based on the converted voltage, the fourth voltage having a high state and a low state, the high state being triggered depending on the sign of the amplitude of the first converted voltage, the state low being triggered depending on the sign of the amplitude of the opposite of the second converted voltage,

- an own set of switching to multiply the third voltage with the normalized condition of the fourth voltage to obtain a multiplied voltage, the multiplied voltage having two states corresponding to the states of the fourth voltage, one of said states having a value equal to the third voltage, the other state having a zero value,

- a shifter adapted to shift the amplitude of the voltage multiplied to obtain a transistor of the control voltage, the control voltage having:

• a peak to peak amplitude equal to the third voltage,

• a high state corresponding to the top of the fourth energized state, and · a low state corresponding to the low state of the fourth voltage and wherein the control voltage has the opposite sign to the sign of the top of the state control voltage.

According to particular embodiments, the control device comprises one or more of the following characteristics, taken in isolation or according to all technically possible combinations:

- each of the rectifier circuit and the flip-flop is connected directly to the transformer;

- each of the first secondary winding and the second secondary winding is adapted to convert the first voltage by multiplying by the same multiplication coefficient;

- the first winding extends between a first terminal and the midpoint and the second winding extends between a second terminal and the midpoint, the rectifying circuit being connected to the midpoint and to each of the first terminal and second terminal, the flip-flop being connected to the first terminal and the second terminal;

- the rectifier circuit comprises:

- a clean rectifier rectifying the first converted voltage and opposite the second converted voltage to obtain a rectified voltage, the rectifier comprising a first diode and a second diode, the first diode being adapted to rectify the first converted voltage, the second diode being adapted to straighten opposite the second converted voltage, and

- a capacitor adapted to be charged for the third voltage.

- the top of the fourth voltage applied state is triggered at the instant of the rising edges of the positive pulses of the first converted voltage, the low voltage of the fourth state being triggered at the instant of the rising edges of the positive pulses of the opposite the second converted voltage;

- the multiplied voltage has two states, the shift circuit comprising a capacitor and a zener diode; the Zener diode being adapted, in one of the states of the multiplied voltage, charging the capacitor to a fifth voltage equal to the third voltage minus the voltage of the Zener diode, and to produce a control voltage of the transistor equal to the voltage of the Zener diode;

-the Zener diode is clean, in the other state of the multiplied voltage, to produce a control voltage of the transistor equal to the opposite of the fifth voltage across the capacitor.

The invention also relates to a converter comprising at least one transistor and at least one control device of the transistor as described above.

The invention also relates to an embedded system comprising such a converter.

Other features and advantages of the invention will become apparent from reading the following description of the invention embodiments, given by way of example only, with reference to the drawings, which are:

- Figure 1 a block diagram of an example of a transistor and a transistor of the control device,

- Figure 2 is a diagrammatic view of an electric circuit including the transistor and the control device of the transistor of Figure 1,

- Figure 3 and 4, a timing diagram of a first control signal, respectively, of a second control signal,

- Figures 5 and 6, a timing diagram of a first voltage, respectively of a first and a second converted voltage,

- Figures 7-1 1, a timing diagram of a third voltage, respectively of a fourth voltage, respectively of a multiplied voltage, respectively of a fifth voltage, respectively to a control voltage, and

- Figure 12, a schematic view of an embedded system.

A transistor 10 and a control device 12 of such a transistor 10 are illustrated in Figures 1 and 2.

In the example illustrated by Figure 2, the transistor 10 comprises a gate G, a source S, a drain D and a base B.

The transistor 10 is, for example, a MOSFET transistor. Such a MOSFET, for example, a silicon transistor or a silicon carbide transistor. Compared to silicon transistors, silicon carbide transistors have a higher breakdown voltage, a higher switching speed and a higher operating temperature.

The control device 12 is adapted to generate a voltage V out of control of the transistor 10 and, more particularly, a voltage V out control the gate of transistor 10.

The control device 12 comprises, successively connected to each other, a voltage source 15, a cutting assembly 16, a transformer 18, a rectifying circuit 20, a latch 22, a switch assembly 24 and an offset circuit 26.

The voltage source 15 is suitable for delivering a DC voltage V in at the entrance of the cutting assembly 16.

The cutting assembly 16 comprises a set of switches controlled by periodic pulse signals for outputting a first voltage V c . The first voltage V c is formed of alternately successive pulses of amplitude equal to the input voltage V in and equal to the opposite of the input voltage V in .

In particular, in the example of Figure 2, the cutting assembly 16 comprises two branches 28, 29 connected in parallel and fed by the input voltage V in . The two branches 28, 29 of the cutting assembly 16 thereby form a bridge, called "H-bridge".

The first part 28 comprises two switches K1 and K3 connected in series in a midpoint M1. The second branch 29 comprises two switches K2 and K4 are connected in series in a midpoint M2. Each switch K1, K2, K3, K4 is controlled by a control input 27A, 27B, 27C, 27D. For example, when the switches K1, K2, K3, K4 are field effect transistors, control inputs 27A, 27B, 27C, 27D correspond to gates of said transistors.

The control inputs 27A, 27B of the switch K1 of the first branch 28 and the switch K4 of the second branch 29 are controlled by a first control signal V A . An example of a timing chart of the first control signal V A is shown in Figure 3.

27C control inputs, 27D K3 switch from the first branch 28 and the switch K2 of the second branch 29 are controlled by a second control signal V B. An example of a timing chart of the second control signal V B is illustrated in Figure 4.

The first control signal V A and the second control signal V B are generated by a pulse generator.

Each of the first control signal V A and V of the second control signal B is formed of constant pulse width L, are repeated with a constant period T such that the aspect ratio L / T of each pulse is strictly less than 50 percent (%). The shape factor of a pulse is the ratio of pulse width to the period between the pulse and a subsequent pulse.

The high level of the pulses of control signals V A , V B corresponds to the closed state of the switch K1, K2, K3, K4 corresponding. The low level of the pulses of control signals V A , V B corresponds to the open state of the switch K1, K2, K3, K4 corresponding. The first control signal V A and the second control signal V B are shifted in time relative to each other so that there is no temporal overlap between pulses of the first control signal V A and V of the second control signal B . This is necessary not to put the voltage source 15 shorted.

Alternatively, the first control signal V A and the second control signal V B are formed of different widths of pulses L A and L B and / or different pulse repetition periods T A and T B . The first control signal V A and the second control signal V B are shifted in time relative to each other so that there is no temporal overlap between pulses of the first control signal V A and V of the second control signal B .

The cutting assembly 16 is configured to output the first voltage V c , illustrated in Figure 2, from the input voltage V in , the first control signal V A and the second control signal V B .

The first voltage V c , illustrated in Figure 5, is formed:

- amplitude of pulses equal to the input voltage V in and in phase with the pulses of the first control signal V A , and

- pulse amplitude equal to the opposite of the input voltage V in and in phase with the pulses of the second control signal V B .

Thus, the transient responses close switches, the first voltage V c is expressed as the following expression:

v c = v zoom .v an - v zoom .v bn

OR

• V in is the input voltage,

• V year is the normalized first control signal (0 or 1), and

· V bn is the second standardized control signal (0 or 1).

The transformer 18 is fed in with the first voltage V c .

The transformer 18 includes a primary winding 31 and two secondary windings 34, 36.

It is understood by the term "winding", an electric coil.

The primary winding 31 is connected directly, on the one hand, to the midpoint M1 between the switches K1 and K3 of the first branch 28 of the cutting assembly 16 and, on the other hand, at point M2 medium between switches K2 and K4 of the second branch 29 of the cutting assembly 16 so as to receive the first voltage V c .

The secondary windings 34 and 36 have the same number of turns. The secondary windings 34 and 36 are connected to each other at a midpoint 38.

The first secondary winding 34 extends between a first 40 and the mid-point terminal 38. The second secondary winding 36 extends between a second terminal 42 and the midpoint 38.

The two secondary windings 34, 36 having the same number of turns, each of the first secondary winding 34 and the second secondary winding 36 in combination with the primary winding 31 is adapted to convert the first voltage V c by multiplying the magnitude of said first voltage V c with a same multiplication coefficient N. the N multiplication coefficient is defined as the ratio of the number of turns of each secondary winding 34, 36 of the transformer 18 to the number of turns of the primary winding 31 of the transformer 18

Thus, the first secondary winding 34 in combination with the primary winding 31 is adapted to convert the first voltage V c for obtaining a first converted voltage V D . The second winding 36 in combination with the primary winding 31 is adapted to convert the first voltage V c for obtaining a second converted voltage V E . Insofar as the N multiplication coefficient is the same for each of the first and the second winding 34, 36, the second converted voltage V E is identical to the first converted voltage V D . An example of a timing diagram of first and second converted voltage V D , V E is illustrated by Figure 6.

Each of the first and second converted voltage V D , V E is formed:

- amplitude of pulses equal to the multiplication factor N multiplied by the first voltage V c and in phase with the pulses of the first voltage V c having an amplitude equal to the input voltage V in , and

- amplitude of pulses equal to the coefficient multiplying N multiplied by the opposite of the first voltage V c and in phase with the pulses of the first voltage V c having an amplitude equal to the opposite of the input voltage V in .

The rectifying circuit 20 is adapted to extract parts of the same sign of each converted voltage V D , V E and outputting a third voltage V F from the parts of the same sign extracted. The expression "parts of the same sign," it is understood the positive or negative component of a signal.

The third voltage V F is a DC voltage of amplitude equal to the peak value of the parts of the same sign for each voltage converted, and therefore the input voltage V in multiplied by the multiplying coefficient N of the transformer 18. An example a timing diagram of the third voltage V F is shown in Figure 7.

The rectifying circuit 20 is connected directly to each secondary winding 34, 36 of the transformer 18. Thus, the control voltage V out generated at the output of device 12 is galvanically isolated from the input voltage V in , and this without adding other isolation devices such as additional transformers or optocouplers.

The rectifying circuit 20 includes a rectifier 43 and a capacitor 44. The rectifying circuit 20 has a terminal connected to the midpoint 38 and a terminal connected to the first terminal 40 so as to be powered by the first converted voltage V D . The rectifying circuit 20 also presents one terminal connected to the midpoint 38 and a terminal connected to the second terminal 42 so as to be supplied from the second converted voltage V E .

The rectifier 43 is adapted to correct the converted voltage V D and opposite the converted voltage V E and charging the capacitor 44 to obtain a third voltage V F .

The rectifier 43 comprises a first diode 45 and second diode 46. The anode of the first diode 45 is connected to the first terminal 40. The anode of the second diode 46 is connected to the second terminal 42. The cathodes of each of the first diode 45 and second diode 46 are interconnected in a connection point 48.

The first diode 45 is adapted to straighten the first converted voltage V D . The second diode 46 is adapted to straighten opposite the second converted voltage V E . In particular, each of the diodes 45, 46 leaving only pass current in one direction, said diodes 45, 46 provide the assembly formed by the capacitor 44 and the load in parallel, a voltage with respect to the midpoint 38 which has a single sign. In the example illustrated by Figure 2, the orientation of the diodes 45, 46 that are the positive portions of the first converted voltage V D and opposite the second converted voltage V Epassing. In a variant in which the diodes 45, 46 are oriented in the opposite direction, the negative portions of the first converted voltage V D and opposite the second converted voltage V E that pass.

The capacitor 44 is connected on the one hand, to the midpoint 38 and, on the other hand, at the connection point 48.

The latch 22 is, for example, an RS flip-flop (short for "Reset" and "Set" translated into French by "Disable" and "Enable").

Flip-flop 22 is directly connected to the transformer 18.

The rocker 22 comprises two inputs and at least one outlet.

The first input of the flip-flop 22 receives the first converted voltage V D . The second input of the flip-flop 22 receives the second converted voltage V E . The flip-flop 22 is also supplied with a power supply 23.

Flip-flop 22 is adapted to output a fourth voltage V H from the converted voltages V D and V E . The fourth voltage V H is a logic signal having a high state and a low state. The first input of the flip-flop 22 is used to deliver the high state of the fourth voltage V H . The second input of the flip-flop 22 allows the delivery of the low state of the fourth voltage V H . An example of a timing chart of the fourth voltage V H is illustrated in Figure 8.

In the example illustrated by the figures, the high state of the fourth voltage V H is triggered at the instant of the rising edges of the positive pulses of the first converted voltage V D . The low state of the fourth voltage V H is triggered at time fronts

amounts of the positive pulses of the opposite of the second converted voltage V E , that is to say, the rising edges of the negative pulses of the second converted voltage V E .

The switching assembly 24 is adapted to multiply the third voltage V F with the standard state of the fourth voltage V H to obtain a multiplied voltage V ,.

The switching assembly 24 is connected to the rectifying circuit 20 so as to receive the third voltage V F . The switching assembly 24 is connected to the rocker 22 so as to receive the fourth voltage V H .

The switch assembly 24 includes two switches 50, 52 and an amplifier 54 in opposite.

The two switches 50, 52 are connected in series in a mid-point 56.

The first switch 50 includes a control input of said switch 50 receiving the fourth voltage V H . The second switch 52 includes a control input of said second switch 52 receiving opposite the fourth voltage V H , since the inverter 54 is connected between the output of the latch 22 and the control input of the second switch 52.

One of the states of the fourth voltage V H turns on (closed) the switch 50 non-conducting (open) the switch 52. The other state of the fourth voltage V H makes non-conducting (open) the switch 50 and passing (closed) the switch 52. for example, the high states of the fourth voltage V H render passing the switch 50 and not through the switch 52, so that the multiplied voltage V is equal to the third voltage V F. the states the bottom of the fourth voltage V H render non-conducting and the switch 50 through the switch 52, so that the multiplied voltage V is equal to zero. An example of a timing diagram of the multiplied voltage V, is shown in Figure 9.

The offset circuit 26 is adapted to shift the amplitude of the multiplied voltage

V to obtain a voltage V out of control of the transistor 10.

The control voltage V out has an amplitude peak to peak equal to the third voltage V F . In addition, the control voltage V out has: a corresponding high state to the first state of the fourth voltage V H and a low state corresponding to the second state of the fourth voltage V H and wherein the control voltage V out is of sign opposite to the sign of the high state.

In the example illustrated by Figure 2, the offset circuit 26 comprises a capacitor 60, a Zener diode 62 and a diode 63.

Offset circuit 26 receives the multiplied voltage V ,.

The capacitor 60 has one terminal connected to the output of the switching assembly 24 to the midpoint 56 between the two switches 50, 52 and a terminal connected to the cathode of the Zener diode 62 at a connection point 64.

The anode of the Zener diode 62 is connected to the anode of the diode 63. Thus, the Zener diode 62 and the diode 63 are arranged head to tail.

The cathode of the diode 63 is connected to the terminal of the capacitor 44 of the rectifying circuit 20 which is connected to the midpoint 38.

The diode 63 is adapted to block the passage of current.

When the first switch 50 is on and the second switch 52 is non-conducting, the multiplied voltage V, is equal to the third voltage V F , the capacitor 60 is then charged to a fifth voltage V equal to the third voltage V F minus the voltage V z of the Zener diode 62 (the voltage drop by the diode 63) and the control voltage V out is equal to the voltage V z of the Zener diode (the voltage drop close to the diode 63 ). The voltage V z of the Zener diode 62 is continuous.

When the first switch 50 is non-conductive and the second switch

52 is conductive, the multiplied voltage V is zero and the control voltage V out is equal to the opposite of the fifth voltage V, that is to say at the voltage V z of the Zener diode (the voltage waste near the diode 63) minus the third voltage V F . The diode 63 prevents the capacitor 60 from discharging into the Zener diode 62 which one would pass and would short-circuit the capacitor 60.

Exemplary timing diagrams of the fifth voltage V and the control voltage V out are illustrated respectively in Figures 10 and January 1.

The above explanation is given for example by neglecting the voltage value of the diode 63. If the voltage of diode 63 was not neglected, the above explanation is valid by replacing the voltage amplitude V z Zener diode 62 by the sum of the amplitudes of the voltage V z of the Zener diode 62 and the voltage drop of the diode 63.

The operation of the control device 12 of the transistor 10 will now be described.

Initially, the cutting assembly 16 generates a first voltage V c from the input voltage V in , the first control signal V A and the second control signal V B .

Then the first secondary winding 34 of transformer 18 in combination with the primary winding 31 converts the first voltage V c for obtaining a first converted voltage V D . Similarly, the second secondary winding 36 of the

transformer 18 in combination with the primary winding 31 converts the first voltage V c for obtaining a second converted voltage V E .

Then, the rectifying circuit 20 extracts portions of the same sign of each converted voltage V D , -V E and outputs a third voltage V F from the parts of the same sign extracted. In particular, the rectifier 43 rectifies the converted voltage V D and opposite the converted voltage V E to obtain the third voltage V F . The capacitor 44 is charged to the third voltage V F .

In parallel, the flip-flop 22 outputs a fourth voltage V H from the converted signals V D and -V S .

Then, the switching assembly 24 multiplies the third voltage V F with the standard state (0 or 1) of the fourth voltage V H to obtain a multiplied voltage V ,.

Finally, the shift circuit 26 shifts the amplitude of the multiplied voltage V, to obtain a voltage V out of control of the transistor 10. In particular, capacitor 60 of lag circuit 26 is charged to a fifth voltage V equal to the third voltage V F minus the voltage V z of the Zener diode 62, to obtain a voltage V out of control of the transistor 10 with two states V z and V Z -V F .

Thus, the controller 12 selects the voltage shift of the control voltage V out so as to obtain a control voltage V out symmetrically or asymmetrically depending on the control transistor 10. This allows to overcome the existing problems with current control devices that are not adapted for controlling a voltage transistors applicant asymmetric control, such as silicon carbide transistors.

In addition, the control device 12 has a low vis-à-vis impedance of the gate of the transistor 10 and this, whatever the transistor of the control stage 10. The control device 12 is thus less sensitive to risks disruption by crosstalk, which may affect the state of charge of the transistor gate

10.

In addition, the processor 18 of the control device 12 does not directly load the gate of transistor 10 but passes through a buffer component which is the capacitor 44 of the rectifying circuit 20, thereby desensitizing the device control 12 resonance phenomena.

The controller 12 also has a relatively small number of components, which keeps a sufficiently compact 12 controller. In particular, the controller 12 allows the power transmission and control in parallel via the transformer 18 to

midpoint 38 without using other components, such as opto-couplers or additional processors to transmit the command.

12 illustrates in addition an on-board system 100, such as an aircraft, comprising a converter 1 1 1. The converter 1 1 1 includes the transistor 10 and the control device 12 of the transistor 10.

CLAIMS

A control device (12) of a transistor (10), the device (12) comprising:

- a cutting assembly (16) adapted to generate a first voltage (V c ) from an input voltage (V in ) continue, a first control signal (V A ) and a second signal control (V B ), the first control signal (V A ) and the second control signal (V B ) being each formed of pulses without temporal overlap between the pulses of said control signals (V A , V B ), the first voltage (V c ) being formed:

• amplitude pulses equal to the input voltage (V in ) and in phase with the pulses of the first control signal (V A ) and,

• amplitude pulse equal to the opposite of the input voltage (V in ) and in phase with the pulses of the second control signal (V B ),

- a transformer (18) connected to the cutting assembly (16), the transformer (18) comprising two secondary windings (34, 36), the two secondary windings (34, 36) being connected to one another in a middle point (38), the first secondary winding (34) being adapted to convert the first voltage (V c ) to obtain a first converted voltage (V D ), the second secondary winding (36) being adapted to convert the first voltage (V c ) to obtain a second converted voltage (V E ), each of the first and second converted voltage (V D , V E ) being formed:

• of the same sign-amplitude pulses than the first voltage (V c ) and in phase with the pulses of the first voltage (V c ) having an amplitude equal to the input voltage (V in ) and

• sign amplitude pulses opposite to the first voltage (V c ) and in phase with the pulses of the first voltage (V c ) having an amplitude equal to the opposite of the input voltage (V in ) .

- a rectifying circuit (20) adapted to extract parts of the same sign of the first converted voltage (V D ) and opposite the second converted voltage (V E ) and generating a third voltage (V F ) to from parts of the same sign extracted,

- a latch (22) adapted to generate a fourth voltage (V H ) from the converted voltages (V D , V E ), the fourth voltage (V H ) having a high state and a low state, the high state being triggered depending on the sign of the amplitude of the first converted voltage (V D ), the low state being triggered depending on the sign of the amplitude of the opposite of the second converted voltage (V E ),

- a switching assembly (24) adapted to multiply the third voltage (V F ) with the standard state of the fourth voltage (V H ) to obtain a multiplied voltage (V,), the multiplied voltage (V,) having two states corresponding to the states of the fourth voltage (V H ), one of said states having a value equal to the third voltage (V F ), the other state having a zero value, and

- an offset circuit (26) capable of shifting the amplitude of the multiplied voltage (V |) to obtain a control voltage (V out ) of the transistor (10), the control voltage (V out ) having:

• a peak to peak amplitude equal to the third voltage (V F ),

• a top corresponding to the top of the fourth voltage Condition (V H ), and

• a low state corresponding to the low state of the fourth voltage (V H ) and wherein the control voltage (V out ) is of opposite sign to the sign of the top of the control voltage state (V out ).

2. - Device (12) according to claim 1, wherein each of the rectifier circuit (20) and the rocker (22) is connected directly to the transformer (18).

3. - Device (12) according to claim 1 or 2, wherein each of the first secondary winding (34) and the second secondary winding (36) is adapted to convert the first voltage (V c ) by multiplying with the same coefficient multiplying (N).

4. - Device (12) according to any one of claims 1 to 3, wherein the first winding (34) extends between a first terminal (40) and the midpoint (38) and the second winding (36) extends between a second terminal (42) and the midpoint (38), the rectifying circuit (20) being connected to the midpoint (38) and each of the first terminal (40) and second terminal (42 ), the rocker (22) being connected to the first terminal (40) and the second terminal (42).

5. - Device (12) according to any one of claims 1 to 4, wherein the rectifying circuit (20) comprises:

- a rectifier (43) adapted to recover the first converted voltage (V D ) and opposite the second converted voltage (V E ) for obtaining a rectified voltage (V F ), the rectifier (43) comprising a first diode ( 45) and a second diode (46), the first diode (45) being adapted to rectify the first converted voltage (V D ), the second diode (46) being adapted to rectify opposite the second converted voltage (V E ), and

- a capacitor (44) adapted to charge for the third voltage (V F ).

6. - Device (12) according to any one of claims 1 to 5, wherein the top of the fourth voltage state (V H ) is triggered at the instant of the rising edges of the positive pulses of the first converted voltage ( V D ), the bottom of the fourth voltage state (V H ) being triggered at the instant of the rising edges of the positive pulses of the opposite of the second converted voltage (V E ).

7. - Device (12) according to any one of claims 1 to 6, wherein the multiplied voltage (V) has two states, the offset circuit (26) comprising a capacitor (60) and a Zener diode (62 ); the Zener diode (62) being adapted, in one of the states of the multiplied voltage (V) charging the capacitor (60) to a fifth voltage (Vj) equal to the third voltage (V F ) minus the voltage (V z ) of the Zener diode (62) and producing a control voltage (V out ) of the transistor (10) equal to the voltage (V z ) of the Zener diode (62).

8. - Device (12) according to claim 7, wherein the Zener diode (62) is adapted, in the other state of the multiplied voltage (V,) to produce a control voltage (Vout) of the transistor (10 ) equal to the opposite of the fifth voltage (V i) present at the terminals of the capacitor (60).

9. - converter comprising at least one transistor (10) and at least one control device (12) of the transistor (10) according to any one of claims 1 to 8.

10. - On-board system comprising a converter according to claim 9.