Claims:1. An automatic level control circuit (100) for controlling output power overshoot in radio frequency (RF) transmitters operating in time division duplex (TDD) mode, said automatic level control circuit comprising:
a voltage variable attenuator (VVA) (104) that attenuates received RF signal for varying output power level of the transmitter output signal; and
a single pole double throw (SPDT) switch (118) coupled to a capacitor (122) placed in feedback path of an operational amplifier (op-amp) integrator (120), said SPDT switch (118) is controlled, on receipt of a control signal, to toggle between a voltage source (124) and a power detector (112) through a resistor (116), wherein the control signal connects the voltage source (124) to the capacitor (122) in receive mode and connects the power detector (112) through resistor (116) in transmit mode for automatic level control (ALC) operation,
wherein the output from the op-amp integrator (120) is connected to the voltage variable attenuator (104) to control and limit the output power level to a predefined level.
2. The automatic level control circuit as claimed in claim 1, wherein the control signal from a microcontroller (126) is used to control the SPDT switch (118) that follows the transmit/receive cycle of operation of TDD wireless communication system.
3. The automatic level control circuit as claimed in claim 1, wherein the input to the capacitor (122) in the op-amp integrator is toggled between the voltage source in transmit and receive modes.
4. The automatic level control circuit as claimed in claim 1, wherein at the transmit mode, forward transmitted RF power is sampled using a directional coupler (108) and the sampled RF power is converted to voltage signal using the power detector (112), wherein the voltage signal is fed to the capacitor (122) through the resistor (116) for automatic level control operation.
5. The automatic level control circuit as claimed in claim 4, wherein the capacitor (122) is charged by the voltage from the power detector (112).
6. The automatic level control circuit as claimed in claim 1, wherein at the receive mode, the capacitor (122) is connected to the voltage source (124) from digital-to-analogue converter (DAC).
7. The automatic level control circuit as claimed in claim 6, wherein the capacitor (122) is charged by the voltage set from the voltage source (124).
8. The automatic level control circuit as claimed in claim 1, wherein the rate at which the output power increases or decreases is determined by the time constant set by the resistors (116) connected to an inverting terminal of the op-amp integrator (120) and the capacitor (122) connected in the feedback path of the op-amp integrator (120) along with the voltage level used to maintain charge on the capacitor during reception mode.
9. The automatic level control circuit as claimed in claim 1, wherein reference voltage level set on the capacitor (122) through the SPDT switch (118) in the receive mode of operation is more than the forward detected voltage level and the reference voltage level is set to any level using digital to analogue converter (DAC) and the microcontroller.
10. The automatic level control circuit as claimed in claim 1, wherein the reference voltage level set on the SPDT switch (118) in receive mode of operation is a constant voltage level for a given output power level and is constant for any or a combination of transmit/receive ratio and RF duty cycle of operation.
, Description:TECHNICAL FIELD
[0001] The present disclosure relates, in general, to a wireless communication system, and more specifically, relates to a device for controlling output power overshoot in RF transmitters.

BACKGROUND
[0002] Automatic level control (ALC) circuits are widely used in wireless transmitters for controlling the output power level of the transmitter. In general, the ALC circuit consists of a coupler placed at the output of a power amplifier (PA) to sample output power. The ALC circuit can include RF detector, integrator and voltage variable attenuator. ALC circuit is used to regulate the PA power response over the operating frequency band and operating temperature range. The DC voltage from detector output drives the input of an op-amp integrator. A reference voltage is given to the non-inverting input of an op-amp. The output of the op-amp integrator is fed to a PIN attenuator to adjust the gain to maintain a constant output power. There is a provision to vary the ALC response time depending on the type of signal fed to PA. For example, for constant envelope signals, an ALC with a faster response time is used and a slower ALC for amplitude varying envelope signals.
[0003] A few existing systems disclose a system for radio power level control using continuously ramping feedback and calibration-free operation of an analogue feedback system with the power level control across a range of power levels of a digital feedback system. The circuit mentioned in this system describes a control system, which utilizes a traditional analogue feedback loop combined with software control applied to the feedback loop by means of a digitally controlled attenuator for closed-loop operation across a broad range of power levels. Another existing system relates to a track and hold circuit within the control loop of the output power level control circuitry of a transmitter power amplifier used in a digital cellular telephone. However, the circuit is to suppress power transients or overshoots that occur at the output of a controlled power amplifier.
[0004] Another existing technique discloses an electronic system used to control RF output power from a power amplifier in TDMA applications using a multiplier that multiplies the output power by itself to provide a DC component which is fed to a variable gain amplifier. However, the system suffers from limitations that requires an additional connection to the power control loop. There is an increased possibility of unwanted transmitter oscillator leakage to the antenna. Squaring and square-rooting functions are done by analogue circuitry.
[0005] There is therefore a need in the art to provide a simple means of using closed loop ALC circuit for time division duplex (TDD) based systems, which can suppress overshoots that occur at the output of the power amplifier.

OBJECTS OF THE PRESENT DISCLOSURE
[0006] An object of the present disclosure relates, in general, to a wireless communication system, and more specifically, relates to device for controlling output power overshoot in RF transmitters.
[0007] Another object of the present disclosure is to provide a device, which can suppress overshoots that occur at the output of a power amplifier.
[0008] Another object of the present disclosure is to provide a device that provides a dynamic range better than 15dB.
[0009] Another object of the present disclosure is to provide a device that operates for any transmit/receive ratio or any RF duty cycle.
[0010] Another object of the present disclosure is to provide a device that controls the ramp-up/ramp-down rates of the output power.
[0011] Another object of the present disclosure is to provide a device that enables smooth ramp-up signal and output power transients are prevented.
[0012] Yet another object of the present disclosure is to provide a device that maintains power at the required level.

SUMMARY
[0013] The present disclosure relates, in general, to a wireless communication system, and more specifically, relates to device for controlling output power overshoot in RF transmitters. The present disclosure relates to the wireless communication system in which a power amplifier suitable for use in communication transmitter/transceiver transmits bursts of signals in accordance with a time division duplex (TDD) or time-division multiple access (TDMA) protocols. A modified automatic level control circuit is used to suppress the power overshoots observed on power output. The automatic level control circuit includes a voltage variable attenuator for varying the output power level of the transmitter output signal depending on the control voltage fed to the voltage variable attenuator from the op-amp integrator circuit in combination with the output power sampler and power detector.
[0014] In an aspect, the present disclosure relates to an automatic level control circuit for controlling output power overshoot in RF transmitters operating in time division duplex (TDD) mode, the automatic level control circuit comprising a voltage variable attenuator (VVA) that attenuate received signal by varying output power level of the transmitter output signal, a single pole double throw (SPDT) switch coupled to a capacitor placed in feedback path of operational amplifier (op-amp) integrator, and the SPDT switch is controlled, on receipt of a control signal, to toggle between a voltage source and voltage from power detector through resistor, wherein the control signal connects the voltage source to the feedback capacitor in receive mode and connects the power detector via resistor in transmit mode for automatic level control (ALC) operation, wherein the output from the op-amp integrator is connected to the voltage variable attenuator to control and limit the output power level to a predefined level.
[0015] According to an embodiment, the control signal from a microcontroller is used to control the SPDT switch that follows the transmit/receive cycle of operation of TDD wireless communication system.
[0016] According to an embodiment, the input to the feedback capacitor in the op-amp integrator is toggled between the voltage source in transmit and receive modes.
[0017] According to an embodiment, at transmit mode, forward transmitted RF power is sampled using a directional coupler and the sampled RF power is converted to voltage signal using the power detector, wherein the voltage signal is fed to the feedback capacitor through the resistor for automatic level control (ALC) operation.
[0018] According to an embodiment, the capacitor is charged by the voltage from the power detector.
[0019] According to an embodiment, wherein at receive mode, the feedback capacitor is connected to the voltage source from digital-to-analogue converter (DAC).
[0020] According to an embodiment, the capacitor is charged by the voltage set from the voltage source.
[0021] According to an embodiment, the rate at which the output power increases or decreases is determined by the time constant set by the resistors connected to an inverting terminal of the op-amp integrator and the capacitor connected in the feedback path of the op-amp integrator along with the voltage level used to maintain charge on feedback capacitor during reception mode.
[0022] According to an embodiment, reference voltage level set on the feedback capacitor through SPDT switch in the receive mode of operation is more than the forward detected voltage level and the reference voltage level is set to any level using digital to analogue converter (DAC) and the microcontroller.
[0023] According to an embodiment, the reference voltage level set on the SPDT switch in receive mode of operation is a constant voltage level for a given output power level and is constant for any or a combination of transmit/receive ratio and RF duty cycle of operation.
[0024] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The following drawings form part of the present specification and are included to further illustrate aspects of the present disclosure. The disclosure may be better understood by reference to the drawings in combination with the detailed description of the specific embodiments presented herein.
[0026] FIG. 1 illustrates an exemplary functional component of automatic level control circuit, in accordance with an embodiment of the present disclosure.
[0027] FIG. 2 illustrates a graphical view of power amplifier output power plot using conventional ALC circuit, in accordance with an embodiment of the present disclosure.
[0028] FIG. 3 illustrates a graphical view of power amplifier output power plot using proposed ALC circuit, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0029] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0030] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0031] The present disclosure relates, in general, to a wireless communication system, and more specifically, relates to device for controlling output power overshoot in RF transmitters. The automatic level control circuit of the present disclosure enables to overcome the limitations of the prior art by suppressing overshoots that occur at the output of the power amplifier.
[0032] The present disclosure relates to the wireless communication system in which a power amplifier suitable for use in communication transmitter/transceiver transmits bursts of signals in accordance with a time division duplex (TDD) or time-division multiple access (TDMA) protocols. A modified automatic level control circuit is used to suppress the power overshoots observed on power output. The automatic level control circuit includes a voltage variable attenuator for varying the output power level of the transmitter output signal depending on the control voltage fed to the voltage variable attenuator from the op-amp integrator circuit in combination with the output power sampler and power detector.
[0033] The term “time division duplex” (TDD) used herein refers to duplex communication links where uplink is separated from downlink by the allocation of different time slots in the same frequency band. The term “time-division multiple access” used herein refers to a digital modulation technique used in radio communication.
[0034] The ALC of the present disclosure enable to overcome the limitations of the prior art by providing an SPDT switch that is used in the feedback path of the op-amp integrator circuit for alternatively connecting the feedback capacitor in the integrator circuit to a voltage source in receive mode and to the power detector during transmit mode. The present disclosure can be described in enabling detail in the following examples, which may represent more than one embodiment of the present disclosure. The description of terms and features related to the present disclosure shall be clear from the embodiments that are illustrated and described; however, the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents of the embodiments are possible within the scope of the present disclosure. Additionally, the invention can include other embodiments that are within the scope of the claims but are not described in detail with respect to the following description.
[0035] FIG. 1 illustrates an exemplary functional component of automatic level control circuit, in accordance with an embodiment of the present disclosure.
[0036] Referring to FIG. 1, automatic level control circuit 100 is configured to limit the power output from the power amplifier to the required level. The present disclosure relates to closed loop power control in wireless transmitters. The present disclosure provides a means to control the power overshoot and maintain power at the required level in closed-loop automatic level control circuits mainly in time division duplex (TDD) based systems. The automatic level control circuit 100 can include voltage variable attenuator (VVA) 104, a power amplifier 106, directional coupler 108, antenna 110, power detector 112, voltage reference source 114, resistor 116, switch 118, integrator 120, capacitor 122, voltage source 124 and microcontroller 126.
[0037] During transmission, radio frequency (RF) signal 102 is fed to the VVA 104, which can attenuate the RF signal by varying the control voltage fed to the VVA 104. The RF signal from the VVA 104 is fed to the power amplifier 106 or a few gain stages followed by the power amplifier 106. The output of the power amplifier 106 is fed to the directional coupler 108 that is used to sample forward RF power and the sampled power is fed to the RF power detector 112. The through path output from the directional coupler 108 is fed to the antenna 110.
[0038] The output of the power detector 112 is fed to the integrator 120 through the resistor 116. In an exemplary embodiment, the integrator 120 can be an operational amplifier (op-amp) with two input terminals and an output terminal. The non-inverting terminal of the operational amplifier is connected to the voltage reference source 114, where the voltage reference source is an output from a digital to analogue converter (DAC).
[0039] The switch (SW1) 118 coupled to the capacitor 122 are placed in a feedback path of op-amp 120. In an exemplary embodiment, switch 118 can be a single pole double throw (SPDT) switch. The normally close (NC) terminal of switch 118 is connected to the voltage source 124 that can be output from the digital-to-analogue converter (DAC) or any voltage derived from supply voltage using potentiometer or resistor-based voltage divider circuit or from a voltage regulator. The normally open (NO) terminal of switch 118 is connected to the resistor 116. The switch (SW1) 118 is controlled using a control signal from the microcontroller 126 or a signal from the radio to activate transmission. The SPDT switch 118 is controlled using the control signal to toggle between the voltage source 124 and voltage from power detector 112 through resistor 116. The control signal connects the voltage source 124 to the feedback capacitor 122 in receive mode and connects the power detector 112 via resistor 116 in transmit mode for automatic level control (ALC) operation.
[0040] The output from switch 118 is connected to the capacitor 122 and the other terminal of the capacitor 122 is connected to the output terminal of the op-amp 120. The output from the op-amp integrator 120 is fed to the VVA 104 voltage control terminal to control the attenuation value of the VVA 104. The switch 118 can be inserted in the feedback path of the op-amp 120 based integrator circuit in the automatic level control loop. The output from the op-amp integrator 120 is connected to the voltage variable attenuator 104 to control and limit the output power level to a predefined level.
[0041] The control signal used to control the SPDT switch 118 that follows the transmit/receive cycle of operation of the TDD wireless communication system. The input to the feedback capacitor 122 in the op-amp integrator 120 is toggled between the voltage source in transmit and receive modes. At transmit mode, forward transmitted RF power is sampled using the directional coupler 108 and the sampled RF power is converted to voltage signal using the power detector 112, where the voltage signal is fed to feedback capacitor 122 via resistor 116 for automatic level control (ALC) operation. At receive mode, the feedback capacitor is connected to the voltage from digital-to-analogue converter (DAC).
[0042] The rate at which the output power increases or decreases is determined by the time constant set by the resistors 116 connected to an inverting terminal of the op-amp integrator 120 and capacitor 122 connected in the feedback path of the op-amp integrator 120 along with the voltage level used to maintain the charge on feedback capacitor during reception mode. The reference voltage level set on the feedback capacitor 122 via SPDT switch 118 in the receive mode of operation is more than the forward detected voltage level and this reference voltage level can be set to any level using DAC and microcontroller. The reference voltage level set on the SPDT switch in the receive mode of operation is a constant voltage level for a given output power level and is also constant for any transmit/receive ratio or any RF duty cycle of operation.
[0043] For example, in an implementation, during the transmission, the burst signal is fed to VVA 104. The burst signal duration depends on the transmit to receive ratio. This ratio can be from 10% to 50%, that is the transmission can be for 10% and remaining 90% in reception mode, for 50% duration in transmit mode and remaining 50% in reception mode. During reception mode, the SW1 118 output is connected to the voltage source 124. In this period the capacitor 122 is charged to voltage set from the voltage source 124. During transmission mode, the switch 118 output is connected to the resistor 116 and the control loop is closed. In this period the capacitor 122 is charged to voltage from the power detector 112 and the ALC gets activated and may limit the output power depending on the reference voltage set on the integrator non-inverting terminal from the voltage source 114. As the transmission shuts off, the switch 118 may get connected to voltage source 124 and the capacitor 122 may get charged to the voltage set from the voltage source 124. So, during this cycle of transmission and reception the charge on the capacitor 122 is always retained and is never discharged completely. So, there may be a smooth ramp-up signal and output power transients are prevented.
[0044] The embodiments of the present disclosure described above provide several advantages. The device 100 of the present disclosure can suppress overshoots that occur at the output of the power amplifier. The device 100 provides dynamic range better than 15dB. The device operates for any transmit/receive ratio or any RF duty cycle, controls the ramp-up/ramp-down rates of the output power and maintains power at the required level.
[0045] FIG. 2 illustrates a graphical view 200 of power amplifier output power plot using conventional ALC circuit, in accordance with an embodiment of the present disclosure. The graphical representation of the power plot of power amplifier output using conventional ALC circuit is indicated in FIG. 2.
[0046] FIG. 3 illustrates a graphical view 300 of power amplifier output power plot using proposed ALC circuit, in accordance with an embodiment of the present disclosure. The graphical representation of the power plot of power amplifier output using proposed ALC circuit shown in FIG. 3. The modified automatic level control circuit 100 is used to suppress the power overshoots observed on power output.
[0047] It will be apparent to those skilled in the art that the device 100 of the disclosure may be provided using some or all of the mentioned features and components without departing from the scope of the present disclosure. While various embodiments of the present disclosure have been illustrated and described herein, it will be clear that the disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the disclosure, as described in the claims.

ADVANTAGES OF THE PRESENT DISCLOSURE
[0048] The present disclosure provides a device, which can suppress overshoots that occur at the output of a power amplifier.
[0049] The present disclosure provides a device that provides a dynamic range better than 15dB.
[0050] The present disclosure provides a device that operates for any transmit/receive ratio or any RF duty cycle.
[0051] The present disclosure provides a device that controls the ramp-up/ramp-down rates of the output power.
[0052] The present disclosure provides a device that enables smooth ramp-up signal and output power transients are prevented.
[0053] The present disclosure provides a device that maintains power at the required level.