Device for resynchronising analog signals obtained by conversion using DDR digital-to-analog converters of synchronised digital signals
The present invention relates to a device for resynchronizing a plurality of analog signals obtained by conversion, using double data rate digital-analog converters, of a plurality of synchronized digital signals at the output of a digital component. It applies, for example, to the field of electronics.
The analog conversion of high-frequency sampling digital signals has always posed problems, notably because of persistent physical phenomena on components internal to the digital-analog converters (DAC). One current solution is to use DACs that operate in accordance with the double data rate protocol, this protocol being better known by the acronym "DDR". The principle of the DDR protocol is to use the rising edges and the falling edges of a clock signal instead of using only its rising edges. Physically, for a DAC to work on digital signals of sampling frequency 2F, the DAC receives a clock signal of frequency 2F as input, which it divides by two by internal mechanisms in order to obtain a clock signal of frequency F. the signal of frequency F is used by the DAC to pace its register stages, notably its input registers receiving the digital signal to be converted. On the one hand, by working on the rising edges and the falling edges of the signal of frequency F in accordance with the DDR protocol, these register stages can process an input digital signal sampled at the frequency 2F. On the other hand, by working at the frequency F instead of working at the frequency 2F, these register stages limit the impact of the persistent physical phenomena. Hereinafter, a DAC operating in accordance with the DDR protocol will be simply referred to as DDR DAC.
In some situations, a number of synchronized digital signals of the same high frequency may have to be converted into analog signals, in such a way that said analog signals must remain synchronized. It may then be advantageous to have a number of DDR DACs receiving one and the same clock signal work in parallel. For example, if we consider two synchronized digital signals of high frequency 2F, these two signals can be supplied as
input to two DDR DACs respectively, the two DDR DACs receiving one and the same clock signal of frequency 2F. However, unfortunately, despite the fact that they receive one and the same clock signal of frequency 2F, there is no reason for the signals of frequency F obtained by division within each of the two DDR DACs to be in phase. The signals of frequency F obtained by division by two within each of the two DDR DACs may be in phase opposition relative to one another. In practice, since these divisions of the signal are performed independently of one another by electronic components which, although identical, are separate, there is no reason for them to give signals that are identical in phase. In the present case, this can be explained by latency times specific to each electronic component which, despite one and the same clock signal cause a time shift on the DDR DACs from the moment they are started up. Thus, the divisions by two may be done on different phases of the clock signal of frequency 2F and the signals of frequency F are in phase opposition. The converted analog signals at the output of the two DDR DACs are then also in phase opposition. Moreover, it should be noted that this phenomenon is not deterministic and that, from one power-on to the next of the two DDR DACs, despite power-on conditions that may seem identical, they may be in phase or in phase opposition in a completely unpredictable way.
The problem seems to have been identified by DDR DAC manufacturers, some of whom have even published technical notes aiming to give guidelines and advice to the users faced with the problem. The main imperative is to ensure, as far as possible, that the DDR DACs are operating in similar environments, for example by notably taking care to subject the lines carrying the clock signal to the same stresses. However, the attempts along these lines conducted by the applicant with the assistance of the manufacturers have been unsuccessful. One manufacturer is considering next producing a device comprising two DDR DACs on one and the same chip which, according to the manufacturer concerned, should resolve the problem since the two DDR DACs will share the startup components suspected of causing the problem. However, this solution is not yet currently available.
In a technical note entitled "Synchronizing Multiple High-Speed Multiplexed DACs for Transmit Applications" available on the website of the
company MAXIM, one solution is disclosed for detecting then correcting the phase opposition between two DDR DACs used to convert to analog two synchronized outputs of a digital component. However, this solution requires the addition of a dedicated component distributed by the company MAXIM.
The aim of the invention is notably to resolve the abovementioned problem, by judiciously exploiting the hardware architecture of the DDR DACs. A subject of the invention is a device for resynchronizing a plurality of analog signals obtained by conversion, using double data rate digital-analog converters, of a plurality of synchronized digital signals of frequency 2F at the output of a digital component. The device comprises at least two double data rate digital-analog converters A and B, each converter being respectively connected to an output channel of the digital component. The converters A and B receive one and the same clock signal of frequency 2F, the converters A and B independently dividing this clock signal by two to obtain a clock signal of frequency F that can be used to pace their output registers and their input registers at the frequency F. The converter B supplies the clock signal at the frequency F to the digital component to pace the output registers of said component, so that the analog signals at the output of the two converters A and B remain synchronized even if the clock signal at the frequency FA obtained by division in the converter A is in phase opposition relative to the clock signal of the frequency FB obtained by division in the converter B.
The converters A and B can each comprise a clock output supplying the clock signal at the frequency F and a clock input that can be used to pace their input registers. The clock output of the converter A may advantageously be connected to its clock input and the clock output of the converter B may advantageously be connected to its clock input. The clock output of the converter B may advantageously also supply the clock signal for the output registers of the digital component.
For example, the digital component may be a serialization module implemented in a programmable gate array. It may, for example, be used to change 56-bit digital signals to 14-bit signals by multiplying the frequency by four. For example, the frequency 2F may be greater than 1000 megahertz.
Other main advantages of the invention are that it does not require a mechanism for initially detecting a phase opposition situation and a mechanism for then correcting any phase opposition. The invention provides a simple, unitary and standalone solution which works identically whether or not there is phase opposition.
Other features and advantages of the invention will become apparent from the following description given in light of the appended drawings which represent:
- figure 1, a block diagram illustration of an example of the hardware architecture of a DDR DAC;
- figure 2, an illustration of examples of signals that can result from the division by two of a clock signal;
- figure 3, a block diagram illustration of an example of a device according to the invention.
Figure 1 is a block diagram illustration of an example of the hardware architecture of a DDR DAC A. The DDR DAC A of figure 1 is an AD9736 type DDR DAC made by Analog Devices. It comprises an element CLKRX which can receive from the outside a clock signal DACCLK at the frequency 2F. An element DIV2 divides the frequency of DACCLK by two to obtain a clock signal DATACLK_OUT of frequency F, the clock signal DATACLKJDUT being on the one hand supplied as output via a component LVDSTX and the clock signal DATACLK_OUT also being supplied to output registers D1A and D2A internal to the DDR DAC A. The registers D1A and D2A are therefore paced at the frequency F. The DDR DAC A of the example of figure 1 also comprises an element LVDSRX1 which can receive from the outside a clock signal DATACLKJN. The clock signal DATACLKJN is supplied to input registers D1 and D2 via a sampling element SD. The registers D1 and D2 can receive, via an element LVDSRX2, a digital signal DACJNPUTA to be converted. To correctly convert the digital signal DACJNPUTA, the registers D1 and D2 must be synchronized with the output
registers of the external component supplying the signal DACJNPUTA. In other words, the clock signal DATACLKJN must be identical to the signal that paces the output registers of a component which supplies the digital signal DACJNPUTA to be converted. The DDR DAC A also comprises a multiplexer MUXA which can be used to alternately process the registers D1A and D2A and to supply the data that they contain to an element DACCORE. The element DACCORE supplies as output of the DDR DAC A an analog signal DAC_OUTPUTA which is the conversion of the signal DACJNPUTA. The architecture of the DDR DAC A appears clearly separated into two domains: a domain in which the register stages are paced at the DATACLKJN frequency and a domain in which the register stages are paced at the DACCLK frequency. The invention sets out to judiciously exploit this property that is found in most DDR DACs.
Figure 2 illustrates the two signals DATACLK_OUT that can result from the division by two of the signal DACCLK by the component DIV2. As explained previously, the division performed by DIV2 can be done on different phases of the signal DACCLK of frequency 2F, and in a non-deterministic manner. Thus, two signals DATACLKJDUT may result from the division of the signal DACCLK: either a signal DATACLK_OUT of frequency FA or a signal DATACLKJDUT of frequency FB, the frequencies FA and FB being in phase opposition.
Figure 3 is a block diagram illustration of an example of a device according to the invention. The device comprises two identical DDR DACs of AD9736 type, the DDR DAC A of figure 1 and a DDR DAC B, for the parallel processing of two synchronized digital signals DACJNPUTA and DACJNPUTB, each of 14 bits. These two synchronized digital signals DACJNPUTA and DACJNPUTB may be supplied by a programmable gate array, or FPGA (acronym for field-programmable gate array). For example, the FPGA may be from the SC25M family made by Lattice. It may include two FIFO (first-in first-out) type memory buffers BUF A and BUF B able to receive, for example, two data streams each of 56 bits, and in a
discontinuous manner. The FPGA may include a data serialization module SER, to which the 56-bit data streams are transferred. For example, the module SER may be used to change from two 300 megahertz 56-bit buses at the input to two 14-bit buses with a clock four times faster at the output, that is to say, a 1200 megahertz clock.
The DDR DAC A and the DDR DAC B must therefore convert the two 1200 megahertz 14-bit synchronized digital signals, so that the two analog signals DACJDUTPUTA and DACJDUTPUTB at the output of the DDR DAC A and of DDR DAC B respectively are always synchronized. For this, the DDR DAC A and the DDR DAC B receive as input from their respective CLKRX elements, the same clock signal DACCLK at the frequency 2F of figure 2, with 2F = 1200 megahertz. In the example of figure 3, the output signal DATACLKJDUT at F=600 megahertz from the DDR DAC B can advantageously be supplied as clock signal for the output registers of the module SER. In practice, since the outputs of the module SER are processed by DDR components, namely the DDR DAC A and the DDR DAC B, a clock at 600 megahertz instead of 1200 megahertz is sufficient. This is because, as explained previously, a 600 megahertz clock used in DDR mode is equivalent to a 1200 megahertz clock used for simple data timing. Thus, according to the invention, the data are sent to the output of the module SER with a synchronous clock from the DDR DAC B, which will hereinafter be referred to "reference converter". Moreover, each of the clock signals at the outputs DATACLK_OUT can be returned to its own converter: the output signal at the frequency F = 600 megahertz DATACLKJDUT from the DDR DAC B is supplied as clock signal to the DATACLKJN input of the DDR DAC B and the output signal at the frequency F = 600 megahertz DATACLKJDUT from the DDR DAC A is supplied as clock signal to the DATACLKJN input of the DDR DAC A. However, as explained previously, despite the fact that they receive the same clock signal DACCLK at the frequency 2F = 1200 megahertz and the fact that the lines carrying the signal are subject to the same stresses, there is no reason for the two signals of frequency F = 600 megahertz available on the respective DATACLKJDUT outputs of the DDR DAC A and of the DDR DAC B to be in phase.
In a first case, which is that illustrated by figure 3, they may be in phase opposition, the signal at the DATACLKJDUT output of the DDR DAC
A possibly being at the frequency FA of figure 2 and the signal at the DATACLKJDUT output of the DDR DAC B possibly being at the frequency FB of figure 2. As illustrated by figure 1, the multiplexer MUXA alternately processes the data at the output of the register D1A then the data at the output of the register D2A, the registers D1A and D2A and the multiplexer MUXA themselves being paced internally in the DDR DAC A at the frequency FA. Similarly, the DDR DAC B includes a multiplexer MUXB which alternately processes the data at the output of a register D1B then the data at the output of a register D2B, the registers D1B and D2B and the multiplexer MUXB themselves being paced internally in the DDR DAC B at the frequency FB. However, since, by assumption, FA and FB are in phase opposition, then MUXA and MUXB work in a symmetrical or inverted manner: MUXA processes D1A when MUXB processes D2B and MUXA process D2A when MUXB processes D1B. Now, the outputs of the module SER are paced at the frequency FB, the DDR DAC B being the reference converter supplying the clock signal to the module SER. Therefore, the input registers D1 and D2 of the DDR DAC A paced at FA also work in an inverted or symmetrical manner relative to the output registers of the module SER: the reference D1A ends up containing what the register D2A should have contained and the register D2A ends up containing what the register D1A should have contained. This inversion of the content of the registers D1A and D2A, combined with the inversion in the sequencing of the processing of the registers D1A and D2A by MUXA, makes it possible to reestablish synchronization. In a way, one inversion cancels out the other.
In a second case, the signals of frequency F = 600 megahertz available on the respective DATACLKJDUT outputs of the DDR DAC A and of the DDR DAC B may be in phase, the signal at the DATACLKJDUT output of the DDR DAC A and the signal at the DATACLKJDUT output of the DDR DAC B possibly being at the same frequency FA of figure 2. In this case, there is no longer any inversion and the synchronization is never broken.
In a second case, the signals of frequency F = 600 megahertz available on the respective DATACLKJDUT outputs of the DDR DAC A and of the DDR DAC B may be in phase, the signal at the DATACLKJDUT output of the DDR DAC A and the signal at the DATACLKJDUT output of the DDR
DAC B possibly being at the same frequency FB of figure 2. In this case also, there is no longer any inversion and the synchronization is never broken.
Thus, by virtue of the invention, the converted analog signals at the output of both DDR DAC A and DDR DAC B are always in phase and are never desynchronized.
In addition to the advantage of offering a simple, unitary, standalone and inexpensive solution, other main advantages of the invention described previously are that it can be applied regardless of the number of DDR DACs used, just one of them constituting the reference converter for all the others. Since it is frequency-independent, it can also be applied to high frequencies.

WE CLAIMS
1. A device for resynchronizing a plurality of analog signals
(DAC_OUTPUTA, DAC_OUTPUTB) obtained by conversion, using
double data rate digital-analog converters, of a plurality of synchronized
digital signals (DACJNPUTA, DACJNPUTB) of frequency 2F at the
output of a digital component (SER):
- the device comprising at least two double data rate digital-analog converters A and B, each converter being respectively connected to an output channel of the digital component;
- the converters A and B receiving one and the same clock signal of frequency 2F, the converters A and B independently dividing this clock signal by two to obtain a clock signal of frequency F that can be used to pace their output registers (D1A, D2A) and their input registers (D1, D2) at the frequency F;
the device being characterized in that the converter B supplies the clock signal at the frequency F to the digital component to pace the output registers of said component, so that the analog signals (DAC_OUTPUTA, DACJDUTPUTB) at the output of the two converters A and B remain synchronized even if the clock signal at the frequency FA obtained by division in the converter A is in phase opposition relative to the clock signal at the frequency FB obtained by division in the converter B.
2. The device as claimed in claim 1, characterized in that:
- the converters A and B each comprise a clock output (DATACLK_OUT) supplying the clock signal at the frequency F;
- the converters A and B each comprise a clock input (DATACLK_IN) used to pace their input registers (D1, D2);
- the clock output of the converter A is connected to the clock input of the converter A and the clock output of the converter B is connected to the clock input of the converter B;
- the clock output of the converter B supplies the clock signal for the
output registers of the digital component (SER).
3. The device as claimed in claim 1, characterized in that the digital
component is a serialization module (SER).
4. The device as claimed in claim 3, characterized in that the serialization module (SER) is implemented in a programmable gate array (FPGA).
5. The device as claimed in claim 3, characterized in that the serialization module (SER) can be used to change 56-bit digital signals to 14-bit signals by multiplying the frequency of the signals by four.
6. The device as claimed in claim 3, characterized in that the frequency 2F is greater than 1000 megahertz.